[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap4 / clocks.c

/*
 *
 * Clock initialization for OMAP4
 *
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 *
 * Aneesh V <aneesh@ti.com>
 *
 * Based on previous work by:
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *	Rajendra Nayak <rnayak@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/omap_common.h>
#include <asm/gpio.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>

#ifndef CONFIG_SPL_BUILD
/*
 * printing to console doesn't work unless
 * this code is executed from SPL
 */
#define printf(fmt, args...)
#define puts(s)
#endif /* !CONFIG_SPL_BUILD */

/*
 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
 * We set the maximum voltages allowed here because Smart-Reflex is not
 * enabled in bootloader. Voltage initialization in the kernel will set
 * these to the nominal values after enabling Smart-Reflex
 */
void scale_vcores(void)
{
	u32 volt, omap_rev;

	omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);

	omap_rev = omap_revision();

	/*
	 * Scale Voltage rails:
	 * 1. VDD_CORE
	 * 3. VDD_MPU
	 * 3. VDD_IVA
	 */
	if (omap_rev < OMAP4460_ES1_0) {
		/*
		 * OMAP4430:
		 * VDD_CORE = TWL6030 VCORE3
		 * VDD_MPU = TWL6030 VCORE1
		 * VDD_IVA = TWL6030 VCORE2
		 */
		volt = 1200;
		do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);

		/*
		 * note on VDD_MPU:
		 * Setting a high voltage for Nitro mode as smart reflex is not
		 * enabled. We use the maximum possible value in the AVS range
		 * because the next higher voltage in the discrete range
		 * (code >= 0b111010) is way too high.
		 */
		volt = 1325;
		do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
		volt = 1200;
		do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);

	} else {
		/*
		 * OMAP4460:
		 * VDD_CORE = TWL6030 VCORE1
		 * VDD_MPU = TPS62361
		 * VDD_IVA = TWL6030 VCORE2
		 */
		volt = 1200;
		do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
		/* TPS62361 */
		volt = 1203;
		do_scale_tps62361(TPS62361_VSEL0_GPIO,
				  TPS62361_REG_ADDR_SET1, volt);
		/* VCORE 2 - supplies vdd_iva */
		volt = 1200;
		do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
	}
}

u32 get_offset_code(u32 offset)
{
	u32 offset_code, step = 12660; /* 12.66 mV represented in uV */

	if (omap_revision() == OMAP4430_ES1_0)
		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
	else
		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;

	offset_code = (offset + step - 1) / step;

	/* The code starts at 1 not 0 */
	return ++offset_code;
}
Commit	Line	Data
2e5ba489 S	1	/*
	2	*
	3	* Clock initialization for OMAP4
	4	*
	5	* (C) Copyright 2010
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Aneesh V <aneesh@ti.com>
	9	*
	10	* Based on previous work by:
	11	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	12	* Rajendra Nayak <rnayak@ti.com>
	13	*
	14	* See file CREDITS for list of people who contributed to this
	15	* project.
	16	*
	17	* This program is free software; you can redistribute it and/or
	18	* modify it under the terms of the GNU General Public License as
	19	* published by the Free Software Foundation; either version 2 of
	20	* the License, or (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; if not, write to the Free Software
	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	30	* MA 02111-1307 USA
	31	*/
	32	#include <common.h>
	33	#include <asm/omap_common.h>
	34	#include <asm/gpio.h>
	35	#include <asm/arch/clocks.h>
	36	#include <asm/arch/sys_proto.h>
	37	#include <asm/utils.h>
	38	#include <asm/omap_gpio.h>
	39
	40	#ifndef CONFIG_SPL_BUILD
	41	/*
	42	* printing to console doesn't work unless
	43	* this code is executed from SPL
	44	*/
	45	#define printf(fmt, args...)
	46	#define puts(s)
f281f299	47	#endif /* !CONFIG_SPL_BUILD */
2e5ba489	48
2e5ba489 S	49	/*
	50	* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
	51	* We set the maximum voltages allowed here because Smart-Reflex is not
	52	* enabled in bootloader. Voltage initialization in the kernel will set
	53	* these to the nominal values after enabling Smart-Reflex
	54	*/
	55	void scale_vcores(void)
	56	{
	57	u32 volt, omap_rev;
	58
a78274b2	59	omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
2e5ba489 S	60
2e5ba489 S	61	omap_rev = omap_revision();
2e5ba489 S	62
2e5ba489 S	63	/*
f2ae6c1a NM	64	* Scale Voltage rails:
	65	* 1. VDD_CORE
	66	* 3. VDD_MPU
	67	* 3. VDD_IVA
2e5ba489 S	68	*/
2e5ba489 S	69	if (omap_rev < OMAP4460_ES1_0) {
f2ae6c1a NM	70	/*
	71	* OMAP4430:
	72	* VDD_CORE = TWL6030 VCORE3
	73	* VDD_MPU = TWL6030 VCORE1
	74	* VDD_IVA = TWL6030 VCORE2
	75	*/
	76	volt = 1200;
	77	do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
	78
	79	/*
	80	* note on VDD_MPU:
	81	* Setting a high voltage for Nitro mode as smart reflex is not
	82	* enabled. We use the maximum possible value in the AVS range
	83	* because the next higher voltage in the discrete range
	84	* (code >= 0b111010) is way too high.
	85	*/
2e5ba489 S	86	volt = 1325;
2e5ba489 S	87	do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
f2ae6c1a NM	88	volt = 1200;
	89	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
	90
2e5ba489	91	} else {
f2ae6c1a NM	92	/*
	93	* OMAP4460:
	94	* VDD_CORE = TWL6030 VCORE1
	95	* VDD_MPU = TPS62361
	96	* VDD_IVA = TWL6030 VCORE2
	97	*/
2e5ba489 S	98	volt = 1200;
2e5ba489 S	99	do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
f2ae6c1a NM	100	/* TPS62361 */
	101	volt = 1203;
	102	do_scale_tps62361(TPS62361_VSEL0_GPIO,
	103	TPS62361_REG_ADDR_SET1, volt);
	104	/* VCORE 2 - supplies vdd_iva */
2e5ba489	105	volt = 1200;
f2ae6c1a	106	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
2e5ba489 S	107	}
	108	}
	109
8de17f46 S	110	u32 get_offset_code(u32 offset)
	111	{
	112	u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
	113
	114	if (omap_revision() == OMAP4430_ES1_0)
	115	offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
	116	else
	117	offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
	118
	119	offset_code = (offset + step - 1) / step;
	120
	121	/* The code starts at 1 not 0 */
	122	return ++offset_code;
	123	}