[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap5 / hwinit.c

/*
 *
 * Functions for omap5 based boards.
 *
 * (C) Copyright 2011
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *	Aneesh V	<aneesh@ti.com>
 *	Steve Sakoman	<steve@sakoman.com>
 *	Sricharan	<r.sricharan@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include <asm/omap_common.h>

DECLARE_GLOBAL_DATA_PTR;

u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;

static struct gpio_bank gpio_bank_54xx[8] = {
	{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;

#ifdef CONFIG_SPL_BUILD
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
}

/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
	u32 io_settings = 0;
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);
	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);

	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);

	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);

	/* omap5432 does not use lpddr2 */
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);

	writel(ioregs->ctrl_emif_sdram_config_ext,
	       (*ctrl)->control_emif1_sdram_config_ext);
	writel(ioregs->ctrl_emif_sdram_config_ext,
	       (*ctrl)->control_emif2_sdram_config_ext);

	if (is_omap54xx()) {
		/* Disable DLL select */
		io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
							& 0xFFEFFFFF);
		writel(io_settings,
			(*ctrl)->control_port_emif1_sdram_config);

		io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
							& 0xFFEFFFFF);
		writel(io_settings,
			(*ctrl)->control_port_emif2_sdram_config);
	} else {
		writel(ioregs->ctrl_ddr_ctrl_ext_0,
				(*ctrl)->control_ddr_control_ext_0);
	}
}

/*
 * Some tuning of IOs for optimal power and performance
 */
void do_io_settings(void)
{
	u32 io_settings = 0, mask = 0;

	/* Impedance settings EMMC, C2C 1,2, hsi2 */
	mask = (ds_mask << 2) | (ds_mask << 8) |
		(ds_mask << 16) | (ds_mask << 18);
	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
				(~mask);
	io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
			(ds_45_ohm << 18) | (ds_60_ohm << 2);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_0);

	/* Impedance settings Mcspi2 */
	mask = (ds_mask << 30);
	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
			(~mask);
	io_settings |= (ds_60_ohm << 30);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_1);

	/* Impedance settings C2C 3,4 */
	mask = (ds_mask << 14) | (ds_mask << 16);
	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
			(~mask);
	io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_2);

	/* Slew rate settings EMMC, C2C 1,2 */
	mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
			(~mask);
	io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_0);

	/* Slew rate settings hsi2, Mcspi2 */
	mask = (sc_mask << 24) | (sc_mask << 28);
	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
			(~mask);
	io_settings |= (sc_fast << 28) | (sc_fast << 24);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_1);

	/* Slew rate settings C2C 3,4 */
	mask = (sc_mask << 16) | (sc_mask << 18);
	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
			(~mask);
	io_settings |= (sc_na << 16) | (sc_na << 18);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_2);

	/* impedance and slew rate settings for usb */
	mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
		(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
			(~mask);
	io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
		       (ds_60_ohm << 23) | (sc_fast << 20) |
		       (sc_fast << 17) | (sc_fast << 14);
	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);

	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
		io_settings_lpddr2();
	else
		io_settings_ddr3();

	/* Efuse settings */
	writel(EFUSE_1, (*ctrl)->control_efuse_1);
	writel(EFUSE_2, (*ctrl)->control_efuse_2);
	writel(EFUSE_3, (*ctrl)->control_efuse_3);
	writel(EFUSE_4, (*ctrl)->control_efuse_4);
}

static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
	{0x45, 0x1},	/* 12 MHz   */
	{-1, -1},	/* 13 MHz   */
	{0x63, 0x2},	/* 16.8 MHz */
	{0x57, 0x2},	/* 19.2 MHz */
	{0x20, 0x1},	/* 26 MHz   */
	{-1, -1},	/* 27 MHz   */
	{0x41, 0x3}	/* 38.4 MHz */
};

void srcomp_enable(void)
{
	u32 srcomp_value, mul_factor, div_factor, clk_val, i;
	u32 sysclk_ind	= get_sys_clk_index();
	u32 omap_rev	= omap_revision();

	if (!is_omap54xx())
		return;

	mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
	div_factor = srcomp_parameters[sysclk_ind].divide_factor;

	for (i = 0; i < 4; i++) {
		srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
		srcomp_value &=
			~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
			(div_factor << DIVIDE_FACTOR_XS_SHIFT);
		writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
	}

	if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);

		for (i = 0; i < 4; i++) {
			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~PWRDWN_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);

			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
				& SRCODE_READ_XS_MASK) >>
				SRCODE_READ_XS_SHIFT) == 0)
				;

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~OVERRIDE_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}
	} else {
		srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
				  DIVIDE_FACTOR_XS_MASK);
		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
				(div_factor << DIVIDE_FACTOR_XS_SHIFT);
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		for (i = 0; i < 4; i++) {
			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~OVERRIDE_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~OVERRIDE_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);

		clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);

		for (i = 0; i < 4; i++) {
			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
				& SRCODE_READ_XS_MASK) >>
				SRCODE_READ_XS_SHIFT) == 0)
				;

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}

		while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
			SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
			;

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	}
}
#endif

void config_data_eye_leveling_samples(u32 emif_base)
{
	/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
	if (emif_base == EMIF1_BASE)
		writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
			(*ctrl)->control_emif1_sdram_config_ext);
	else if (emif_base == EMIF2_BASE)
		writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
			(*ctrl)->control_emif2_sdram_config_ext);
}

void init_omap_revision(void)
{
	/*
	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
	 * Also, ES1 and ES2 have different ARM revisions
	 * So use ARM revision for identification
	 */
	unsigned int rev = cortex_rev();

	switch (readl(CONTROL_ID_CODE)) {
	case OMAP5430_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = OMAP5430_ES1_0;
		if (rev == MIDR_CORTEX_A15_R2P2)
			*omap_si_rev = OMAP5430_ES2_0;
		break;
	case OMAP5432_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = OMAP5432_ES1_0;
		if (rev == MIDR_CORTEX_A15_R2P2)
			*omap_si_rev = OMAP5432_ES2_0;
		break;
	case OMAP5430_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = OMAP5430_ES2_0;
		break;
	case OMAP5432_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = OMAP5432_ES2_0;
		break;
	case DRA752_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = DRA752_ES1_0;
		break;
	default:
		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
	}
}

void reset_cpu(ulong ignored)
{
	u32 omap_rev = omap_revision();

	/*
	 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
	 * So use cold reset in case instead.
	 */
	if (omap_rev == OMAP5430_ES1_0)
		writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
	else
		writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
}

u32 warm_reset(void)
{
	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}

void setup_warmreset_time(void)
{
	u32 rst_time, rst_val;

#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
	rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
#else
	rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
#endif
	rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;

	if (rst_time > RSTTIME1_MASK)
		rst_time = RSTTIME1_MASK;

	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
	rst_val |= rst_time;
	writel(rst_val, (*prcm)->prm_rsttime);
}
Commit	Line	Data
508a58fa S	1	/*
	2	*
	3	* Functions for omap5 based boards.
	4	*
	5	* (C) Copyright 2011
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Aneesh V <aneesh@ti.com>
	10	* Steve Sakoman <steve@sakoman.com>
	11	* Sricharan <r.sricharan@ti.com>
	12	*
	13	* See file CREDITS for list of people who contributed to this
	14	* project.
	15	*
	16	* This program is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of
	19	* the License, or (at your option) any later version.
	20	*
	21	* This program is distributed in the hope that it will be useful,
	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* You should have received a copy of the GNU General Public License
	27	* along with this program; if not, write to the Free Software
	28	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	29	* MA 02111-1307 USA
	30	*/
	31	#include <common.h>
	32	#include <asm/armv7.h>
	33	#include <asm/arch/cpu.h>
	34	#include <asm/arch/sys_proto.h>
af1d002f	35	#include <asm/arch/clock.h>
508a58fa S	36	#include <asm/sizes.h>
	37	#include <asm/utils.h>
	38	#include <asm/arch/gpio.h>
784ab7c5	39	#include <asm/emif.h>
f92f2277	40	#include <asm/omap_common.h>
508a58fa S	41
	42	DECLARE_GLOBAL_DATA_PTR;
	43
f92f2277	44	u32 const omap_si_rev = (u32 )OMAP_SRAM_SCRATCH_OMAP_REV;
508a58fa	45
87bd05d7	46	static struct gpio_bank gpio_bank_54xx[8] = {
508a58fa S	47	{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
	48	{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
	49	{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
	50	{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
	51	{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
	52	{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
87bd05d7 AL	53	{ (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
87bd05d7 AL	54	{ (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
508a58fa S	55	};
	56
	57	const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
	58
	59	#ifdef CONFIG_SPL_BUILD
eb4e18e8 LV	60	/* LPDDR2 specific IO settings */
	61	static void io_settings_lpddr2(void)
	62	{
ef1697e9 LV	63	const struct ctrl_ioregs *ioregs;
	64
	65	get_ioregs(&ioregs);
	66	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	67	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
	68	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	69	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
	70	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
	71	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	72	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	73	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	74	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
eb4e18e8 LV	75	}
	76
	77	/* DDR3 specific IO settings */
	78	static void io_settings_ddr3(void)
	79	{
	80	u32 io_settings = 0;
ef1697e9	81	const struct ctrl_ioregs *ioregs;
eb4e18e8	82
ef1697e9 LV	83	get_ioregs(&ioregs);
	84	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
	85	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	86	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
eb4e18e8	87
ef1697e9 LV	88	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
	89	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	90	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
eb4e18e8	91
ef1697e9 LV	92	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	93	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	94	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
eb4e18e8 LV	95
eb4e18e8 LV	96	/* omap5432 does not use lpddr2 */
ef1697e9 LV	97	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
ef1697e9 LV	98	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
eb4e18e8	99
ef1697e9 LV	100	writel(ioregs->ctrl_emif_sdram_config_ext,
	101	(*ctrl)->control_emif1_sdram_config_ext);
	102	writel(ioregs->ctrl_emif_sdram_config_ext,
	103	(*ctrl)->control_emif2_sdram_config_ext);
eb4e18e8	104
92b0482c S	105	if (is_omap54xx()) {
	106	/* Disable DLL select */
	107	io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
eb4e18e8	108	& 0xFFEFFFFF);
92b0482c S	109	writel(io_settings,
92b0482c S	110	(*ctrl)->control_port_emif1_sdram_config);
eb4e18e8	111
92b0482c	112	io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
eb4e18e8	113	& 0xFFEFFFFF);
92b0482c S	114	writel(io_settings,
	115	(*ctrl)->control_port_emif2_sdram_config);
	116	} else {
	117	writel(ioregs->ctrl_ddr_ctrl_ext_0,
	118	(*ctrl)->control_ddr_control_ext_0);
	119	}
eb4e18e8 LV	120	}
eb4e18e8 LV	121
508a58fa S	122	/*
	123	* Some tuning of IOs for optimal power and performance
	124	*/
	125	void do_io_settings(void)
	126	{
6ad8d67d	127	u32 io_settings = 0, mask = 0;
6ad8d67d S	128
	129	/* Impedance settings EMMC, C2C 1,2, hsi2 */
	130	mask = (ds_mask << 2) \| (ds_mask << 8) \|
	131	(ds_mask << 16) \| (ds_mask << 18);
c43c8339	132	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
6ad8d67d S	133	(~mask);
	134	io_settings \|= (ds_60_ohm << 8) \| (ds_45_ohm << 16) \|
	135	(ds_45_ohm << 18) \| (ds_60_ohm << 2);
c43c8339	136	writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
6ad8d67d S	137
	138	/* Impedance settings Mcspi2 */
	139	mask = (ds_mask << 30);
c43c8339	140	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
6ad8d67d S	141	(~mask);
6ad8d67d S	142	io_settings \|= (ds_60_ohm << 30);
c43c8339	143	writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
6ad8d67d S	144
	145	/* Impedance settings C2C 3,4 */
	146	mask = (ds_mask << 14) \| (ds_mask << 16);
c43c8339	147	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
6ad8d67d S	148	(~mask);
6ad8d67d S	149	io_settings \|= (ds_45_ohm << 14) \| (ds_45_ohm << 16);
c43c8339	150	writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
6ad8d67d S	151
	152	/* Slew rate settings EMMC, C2C 1,2 */
	153	mask = (sc_mask << 8) \| (sc_mask << 16) \| (sc_mask << 18);
c43c8339	154	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
6ad8d67d S	155	(~mask);
6ad8d67d S	156	io_settings \|= (sc_fast << 8) \| (sc_na << 16) \| (sc_na << 18);
c43c8339	157	writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
6ad8d67d S	158
	159	/* Slew rate settings hsi2, Mcspi2 */
	160	mask = (sc_mask << 24) \| (sc_mask << 28);
c43c8339	161	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
6ad8d67d S	162	(~mask);
6ad8d67d S	163	io_settings \|= (sc_fast << 28) \| (sc_fast << 24);
c43c8339	164	writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
6ad8d67d S	165
	166	/* Slew rate settings C2C 3,4 */
	167	mask = (sc_mask << 16) \| (sc_mask << 18);
c43c8339	168	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
6ad8d67d S	169	(~mask);
6ad8d67d S	170	io_settings \|= (sc_na << 16) \| (sc_na << 18);
c43c8339	171	writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
6ad8d67d S	172
	173	/* impedance and slew rate settings for usb */
	174	mask = (usb_i_mask << 29) \| (usb_i_mask << 26) \| (usb_i_mask << 23) \|
	175	(usb_i_mask << 20) \| (usb_i_mask << 17) \| (usb_i_mask << 14);
c43c8339	176	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
6ad8d67d S	177	(~mask);
	178	io_settings \|= (ds_60_ohm << 29) \| (ds_60_ohm << 26) \|
	179	(ds_60_ohm << 23) \| (sc_fast << 20) \|
	180	(sc_fast << 17) \| (sc_fast << 14);
c43c8339	181	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
6ad8d67d	182
9ca8bfea	183	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
eb4e18e8 LV	184	io_settings_lpddr2();
	185	else
	186	io_settings_ddr3();
6ad8d67d S	187
6ad8d67d S	188	/* Efuse settings */
c43c8339 LV	189	writel(EFUSE_1, (*ctrl)->control_efuse_1);
	190	writel(EFUSE_2, (*ctrl)->control_efuse_2);
	191	writel(EFUSE_3, (*ctrl)->control_efuse_3);
	192	writel(EFUSE_4, (*ctrl)->control_efuse_4);
508a58fa	193	}
d4d986ee LV	194
	195	static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
	196	{0x45, 0x1}, /* 12 MHz */
	197	{-1, -1}, /* 13 MHz */
	198	{0x63, 0x2}, /* 16.8 MHz */
	199	{0x57, 0x2}, /* 19.2 MHz */
	200	{0x20, 0x1}, /* 26 MHz */
	201	{-1, -1}, /* 27 MHz */
	202	{0x41, 0x3} /* 38.4 MHz */
	203	};
	204
	205	void srcomp_enable(void)
	206	{
	207	u32 srcomp_value, mul_factor, div_factor, clk_val, i;
	208	u32 sysclk_ind = get_sys_clk_index();
	209	u32 omap_rev = omap_revision();
	210
e9d6cd04 LV	211	if (!is_omap54xx())
	212	return;
	213
d4d986ee LV	214	mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
	215	div_factor = srcomp_parameters[sysclk_ind].divide_factor;
	216
	217	for (i = 0; i < 4; i++) {
	218	srcomp_value = readl((ctrl)->control_srcomp_north_side + i4);
	219	srcomp_value &=
	220	~(MULTIPLY_FACTOR_XS_MASK \| DIVIDE_FACTOR_XS_MASK);
	221	srcomp_value \|= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) \|
	222	(div_factor << DIVIDE_FACTOR_XS_SHIFT);
	223	writel(srcomp_value, (ctrl)->control_srcomp_north_side + i4);
	224	}
	225
	226	if ((omap_rev == OMAP5430_ES1_0) \|\| (omap_rev == OMAP5432_ES1_0)) {
	227	clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
	228	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
	229	writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
	230
	231	for (i = 0; i < 4; i++) {
	232	srcomp_value =
	233	readl((ctrl)->control_srcomp_north_side + i4);
	234	srcomp_value &= ~PWRDWN_XS_MASK;
	235	writel(srcomp_value,
	236	(ctrl)->control_srcomp_north_side + i4);
	237
	238	while (((readl((ctrl)->control_srcomp_north_side + i4)
	239	& SRCODE_READ_XS_MASK) >>
	240	SRCODE_READ_XS_SHIFT) == 0)
	241	;
	242
	243	srcomp_value =
	244	readl((ctrl)->control_srcomp_north_side + i4);
	245	srcomp_value &= ~OVERRIDE_XS_MASK;
	246	writel(srcomp_value,
	247	(ctrl)->control_srcomp_north_side + i4);
	248	}
	249	} else {
	250	srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
	251	srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK \|
	252	DIVIDE_FACTOR_XS_MASK);
	253	srcomp_value \|= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) \|
	254	(div_factor << DIVIDE_FACTOR_XS_SHIFT);
	255	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	256
	257	for (i = 0; i < 4; i++) {
	258	srcomp_value =
	259	readl((ctrl)->control_srcomp_north_side + i4);
	260	srcomp_value \|= SRCODE_OVERRIDE_SEL_XS_MASK;
	261	writel(srcomp_value,
	262	(ctrl)->control_srcomp_north_side + i4);
	263
	264	srcomp_value =
	265	readl((ctrl)->control_srcomp_north_side + i4);
	266	srcomp_value &= ~OVERRIDE_XS_MASK;
	267	writel(srcomp_value,
	268	(ctrl)->control_srcomp_north_side + i4);
	269	}
	270
	271	srcomp_value =
	272	readl((*ctrl)->control_srcomp_east_side_wkup);
	273	srcomp_value \|= SRCODE_OVERRIDE_SEL_XS_MASK;
	274	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	275
	276	srcomp_value =
	277	readl((*ctrl)->control_srcomp_east_side_wkup);
278	srcomp_value &= ~OVERRIDE_XS_MASK;
279	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
280
281	clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
282	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
283	writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
284
285	clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
286	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
287	writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
288
289	for (i = 0; i < 4; i++) {
290	while (((readl((ctrl)->control_srcomp_north_side + i4)
291	& SRCODE_READ_XS_MASK) >>
292	SRCODE_READ_XS_SHIFT) == 0)
293	;
294
295	srcomp_value =
296	readl((ctrl)->control_srcomp_north_side + i4);
297	srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
298	writel(srcomp_value,
299	(ctrl)->control_srcomp_north_side + i4);
300	}
301
302	while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
303	SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
304	;
305
306	srcomp_value =
307	readl((*ctrl)->control_srcomp_east_side_wkup);
308	srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
309	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
310	}
311	}
508a58fa S	312	#endif
508a58fa S	313
784ab7c5 LV	314	void config_data_eye_leveling_samples(u32 emif_base)
784ab7c5 LV	315	{
784ab7c5 LV	316	/EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4/
	317	if (emif_base == EMIF1_BASE)
	318	writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
c43c8339	319	(*ctrl)->control_emif1_sdram_config_ext);
784ab7c5 LV	320	else if (emif_base == EMIF2_BASE)
784ab7c5 LV	321	writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
c43c8339	322	(*ctrl)->control_emif2_sdram_config_ext);
784ab7c5 LV	323	}
784ab7c5 LV	324
508a58fa S	325	void init_omap_revision(void)
	326	{
	327	/*
	328	* For some of the ES2/ES1 boards ID_CODE is not reliable:
	329	* Also, ES1 and ES2 have different ARM revisions
	330	* So use ARM revision for identification
	331	*/
	332	unsigned int rev = cortex_rev();
	333
eed7c0f7 S	334	switch (readl(CONTROL_ID_CODE)) {
	335	case OMAP5430_CONTROL_ID_CODE_ES1_0:
	336	*omap_si_rev = OMAP5430_ES1_0;
	337	if (rev == MIDR_CORTEX_A15_R2P2)
	338	*omap_si_rev = OMAP5430_ES2_0;
	339	break;
	340	case OMAP5432_CONTROL_ID_CODE_ES1_0:
	341	*omap_si_rev = OMAP5432_ES1_0;
	342	if (rev == MIDR_CORTEX_A15_R2P2)
	343	*omap_si_rev = OMAP5432_ES2_0;
	344	break;
	345	case OMAP5430_CONTROL_ID_CODE_ES2_0:
	346	*omap_si_rev = OMAP5430_ES2_0;
	347	break;
	348	case OMAP5432_CONTROL_ID_CODE_ES2_0:
	349	*omap_si_rev = OMAP5432_ES2_0;
cdd50a8d	350	break;
de62688b LV	351	case DRA752_CONTROL_ID_CODE_ES1_0:
	352	*omap_si_rev = DRA752_ES1_0;
	353	break;
508a58fa	354	default:
087189fb	355	*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
508a58fa S	356	}
508a58fa S	357	}
0696473b S	358
	359	void reset_cpu(ulong ignored)
	360	{
	361	u32 omap_rev = omap_revision();
	362
	363	/*
	364	* WARM reset is not functional in case of OMAP5430 ES1.0 soc.
	365	* So use cold reset in case instead.
	366	*/
	367	if (omap_rev == OMAP5430_ES1_0)
d4e4129c	368	writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
0696473b	369	else
d4e4129c LV	370	writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
	371	}
	372
	373	u32 warm_reset(void)
	374	{
	375	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
0696473b	376	}
0b1b60c7 LV	377
	378	void setup_warmreset_time(void)
	379	{
	380	u32 rst_time, rst_val;
	381
	382	#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
	383	rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
	384	#else
	385	rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
	386	#endif
	387	rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
	388
	389	if (rst_time > RSTTIME1_MASK)
	390	rst_time = RSTTIME1_MASK;
	391
	392	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
	393	rst_val \|= rst_time;
	394	writel(rst_val, (*prcm)->prm_rsttime);
	395	}