[people/ms/u-boot.git] / arch / arm / cpu / armv7 / socfpga / misc.c

/*
 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <altera.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/nic301.h>
#include <asm/arch/scu.h>
#include <asm/pl310.h>

DECLARE_GLOBAL_DATA_PTR;

static struct pl310_regs *const pl310 =
	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static struct socfpga_system_manager *sysmgr_regs =
	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static struct socfpga_reset_manager *reset_manager_base =
	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
static struct nic301_registers *nic301_regs =
	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static struct scu_registers *scu_regs =
	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;

int dram_init(void)
{
	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
	return 0;
}

void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
	icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
	dcache_enable();
#endif
}

/*
 * DesignWare Ethernet initialization
 */
#ifdef CONFIG_DESIGNWARE_ETH
int cpu_eth_init(bd_t *bis)
{
#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
#else
#error "Incorrect CONFIG_EMAC_BASE value!"
#endif

	/* Initialize EMAC. This needs to be done at least once per boot. */

	/*
	 * Putting the EMAC controller to reset when configuring the PHY
	 * interface select at System Manager
	 */
	socfpga_emac_reset(1);

	/* Clearing emac0 PHY interface select to 0 */
	clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
		     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);

	/* configure to PHY interface select choosed */
	setbits_le32(&sysmgr_regs->emacgrp_ctrl,
		     SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);

	/* Release the EMAC controller from reset */
	socfpga_emac_reset(0);

	/* initialize and register the emac */
	return designware_initialize(CONFIG_EMAC_BASE,
				     CONFIG_PHY_INTERFACE_MODE);
}
#endif

#ifdef CONFIG_DWMMC
/*
 * Initializes MMC controllers.
 * to override, implement board_mmc_init()
 */
int cpu_mmc_init(bd_t *bis)
{
	return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
				  CONFIG_HPS_SDMMC_BUSWIDTH, 0);
}
#endif

#if defined(CONFIG_DISPLAY_CPUINFO)
/*
 * Print CPU information
 */
int print_cpuinfo(void)
{
	puts("CPU:   Altera SoCFPGA Platform\n");
	return 0;
}
#endif

#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
int overwrite_console(void)
{
	return 0;
}
#endif

#ifdef CONFIG_FPGA
/*
 * FPGA programming support for SoC FPGA Cyclone V
 */
static Altera_desc altera_fpga[] = {
	{
		/* Family */
		Altera_SoCFPGA,
		/* Interface type */
		fast_passive_parallel,
		/* No limitation as additional data will be ignored */
		-1,
		/* No device function table */
		NULL,
		/* Base interface address specified in driver */
		NULL,
		/* No cookie implementation */
		0
	},
};

/* add device descriptor to FPGA device table */
static void socfpga_fpga_add(void)
{
	int i;
	fpga_init();
	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
		fpga_add(fpga_altera, &altera_fpga[i]);
}
#else
static inline void socfpga_fpga_add(void) {}
#endif

int arch_cpu_init(void)
{
	/*
	 * If the HW watchdog is NOT enabled, make sure it is not running,
	 * for example because it was enabled in the preloader. This might
	 * trigger a watchdog-triggered reboot of Linux kernel later.
	 */
#ifndef CONFIG_HW_WATCHDOG
	socfpga_watchdog_reset();
#endif
	return 0;
}

/*
 * Convert all NIC-301 AMBA slaves from secure to non-secure
 */
static void socfpga_nic301_slave_ns(void)
{
	writel(0x1, &nic301_regs->lwhps2fpgaregs);
	writel(0x1, &nic301_regs->hps2fpgaregs);
	writel(0x1, &nic301_regs->acp);
	writel(0x1, &nic301_regs->rom);
	writel(0x1, &nic301_regs->ocram);
	writel(0x1, &nic301_regs->sdrdata);
}

static uint32_t iswgrp_handoff[8];

int arch_early_init_r(void)
{
	int i;
	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);

	socfpga_bridges_reset(1);
	socfpga_nic301_slave_ns();

	/*
	 * Private components security:
	 * U-Boot : configure private timer, global timer and cpu component
	 * access as non secure for kernel stage (as required by Linux)
	 */
	setbits_le32(&scu_regs->sacr, 0xfff);

	/* Configure the L2 controller to make SDRAM start at 0 */
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	writel(0x2, &nic301_regs->remap);
#else
	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */
	writel(0x1, &pl310->pl310_addr_filter_start);
#endif

	/* Add device descriptor to FPGA device table */
	socfpga_fpga_add();

#ifdef CONFIG_DESIGNWARE_SPI
	/* Get Designware SPI controller out of reset */
	socfpga_spim_enable();
#endif

	return 0;
}

static void socfpga_sdram_apply_static_cfg(void)
{
	const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
	const uint32_t applymask = 0x8;
	uint32_t val = readl(staticcfg) | applymask;

	/*
	 * SDRAM staticcfg register specific:
	 * When applying the register setting, the CPU must not access
	 * SDRAM. Luckily for us, we can abuse i-cache here to help us
	 * circumvent the SDRAM access issue. The idea is to make sure
	 * that the code is in one full i-cache line by branching past
	 * it and back. Once it is in the i-cache, we execute the core
	 * of the code and apply the register settings.
	 *
	 * The code below uses 7 instructions, while the Cortex-A9 has
	 * 32-byte cachelines, thus the limit is 8 instructions total.
	 */
	asm volatile(
		".align	5			\n"
		"	b	2f		\n"
		"1:	str	%0,	[%1]	\n"
		"	dsb			\n"
		"	isb			\n"
		"	b	3f		\n"
		"2:	b	1b		\n"
		"3:	nop			\n"
	: : "r"(val), "r"(staticcfg) : "memory", "cc");
}

int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	if (argc != 2)
		return CMD_RET_USAGE;

	argv++;

	switch (*argv[0]) {
	case 'e':	/* Enable */
		writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
		socfpga_sdram_apply_static_cfg();
		writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
		writel(iswgrp_handoff[1], &nic301_regs->remap);
		break;
	case 'd':	/* Disable */
		writel(0, &sysmgr_regs->fpgaintfgrp_module);
		writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
		socfpga_sdram_apply_static_cfg();
		writel(0, &reset_manager_base->brg_mod_reset);
		writel(1, &nic301_regs->remap);
		break;
	default:
		return CMD_RET_USAGE;
	}

	return 0;
}

U_BOOT_CMD(
	bridge, 2, 1, do_bridge,
	"SoCFPGA HPS FPGA bridge control",
	"enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
	""
);
Commit	Line	Data
77754408 DN	1	/*
	2	* Copyright (C) 2012 Altera Corporation <www.altera.com>
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
77754408 DN	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
230fe9b2	9	#include <altera.h>
99b97106 PM	10	#include <miiphy.h>
99b97106 PM	11	#include <netdev.h>
de6da925	12	#include <asm/arch/reset_manager.h>
45d6e677	13	#include <asm/arch/system_manager.h>
4e736869	14	#include <asm/arch/dwmmc.h>
60d804c2	15	#include <asm/arch/nic301.h>
13e81d45	16	#include <asm/arch/scu.h>
60d804c2	17	#include <asm/pl310.h>
77754408 DN	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
60d804c2 MV	21	static struct pl310_regs *const pl310 =
60d804c2 MV	22	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
45d6e677 PM	23	static struct socfpga_system_manager *sysmgr_regs =
45d6e677 PM	24	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
7249fafb MV	25	static struct socfpga_reset_manager *reset_manager_base =
7249fafb MV	26	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
60d804c2 MV	27	static struct nic301_registers *nic301_regs =
60d804c2 MV	28	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
13e81d45 PM	29	static struct scu_registers *scu_regs =
13e81d45 PM	30	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
45d6e677	31
77754408 DN	32	int dram_init(void)
	33	{
	34	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
	35	return 0;
	36	}
23f23f23	37
4ab333b7 MV	38	void enable_caches(void)
	39	{
	40	#ifndef CONFIG_SYS_ICACHE_OFF
	41	icache_enable();
	42	#endif
	43	#ifndef CONFIG_SYS_DCACHE_OFF
	44	dcache_enable();
	45	#endif
	46	}
	47
45d6e677 PM	48	/*
	49	* DesignWare Ethernet initialization
	50	*/
	51	#ifdef CONFIG_DESIGNWARE_ETH
	52	int cpu_eth_init(bd_t *bis)
	53	{
	54	#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
	55	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
	56	#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
	57	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
	58	#else
	59	#error "Incorrect CONFIG_EMAC_BASE value!"
	60	#endif
	61
	62	/* Initialize EMAC. This needs to be done at least once per boot. */
	63
	64	/*
	65	* Putting the EMAC controller to reset when configuring the PHY
	66	* interface select at System Manager
	67	*/
	68	socfpga_emac_reset(1);
	69
	70	/* Clearing emac0 PHY interface select to 0 */
	71	clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
	72	SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
	73
	74	/* configure to PHY interface select choosed */
	75	setbits_le32(&sysmgr_regs->emacgrp_ctrl,
	76	SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
	77
	78	/* Release the EMAC controller from reset */
	79	socfpga_emac_reset(0);
	80
	81	/* initialize and register the emac */
	82	return designware_initialize(CONFIG_EMAC_BASE,
	83	CONFIG_PHY_INTERFACE_MODE);
	84	}
	85	#endif
	86
4e736869 PM	87	#ifdef CONFIG_DWMMC
	88	/*
	89	* Initializes MMC controllers.
	90	* to override, implement board_mmc_init()
	91	*/
	92	int cpu_mmc_init(bd_t *bis)
	93	{
	94	return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
	95	CONFIG_HPS_SDMMC_BUSWIDTH, 0);
	96	}
	97	#endif
	98
23f23f23 CLS	99	#if defined(CONFIG_DISPLAY_CPUINFO)
	100	/*
	101	* Print CPU information
	102	*/
	103	int print_cpuinfo(void)
	104	{
d5a3d3c9	105	puts("CPU: Altera SoCFPGA Platform\n");
23f23f23 CLS	106	return 0;
	107	}
	108	#endif
	109
	110	#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
	111	defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
	112	int overwrite_console(void)
	113	{
	114	return 0;
	115	}
	116	#endif
	117
230fe9b2 PM	118	#ifdef CONFIG_FPGA
	119	/*
	120	* FPGA programming support for SoC FPGA Cyclone V
	121	*/
	122	static Altera_desc altera_fpga[] = {
	123	{
	124	/* Family */
	125	Altera_SoCFPGA,
	126	/* Interface type */
	127	fast_passive_parallel,
	128	/* No limitation as additional data will be ignored */
	129	-1,
	130	/* No device function table */
	131	NULL,
	132	/* Base interface address specified in driver */
	133	NULL,
	134	/* No cookie implementation */
	135	0
	136	},
	137	};
	138
	139	/* add device descriptor to FPGA device table */
	140	static void socfpga_fpga_add(void)
	141	{
	142	int i;
	143	fpga_init();
	144	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
	145	fpga_add(fpga_altera, &altera_fpga[i]);
	146	}
	147	#else
	148	static inline void socfpga_fpga_add(void) {}
	149	#endif
	150
de6da925 PM	151	int arch_cpu_init(void)
	152	{
	153	/*
	154	* If the HW watchdog is NOT enabled, make sure it is not running,
	155	* for example because it was enabled in the preloader. This might
	156	* trigger a watchdog-triggered reboot of Linux kernel later.
	157	*/
	158	#ifndef CONFIG_HW_WATCHDOG
	159	socfpga_watchdog_reset();
	160	#endif
	161	return 0;
	162	}
	163
13e81d45 PM	164	/*
	165	* Convert all NIC-301 AMBA slaves from secure to non-secure
	166	*/
	167	static void socfpga_nic301_slave_ns(void)
	168	{
	169	writel(0x1, &nic301_regs->lwhps2fpgaregs);
	170	writel(0x1, &nic301_regs->hps2fpgaregs);
	171	writel(0x1, &nic301_regs->acp);
	172	writel(0x1, &nic301_regs->rom);
	173	writel(0x1, &nic301_regs->ocram);
	174	writel(0x1, &nic301_regs->sdrdata);
	175	}
	176
7249fafb MV	177	static uint32_t iswgrp_handoff[8];
7249fafb MV	178
fc520894	179	int arch_early_init_r(void)
23f23f23	180	{
7249fafb MV	181	int i;
	182	for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
	183	iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
	184
13e81d45 PM	185	socfpga_bridges_reset(1);
	186	socfpga_nic301_slave_ns();
	187
	188	/*
	189	* Private components security:
	190	* U-Boot : configure private timer, global timer and cpu component
	191	* access as non secure for kernel stage (as required by Linux)
	192	*/
	193	setbits_le32(&scu_regs->sacr, 0xfff);
	194
60d804c2 MV	195	/* Configure the L2 controller to make SDRAM start at 0 */
	196	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	197	writel(0x2, &nic301_regs->remap);
	198	#else
	199	writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
	200	writel(0x1, &pl310->pl310_addr_filter_start);
	201	#endif
	202
230fe9b2 PM	203	/* Add device descriptor to FPGA device table */
230fe9b2 PM	204	socfpga_fpga_add();
a877bec3 SR	205
	206	#ifdef CONFIG_DESIGNWARE_SPI
	207	/* Get Designware SPI controller out of reset */
	208	socfpga_spim_enable();
	209	#endif
	210
23f23f23 CLS	211	return 0;
23f23f23 CLS	212	}
7249fafb MV	213
	214	static void socfpga_sdram_apply_static_cfg(void)
	215	{
	216	const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
	217	const uint32_t applymask = 0x8;
	218	uint32_t val = readl(staticcfg) \| applymask;
	219
	220	/*
	221	* SDRAM staticcfg register specific:
	222	* When applying the register setting, the CPU must not access
	223	* SDRAM. Luckily for us, we can abuse i-cache here to help us
	224	* circumvent the SDRAM access issue. The idea is to make sure
	225	* that the code is in one full i-cache line by branching past
	226	* it and back. Once it is in the i-cache, we execute the core
	227	* of the code and apply the register settings.
	228	*
	229	* The code below uses 7 instructions, while the Cortex-A9 has
	230	* 32-byte cachelines, thus the limit is 8 instructions total.
	231	*/
	232	asm volatile(
	233	".align 5 \n"
	234	" b 2f \n"
	235	"1: str %0, [%1] \n"
	236	" dsb \n"
	237	" isb \n"
	238	" b 3f \n"
	239	"2: b 1b \n"
	240	"3: nop \n"
	241	: : "r"(val), "r"(staticcfg) : "memory", "cc");
	242	}
	243
	244	int do_bridge(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	245	{
	246	if (argc != 2)
	247	return CMD_RET_USAGE;
	248
	249	argv++;
	250
	251	switch (*argv[0]) {
	252	case 'e': /* Enable */
	253	writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
	254	socfpga_sdram_apply_static_cfg();
	255	writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
	256	writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
	257	writel(iswgrp_handoff[1], &nic301_regs->remap);
	258	break;
	259	case 'd': /* Disable */
	260	writel(0, &sysmgr_regs->fpgaintfgrp_module);
	261	writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
	262	socfpga_sdram_apply_static_cfg();
	263	writel(0, &reset_manager_base->brg_mod_reset);
	264	writel(1, &nic301_regs->remap);
	265	break;
	266	default:
	267	return CMD_RET_USAGE;
	268	}
	269
	270	return 0;
	271	}
	272
	273	U_BOOT_CMD(
	274	bridge, 2, 1, do_bridge,
	275	"SoCFPGA HPS FPGA bridge control",
	276	"enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
277	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
278	""
279	);