[thirdparty/u-boot.git] / arch / arm / cpu / armv7 / start.S

/*
 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
 *
 * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
 *
 * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
 * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
 * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
 * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
 * Copyright (c) 2003	Kshitij <kshitij@ti.com>
 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/system.h>
#include <linux/linkage.h>

.globl _start
_start: b	reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq
#ifdef CONFIG_SPL_BUILD
_undefined_instruction: .word _undefined_instruction
_software_interrupt:	.word _software_interrupt
_prefetch_abort:	.word _prefetch_abort
_data_abort:		.word _data_abort
_not_used:		.word _not_used
_irq:			.word _irq
_fiq:			.word _fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#else
_undefined_instruction: .word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#endif	/* CONFIG_SPL_BUILD */

.global _end_vect
_end_vect:

	.balignl 16,0xdeadbeef
/*************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************/

.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	.word	CONFIG_SPL_TEXT_BASE
#else
	.word	CONFIG_SYS_TEXT_BASE
#endif

/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	bl	save_boot_params
	/*
	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
	 * except if in HYP mode already
	 */
	mrs	r0, cpsr
	and	r1, r0, #0x1f		@ mask mode bits
	teq	r1, #0x1a		@ test for HYP mode
	bicne	r0, r0, #0x1f		@ clear all mode bits
	orrne	r0, r0, #0x13		@ set SVC mode
	orr	r0, r0, #0xc0		@ disable FIQ and IRQ
	msr	cpsr,r0

/*
 * Setup vector:
 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
 * Continue to use ROM code vector only in OMAP4 spl)
 */
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTRL Register
	bic	r0, #CR_V		@ V = 0
	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTRL Register

	/* Set vector address in CP15 VBAR register */
	ldr	r0, =_start
	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
#endif

	/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_cp15
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

ENTRY(c_runtime_cpu_setup)
/*
 * If I-cache is enabled invalidate it
 */
#ifndef CONFIG_SYS_ICACHE_OFF
	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c5, 4	@ ISB
#endif
/*
 * Move vector table
 */
	/* Set vector address in CP15 VBAR register */
	ldr     r0, =_start
	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR

	bx	lr

ENDPROC(c_runtime_cpu_setup)

/*************************************************************************
 *
 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
 *	__attribute__((weak));
 *
 * Stack pointer is not yet initialized at this moment
 * Don't save anything to stack even if compiled with -O0
 *
 *************************************************************************/
ENTRY(save_boot_params)
	bx	lr			@ back to my caller
ENDPROC(save_boot_params)
	.weak	save_boot_params

/*************************************************************************
 *
 * cpu_init_cp15
 *
 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
 * CONFIG_SYS_ICACHE_OFF is defined.
 *
 *************************************************************************/
ENTRY(cpu_init_cp15)
	/*
	 * Invalidate L1 I/D
	 */
	mov	r0, #0			@ set up for MCR
	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c5, 4	@ ISB

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
#ifdef CONFIG_SYS_ICACHE_OFF
	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
#else
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
#endif
	mcr	p15, 0, r0, c1, c0, 0

#ifdef CONFIG_ARM_ERRATA_716044
	mrc	p15, 0, r0, c1, c0, 0	@ read system control register
	orr	r0, r0, #1 << 11	@ set bit #11
	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
#endif

#ifdef CONFIG_ARM_ERRATA_742230
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 4		@ set bit #4
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
#endif

#ifdef CONFIG_ARM_ERRATA_743622
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 6		@ set bit #6
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
#endif

#ifdef CONFIG_ARM_ERRATA_751472
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 11	@ set bit #11
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
#endif

	mov	pc, lr			@ back to my caller
ENDPROC(cpu_init_cp15)

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************/
ENTRY(cpu_init_crit)
	/*
	 * Jump to board specific initialization...
	 * The Mask ROM will have already initialized
	 * basic memory. Go here to bump up clock rate and handle
	 * wake up conditions.
	 */
	b	lowlevel_init		@ go setup pll,mux,memory
ENDPROC(cpu_init_crit)
#endif

#ifndef CONFIG_SPL_BUILD
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
						@ user stack
	stmia	sp, {r0 - r12}			@ Save user registers (now in
						@ svc mode) r0-r12
	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort
						@ stack
	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
						@ and cpsr (into parm regs)
	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp				@ save current stack into r0
						@ (param register)
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
						@ a reserved stack spot would
						@ be good.
	stmdb	r8, {sp, lr}^			@ Calling SP, LR
	str	lr, [r8, #0]			@ Save calling PC
	mrs	r6, spsr
	str	r6, [r8, #4]			@ Save CPSR
	str	r0, [r8, #8]			@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into
						@ cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter
						@ in banked mode)

	str	lr, [r13]			@ save caller lr in position 0
						@ of saved stack
	mrs	lr, spsr			@ get the spsr
	str	lr, [r13, #4]			@ save spsr in position 1 of
						@ saved stack

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13			@ switch modes, make sure
						@ moves will execute
	mov	lr, pc				@ capture return pc
	movs	pc, lr				@ jump to next instruction &
						@ switch modes.
	.endm

	.macro get_bad_stack_swi
	sub	r13, r13, #4			@ space on current stack for
						@ scratch reg.
	str	r0, [r13]			@ save R0's value.
	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
						@ spots for abort stack
	str	lr, [r0]			@ save caller lr in position 0
						@ of saved stack
	mrs	lr, spsr			@ get the spsr
	str	lr, [r0, #4]			@ save spsr in position 1 of
						@ saved stack
	ldr	lr, [r0]			@ restore lr
	ldr	r0, [r13]			@ restore r0
	add	r13, r13, #4			@ pop stack entry
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align	5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack_swi
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effective fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif /* CONFIG_USE_IRQ */
#endif /* CONFIG_SPL_BUILD */
Commit	Line	Data
0b02b184 DB	1	/*
	2	* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
	3	*
	4	* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
	5	*
	6	* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
	7	* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
792a09eb	8	* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
0b02b184 DB	9	* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
	10	* Copyright (c) 2003 Kshitij <kshitij@ti.com>
	11	* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
	12	*
3765b3e7	13	* SPDX-License-Identifier: GPL-2.0+
0b02b184 DB	14	*/
0b02b184 DB	15
25ddd1fb	16	#include <asm-offsets.h>
0b02b184 DB	17	#include <config.h>
0b02b184 DB	18	#include <version.h>
a8c68639	19	#include <asm/system.h>
74236aca	20	#include <linux/linkage.h>
0b02b184 DB	21
	22	.globl _start
	23	_start: b reset
	24	ldr pc, _undefined_instruction
	25	ldr pc, _software_interrupt
	26	ldr pc, _prefetch_abort
	27	ldr pc, _data_abort
	28	ldr pc, _not_used
	29	ldr pc, _irq
	30	ldr pc, _fiq
033ca724 A	31	#ifdef CONFIG_SPL_BUILD
	32	_undefined_instruction: .word _undefined_instruction
	33	_software_interrupt: .word _software_interrupt
	34	_prefetch_abort: .word _prefetch_abort
	35	_data_abort: .word _data_abort
	36	_not_used: .word _not_used
	37	_irq: .word _irq
	38	_fiq: .word _fiq
	39	_pad: .word 0x12345678 /* now 164=64 /
	40	#else
0b02b184 DB	41	_undefined_instruction: .word undefined_instruction
	42	_software_interrupt: .word software_interrupt
	43	_prefetch_abort: .word prefetch_abort
	44	_data_abort: .word data_abort
	45	_not_used: .word not_used
	46	_irq: .word irq
	47	_fiq: .word fiq
	48	_pad: .word 0x12345678 /* now 164=64 /
033ca724 A	49	#endif /* CONFIG_SPL_BUILD */
033ca724 A	50
0b02b184 DB	51	.global _end_vect
	52	_end_vect:
	53
	54	.balignl 16,0xdeadbeef
	55	/*************************************************************************
	56	*
	57	* Startup Code (reset vector)
	58	*
	59	* do important init only if we don't start from memory!
	60	* setup Memory and board specific bits prior to relocation.
	61	* relocate armboot to ram
	62	* setup stack
	63	*
	64	*************************************************************************/
	65
561142af	66	.globl _TEXT_BASE
0b02b184	67	_TEXT_BASE:
508611bc BT	68	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	69	.word CONFIG_SPL_TEXT_BASE
	70	#else
14d0a02a	71	.word CONFIG_SYS_TEXT_BASE
508611bc	72	#endif
0b02b184	73
0b02b184 DB	74	/*
	75	* These are defined in the board-specific linker script.
	76	*/
c3d3a541 HS	77	.globl _bss_start_ofs
	78	_bss_start_ofs:
	79	.word __bss_start - _start
0b02b184	80
c3d3a541 HS	81	.globl _bss_end_ofs
c3d3a541 HS	82	_bss_end_ofs:
3929fb0a	83	.word __bss_end - _start
0b02b184	84
f326cbba PYC	85	.globl _end_ofs
	86	_end_ofs:
	87	.word _end - _start
	88
0b02b184 DB	89	#ifdef CONFIG_USE_IRQ
	90	/* IRQ stack memory (calculated at run-time) */
	91	.globl IRQ_STACK_START
	92	IRQ_STACK_START:
	93	.word 0x0badc0de
	94
	95	/* IRQ stack memory (calculated at run-time) */
	96	.globl FIQ_STACK_START
	97	FIQ_STACK_START:
	98	.word 0x0badc0de
	99	#endif
	100
561142af HS	101	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	102	.globl IRQ_STACK_START_IN
	103	IRQ_STACK_START_IN:
	104	.word 0x0badc0de
	105
561142af HS	106	/*
	107	* the actual reset code
	108	*/
	109
	110	reset:
8cf686e1	111	bl save_boot_params
561142af	112	/*
c4a4e2e2 AP	113	* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
c4a4e2e2 AP	114	* except if in HYP mode already
561142af HS	115	*/
561142af HS	116	mrs r0, cpsr
c4a4e2e2 AP	117	and r1, r0, #0x1f @ mask mode bits
	118	teq r1, #0x1a @ test for HYP mode
	119	bicne r0, r0, #0x1f @ clear all mode bits
	120	orrne r0, r0, #0x13 @ set SVC mode
	121	orr r0, r0, #0xc0 @ disable FIQ and IRQ
561142af HS	122	msr cpsr,r0
561142af HS	123
a8c68639 A	124	/*
	125	* Setup vector:
	126	* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
	127	* Continue to use ROM code vector only in OMAP4 spl)
	128	*/
	129	#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
	130	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
	131	mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
	132	bic r0, #CR_V @ V = 0
	133	mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
	134
	135	/* Set vector address in CP15 VBAR register */
	136	ldr r0, =_start
	137	mcr p15, 0, r0, c12, c0, 0 @Set VBAR
	138	#endif
	139
561142af HS	140	/* the mask ROM code should have PLL and others stable */
561142af HS	141	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
80433c9a	142	bl cpu_init_cp15
561142af HS	143	bl cpu_init_crit
	144	#endif
	145
e05e5de7	146	bl _main
561142af HS	147
	148	/------------------------------------------------------------------------------/
	149
e05e5de7	150	ENTRY(c_runtime_cpu_setup)
c2dd0d45 A	151	/*
	152	* If I-cache is enabled invalidate it
	153	*/
	154	#ifndef CONFIG_SYS_ICACHE_OFF
	155	mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
	156	mcr p15, 0, r0, c7, c10, 4 @ DSB
	157	mcr p15, 0, r0, c7, c5, 4 @ ISB
	158	#endif
f8b9d1d3 TK	159	/*
	160	* Move vector table
	161	*/
f8b9d1d3 TK	162	/* Set vector address in CP15 VBAR register */
f8b9d1d3 TK	163	ldr r0, =_start
f8b9d1d3	164	mcr p15, 0, r0, c12, c0, 0 @Set VBAR
f8b9d1d3	165
e05e5de7 AA	166	bx lr
	167
	168	ENDPROC(c_runtime_cpu_setup)
c3d3a541	169
6f0dba85 TK	170	/*************************************************************************
	171	*
	172	* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
	173	* __attribute__((weak));
	174	*
	175	* Stack pointer is not yet initialized at this moment
	176	* Don't save anything to stack even if compiled with -O0
	177	*
	178	*************************************************************************/
	179	ENTRY(save_boot_params)
	180	bx lr @ back to my caller
	181	ENDPROC(save_boot_params)
	182	.weak save_boot_params
	183
0b02b184 DB	184	/*************************************************************************
0b02b184 DB	185	*
80433c9a	186	* cpu_init_cp15
0b02b184	187	*
80433c9a SG	188	* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
80433c9a SG	189	* CONFIG_SYS_ICACHE_OFF is defined.
0b02b184 DB	190	*
0b02b184 DB	191	*************************************************************************/
74236aca	192	ENTRY(cpu_init_cp15)
0b02b184 DB	193	/*
	194	* Invalidate L1 I/D
	195	*/
	196	mov r0, #0 @ set up for MCR
	197	mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
	198	mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
c2dd0d45 A	199	mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
	200	mcr p15, 0, r0, c7, c10, 4 @ DSB
	201	mcr p15, 0, r0, c7, c5, 4 @ ISB
0b02b184 DB	202
	203	/*
	204	* disable MMU stuff and caches
	205	*/
	206	mrc p15, 0, r0, c1, c0, 0
	207	bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
	208	bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
	209	orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
c2dd0d45 A	210	orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
	211	#ifdef CONFIG_SYS_ICACHE_OFF
	212	bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
	213	#else
	214	orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
	215	#endif
0b02b184	216	mcr p15, 0, r0, c1, c0, 0
0678587f	217
c5d4752c SW	218	#ifdef CONFIG_ARM_ERRATA_716044
	219	mrc p15, 0, r0, c1, c0, 0 @ read system control register
	220	orr r0, r0, #1 << 11 @ set bit #11
	221	mcr p15, 0, r0, c1, c0, 0 @ write system control register
	222	#endif
	223
0678587f SW	224	#ifdef CONFIG_ARM_ERRATA_742230
	225	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	226	orr r0, r0, #1 << 4 @ set bit #4
	227	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	228	#endif
	229
	230	#ifdef CONFIG_ARM_ERRATA_743622
	231	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	232	orr r0, r0, #1 << 6 @ set bit #6
	233	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	234	#endif
	235
	236	#ifdef CONFIG_ARM_ERRATA_751472
	237	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	238	orr r0, r0, #1 << 11 @ set bit #11
	239	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	240	#endif
	241
80433c9a	242	mov pc, lr @ back to my caller
74236aca	243	ENDPROC(cpu_init_cp15)
0b02b184	244
80433c9a SG	245	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	246	/*************************************************************************
	247	*
	248	* CPU_init_critical registers
	249	*
	250	* setup important registers
	251	* setup memory timing
	252	*
	253	*************************************************************************/
74236aca	254	ENTRY(cpu_init_crit)
0b02b184 DB	255	/*
	256	* Jump to board specific initialization...
	257	* The Mask ROM will have already initialized
	258	* basic memory. Go here to bump up clock rate and handle
	259	* wake up conditions.
	260	*/
63ee53a7	261	b lowlevel_init @ go setup pll,mux,memory
74236aca	262	ENDPROC(cpu_init_crit)
22193540	263	#endif
033ca724 A	264
033ca724 A	265	#ifndef CONFIG_SPL_BUILD
0b02b184 DB	266	/*
	267	*************************************************************************
	268	*
	269	* Interrupt handling
	270	*
	271	*************************************************************************
	272	*/
	273	@
	274	@ IRQ stack frame.
	275	@
	276	#define S_FRAME_SIZE 72
	277
	278	#define S_OLD_R0 68
	279	#define S_PSR 64
	280	#define S_PC 60
	281	#define S_LR 56
	282	#define S_SP 52
	283
	284	#define S_IP 48
	285	#define S_FP 44
	286	#define S_R10 40
	287	#define S_R9 36
	288	#define S_R8 32
	289	#define S_R7 28
	290	#define S_R6 24
	291	#define S_R5 20
	292	#define S_R4 16
	293	#define S_R3 12
	294	#define S_R2 8
	295	#define S_R1 4
	296	#define S_R0 0
	297
	298	#define MODE_SVC 0x13
	299	#define I_BIT 0x80
	300
	301	/*
	302	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	303	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	304	*/
	305
	306	.macro bad_save_user_regs
	307	sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
	308	@ user stack
	309	stmia sp, {r0 - r12} @ Save user registers (now in
	310	@ svc mode) r0-r12
561142af	311	ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
0b02b184 DB	312	@ stack
	313	ldmia r2, {r2 - r3} @ get values for "aborted" pc
	314	@ and cpsr (into parm regs)
	315	add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
	316
	317	add r5, sp, #S_SP
	318	mov r1, lr
	319	stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
	320	mov r0, sp @ save current stack into r0
	321	@ (param register)
	322	.endm
	323
	324	.macro irq_save_user_regs
	325	sub sp, sp, #S_FRAME_SIZE
	326	stmia sp, {r0 - r12} @ Calling r0-r12
	327	add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
	328	@ a reserved stack spot would
	329	@ be good.
	330	stmdb r8, {sp, lr}^ @ Calling SP, LR
	331	str lr, [r8, #0] @ Save calling PC
	332	mrs r6, spsr
	333	str r6, [r8, #4] @ Save CPSR
	334	str r0, [r8, #8] @ Save OLD_R0
	335	mov r0, sp
	336	.endm
	337
	338	.macro irq_restore_user_regs
	339	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	340	mov r0, r0
	341	ldr lr, [sp, #S_PC] @ Get PC
	342	add sp, sp, #S_FRAME_SIZE
	343	subs pc, lr, #4 @ return & move spsr_svc into
	344	@ cpsr
	345	.endm
	346
	347	.macro get_bad_stack
561142af HS	348	ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
561142af HS	349	@ in banked mode)
0b02b184 DB	350
	351	str lr, [r13] @ save caller lr in position 0
	352	@ of saved stack
	353	mrs lr, spsr @ get the spsr
	354	str lr, [r13, #4] @ save spsr in position 1 of
	355	@ saved stack
	356
	357	mov r13, #MODE_SVC @ prepare SVC-Mode
	358	@ msr spsr_c, r13
	359	msr spsr, r13 @ switch modes, make sure
	360	@ moves will execute
	361	mov lr, pc @ capture return pc
	362	movs pc, lr @ jump to next instruction &
	363	@ switch modes.
	364	.endm
	365
	366	.macro get_bad_stack_swi
	367	sub r13, r13, #4 @ space on current stack for
	368	@ scratch reg.
	369	str r0, [r13] @ save R0's value.
561142af	370	ldr r0, IRQ_STACK_START_IN @ get data regions start
0b02b184 DB	371	@ spots for abort stack
	372	str lr, [r0] @ save caller lr in position 0
	373	@ of saved stack
4411b2ae	374	mrs lr, spsr @ get the spsr
0b02b184 DB	375	str lr, [r0, #4] @ save spsr in position 1 of
0b02b184 DB	376	@ saved stack
4411b2ae	377	ldr lr, [r0] @ restore lr
0b02b184 DB	378	ldr r0, [r13] @ restore r0
	379	add r13, r13, #4 @ pop stack entry
	380	.endm
	381
	382	.macro get_irq_stack @ setup IRQ stack
	383	ldr sp, IRQ_STACK_START
	384	.endm
	385
	386	.macro get_fiq_stack @ setup FIQ stack
	387	ldr sp, FIQ_STACK_START
	388	.endm
	389
	390	/*
	391	* exception handlers
	392	*/
	393	.align 5
	394	undefined_instruction:
	395	get_bad_stack
	396	bad_save_user_regs
	397	bl do_undefined_instruction
	398
	399	.align 5
	400	software_interrupt:
	401	get_bad_stack_swi
	402	bad_save_user_regs
	403	bl do_software_interrupt
	404
	405	.align 5
	406	prefetch_abort:
	407	get_bad_stack
	408	bad_save_user_regs
	409	bl do_prefetch_abort
	410
	411	.align 5
	412	data_abort:
	413	get_bad_stack
	414	bad_save_user_regs
	415	bl do_data_abort
	416
	417	.align 5
	418	not_used:
	419	get_bad_stack
	420	bad_save_user_regs
	421	bl do_not_used
	422
	423	#ifdef CONFIG_USE_IRQ
	424
	425	.align 5
	426	irq:
	427	get_irq_stack
	428	irq_save_user_regs
	429	bl do_irq
	430	irq_restore_user_regs
	431
	432	.align 5
	433	fiq:
	434	get_fiq_stack
	435	/* someone ought to write a more effective fiq_save_user_regs */
	436	irq_save_user_regs
	437	bl do_fiq
	438	irq_restore_user_regs
	439
	440	#else
	441
442	.align 5
443	irq:
444	get_bad_stack
445	bad_save_user_regs
446	bl do_irq
447
448	.align 5
449	fiq:
450	get_bad_stack
451	bad_save_user_regs
452	bl do_fiq
453
033ca724 A	454	#endif /* CONFIG_USE_IRQ */
033ca724 A	455	#endif /* CONFIG_SPL_BUILD */