[people/ms/u-boot.git] / arch / arm / cpu / armv7 / sunxi / clock_sun6i.c

/*
 * sun6i specific clock code
 *
 * (C) Copyright 2007-2012
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>

void clock_init_uart(void)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	/* uart clock source is apb2 */
	writel(APB2_CLK_SRC_OSC24M|
	       APB2_CLK_RATE_N_1|
	       APB2_CLK_RATE_M(1),
	       &ccm->apb2_div);

	/* open the clock for uart */
	setbits_le32(&ccm->apb2_gate,
		     CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
				       CONFIG_CONS_INDEX - 1));

	/* deassert uart reset */
	setbits_le32(&ccm->apb2_reset_cfg,
		     1 << (APB2_RESET_UART_SHIFT +
			   CONFIG_CONS_INDEX - 1));

	/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
}

int clock_twi_onoff(int port, int state)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	if (port > 3)
		return -1;

	/* set the apb clock gate for twi */
	if (state)
		setbits_le32(&ccm->apb2_gate,
			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
	else
		clrbits_le32(&ccm->apb2_gate,
			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));

	return 0;
}

unsigned int clock_get_pll6(void)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	uint32_t rval = readl(&ccm->pll6_cfg);
	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
	return 24000000 * n * k / 2;
}
Commit	Line	Data
14177e47 CYT	1	/*
	2	* sun6i specific clock code
	3	*
	4	* (C) Copyright 2007-2012
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#include <common.h>
	14	#include <asm/io.h>
	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/sys_proto.h>
	17
	18	void clock_init_uart(void)
	19	{
	20	struct sunxi_ccm_reg *const ccm =
	21	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	22
	23	/* uart clock source is apb2 */
	24	writel(APB2_CLK_SRC_OSC24M\|
	25	APB2_CLK_RATE_N_1\|
	26	APB2_CLK_RATE_M(1),
	27	&ccm->apb2_div);
	28
	29	/* open the clock for uart */
	30	setbits_le32(&ccm->apb2_gate,
	31	CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
	32	CONFIG_CONS_INDEX - 1));
	33
	34	/* deassert uart reset */
	35	setbits_le32(&ccm->apb2_reset_cfg,
	36	1 << (APB2_RESET_UART_SHIFT +
	37	CONFIG_CONS_INDEX - 1));
	38
	39	/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
	40	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
	41	}
	42
	43	int clock_twi_onoff(int port, int state)
	44	{
	45	struct sunxi_ccm_reg *const ccm =
	46	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	47
	48	if (port > 3)
	49	return -1;
	50
	51	/* set the apb clock gate for twi */
	52	if (state)
	53	setbits_le32(&ccm->apb2_gate,
	54	CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
	55	else
	56	clrbits_le32(&ccm->apb2_gate,
	57	CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
	58
	59	return 0;
	60	}
	61
	62	unsigned int clock_get_pll6(void)
	63	{
	64	struct sunxi_ccm_reg *const ccm =
65	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
66	uint32_t rval = readl(&ccm->pll6_cfg);
67	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
68	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
69	return 24000000 * n * k / 2;
70	}