[people/ms/u-boot.git] / arch / arm / cpu / armv7 / sunxi / clock_sun6i.c

/*
 * sun6i specific clock code
 *
 * (C) Copyright 2007-2012
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>

#ifdef CONFIG_SPL_BUILD
void clock_init_safe(void)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	struct sunxi_prcm_reg * const prcm =
		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;

	/* Set PLL ldo voltage without this PLL6 does not work properly */
	clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
			PRCM_PLL_CTRL_LDO_KEY);
	clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
		PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);

	clock_set_pll1(408000000);

	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
	while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
		;

	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);

	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
	writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
}
#endif

void clock_init_uart(void)
{
#if CONFIG_CONS_INDEX < 5
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	/* uart clock source is apb2 */
	writel(APB2_CLK_SRC_OSC24M|
	       APB2_CLK_RATE_N_1|
	       APB2_CLK_RATE_M(1),
	       &ccm->apb2_div);

	/* open the clock for uart */
	setbits_le32(&ccm->apb2_gate,
		     CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
				       CONFIG_CONS_INDEX - 1));

	/* deassert uart reset */
	setbits_le32(&ccm->apb2_reset_cfg,
		     1 << (APB2_RESET_UART_SHIFT +
			   CONFIG_CONS_INDEX - 1));
#else
	/* enable R_PIO and R_UART clocks, and de-assert resets */
	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
#endif
}

int clock_twi_onoff(int port, int state)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	if (port == 5) {
		if (state)
			prcm_apb0_enable(
				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
		else
			prcm_apb0_disable(
				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
		return 0;
	}

	/* set the apb clock gate for twi */
	if (state)
		setbits_le32(&ccm->apb2_gate,
			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
	else
		clrbits_le32(&ccm->apb2_gate,
			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));

	return 0;
}

#ifdef CONFIG_SPL_BUILD
void clock_set_pll1(unsigned int clk)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	const int p = 0;
	int k = 1;
	int m = 1;

	if (clk > 1152000000) {
		k = 2;
	} else if (clk > 768000000) {
		k = 3;
		m = 2;
	}

	/* Switch to 24MHz clock while changing PLL1 */
	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
	       ATB_DIV_2 << ATB_DIV_SHIFT |
	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
	       &ccm->cpu_axi_cfg);

	/*
	 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
	 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
	 */
	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
	       CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
	       CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
	sdelay(200);

	/* Switch CPU to PLL1 */
	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
	       ATB_DIV_2 << ATB_DIV_SHIFT |
	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
	       &ccm->cpu_axi_cfg);
}
#endif

void clock_set_pll3(unsigned int clk)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */

	if (clk == 0) {
		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
		return;
	}

	/* PLL3 rate = 24000000 * n / m */
	writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
	       CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
	       &ccm->pll3_cfg);
}

void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	const int max_n = 32;
	int k = 1, m = 2;

	if (sigma_delta_enable)
		writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);

	/* PLL5 rate = 24000000 * n * k / m */
	if (clk > 24000000 * k * max_n / m) {
		m = 1;
		if (clk > 24000000 * k * max_n / m)
			k = 2;
	}
	writel(CCM_PLL5_CTRL_EN |
	       (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
	       CCM_PLL5_CTRL_UPD |
	       CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
	       CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);

	udelay(5500);
}

#ifdef CONFIG_MACH_SUN6I
void clock_set_mipi_pll(unsigned int clk)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	unsigned int k, m, n, value, diff;
	unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
	unsigned int src = clock_get_pll3();

	/* All calculations are in KHz to avoid overflows */
	clk /= 1000;
	src /= 1000;

	/* Pick the closest lower clock */
	for (k = 1; k <= 4; k++) {
		for (m = 1; m <= 16; m++) {
			for (n = 1; n <= 16; n++) {
				value = src * n * k / m;
				if (value > clk)
					continue;

				diff = clk - value;
				if (diff < best_diff) {
					best_diff = diff;
					best_k = k;
					best_m = m;
					best_n = n;
				}
				if (diff == 0)
					goto done;
			}
		}
	}

done:
	writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
	       CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
	       CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
}
#endif

#ifdef CONFIG_MACH_SUN8I_A33
void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	if (sigma_delta_enable)
		writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);

	writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
	       (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
	       CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);

	while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
		;
}
#endif

unsigned int clock_get_pll3(void)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	uint32_t rval = readl(&ccm->pll3_cfg);
	int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
	int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;

	/* Multiply by 1000 after dividing by m to avoid integer overflows */
	return (24000 * n / m) * 1000;
}

unsigned int clock_get_pll6(void)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	uint32_t rval = readl(&ccm->pll6_cfg);
	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
	return 24000000 * n * k / 2;
}

unsigned int clock_get_mipi_pll(void)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	uint32_t rval = readl(&ccm->mipi_pll_cfg);
	unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
	unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
	unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
	unsigned int src = clock_get_pll3();

	/* Multiply by 1000 after dividing by m to avoid integer overflows */
	return ((src / 1000) * n * k / m) * 1000;
}

void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
{
	int pll = clock_get_pll6() * 2;
	int div = 1;

	while ((pll / div) > hz)
		div++;

	writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
	       clk_cfg);
}
Commit	Line	Data
14177e47 CYT	1	/*
	2	* sun6i specific clock code
	3	*
	4	* (C) Copyright 2007-2012
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#include <common.h>
	14	#include <asm/io.h>
	15	#include <asm/arch/clock.h>
c757a50b	16	#include <asm/arch/prcm.h>
14177e47 CYT	17	#include <asm/arch/sys_proto.h>
14177e47 CYT	18
62c87ef2 HG	19	#ifdef CONFIG_SPL_BUILD
	20	void clock_init_safe(void)
	21	{
	22	struct sunxi_ccm_reg * const ccm =
	23	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	24	struct sunxi_prcm_reg * const prcm =
	25	(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
	26
	27	/* Set PLL ldo voltage without this PLL6 does not work properly */
	28	clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
	29	PRCM_PLL_CTRL_LDO_KEY);
	30	clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
	31	PRCM_PLL_CTRL_LDO_DIGITAL_EN \| PRCM_PLL_CTRL_LDO_ANALOG_EN \|
	32	PRCM_PLL_CTRL_EXT_OSC_EN \| PRCM_PLL_CTRL_LDO_OUT_L(1140));
	33	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
	34
	35	clock_set_pll1(408000000);
	36
62c87ef2	37	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
52d09311 SS	38	while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
	39	;
	40
	41	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
62c87ef2 HG	42
	43	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
	44	writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
	45	}
	46	#endif
	47
14177e47 CYT	48	void clock_init_uart(void)
14177e47 CYT	49	{
22b61834	50	#if CONFIG_CONS_INDEX < 5
14177e47 CYT	51	struct sunxi_ccm_reg *const ccm =
	52	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	53
	54	/* uart clock source is apb2 */
	55	writel(APB2_CLK_SRC_OSC24M\|
	56	APB2_CLK_RATE_N_1\|
	57	APB2_CLK_RATE_M(1),
	58	&ccm->apb2_div);
	59
	60	/* open the clock for uart */
	61	setbits_le32(&ccm->apb2_gate,
	62	CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
	63	CONFIG_CONS_INDEX - 1));
	64
	65	/* deassert uart reset */
	66	setbits_le32(&ccm->apb2_reset_cfg,
	67	1 << (APB2_RESET_UART_SHIFT +
	68	CONFIG_CONS_INDEX - 1));
c757a50b CYT	69	#else
	70	/* enable R_PIO and R_UART clocks, and de-assert resets */
	71	prcm_apb0_enable(PRCM_APB0_GATE_PIO \| PRCM_APB0_GATE_UART);
	72	#endif
14177e47 CYT	73	}
	74
	75	int clock_twi_onoff(int port, int state)
	76	{
	77	struct sunxi_ccm_reg *const ccm =
	78	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	79
9d082687 JW	80	if (port == 5) {
	81	if (state)
	82	prcm_apb0_enable(
	83	PRCM_APB0_GATE_PIO \| PRCM_APB0_GATE_I2C);
	84	else
	85	prcm_apb0_disable(
	86	PRCM_APB0_GATE_PIO \| PRCM_APB0_GATE_I2C);
	87	return 0;
	88	}
	89
14177e47 CYT	90	/* set the apb clock gate for twi */
	91	if (state)
	92	setbits_le32(&ccm->apb2_gate,
	93	CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
	94	else
	95	clrbits_le32(&ccm->apb2_gate,
	96	CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
	97
	98	return 0;
	99	}
	100
62c87ef2 HG	101	#ifdef CONFIG_SPL_BUILD
	102	void clock_set_pll1(unsigned int clk)
	103	{
	104	struct sunxi_ccm_reg * const ccm =
	105	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
25508ab2	106	const int p = 0;
62c87ef2 HG	107	int k = 1;
	108	int m = 1;
	109
	110	if (clk > 1152000000) {
	111	k = 2;
	112	} else if (clk > 768000000) {
	113	k = 3;
	114	m = 2;
	115	}
	116
	117	/* Switch to 24MHz clock while changing PLL1 */
	118	writel(AXI_DIV_3 << AXI_DIV_SHIFT \|
	119	ATB_DIV_2 << ATB_DIV_SHIFT \|
	120	CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
	121	&ccm->cpu_axi_cfg);
	122
25508ab2 HG	123	/*
	124	* sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
	125	* sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
	126	*/
	127	writel(CCM_PLL1_CTRL_EN \| CCM_PLL1_CTRL_P(p) \|
62c87ef2 HG	128	CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) \|
	129	CCM_PLL1_CTRL_K(k) \| CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
	130	sdelay(200);
	131
	132	/* Switch CPU to PLL1 */
	133	writel(AXI_DIV_3 << AXI_DIV_SHIFT \|
	134	ATB_DIV_2 << ATB_DIV_SHIFT \|
	135	CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
	136	&ccm->cpu_axi_cfg);
	137	}
	138	#endif
	139
0bd51251 HG	140	void clock_set_pll3(unsigned int clk)
	141	{
	142	struct sunxi_ccm_reg * const ccm =
	143	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	144	const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
	145
	146	if (clk == 0) {
	147	clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
	148	return;
	149	}
	150
	151	/* PLL3 rate = 24000000 * n / m */
	152	writel(CCM_PLL3_CTRL_EN \| CCM_PLL3_CTRL_INTEGER_MODE \|
	153	CCM_PLL3_CTRL_N(clk / (24000000 / m)) \| CCM_PLL3_CTRL_M(m),
	154	&ccm->pll3_cfg);
	155	}
	156
5af741f1	157	void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
62c87ef2 HG	158	{
	159	struct sunxi_ccm_reg * const ccm =
	160	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
1aac47bd HG	161	const int max_n = 32;
1aac47bd HG	162	int k = 1, m = 2;
62c87ef2	163
5af741f1 HG	164	if (sigma_delta_enable)
	165	writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
	166
62c87ef2	167	/* PLL5 rate = 24000000 * n * k / m */
1aac47bd HG	168	if (clk > 24000000 * k * max_n / m) {
	169	m = 1;
	170	if (clk > 24000000 * k * max_n / m)
	171	k = 2;
	172	}
5af741f1 HG	173	writel(CCM_PLL5_CTRL_EN \|
	174	(sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) \|
	175	CCM_PLL5_CTRL_UPD \|
62c87ef2 HG	176	CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) \|
	177	CCM_PLL5_CTRL_K(k) \| CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
	178
	179	udelay(5500);
	180	}
	181
55ea98d8 HG	182	#ifdef CONFIG_MACH_SUN6I
	183	void clock_set_mipi_pll(unsigned int clk)
	184	{
	185	struct sunxi_ccm_reg * const ccm =
	186	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	187	unsigned int k, m, n, value, diff;
	188	unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
	189	unsigned int src = clock_get_pll3();
	190
	191	/* All calculations are in KHz to avoid overflows */
	192	clk /= 1000;
	193	src /= 1000;
	194
	195	/* Pick the closest lower clock */
	196	for (k = 1; k <= 4; k++) {
	197	for (m = 1; m <= 16; m++) {
	198	for (n = 1; n <= 16; n++) {
	199	value = src * n * k / m;
	200	if (value > clk)
	201	continue;
	202
	203	diff = clk - value;
	204	if (diff < best_diff) {
	205	best_diff = diff;
	206	best_k = k;
	207	best_m = m;
	208	best_n = n;
	209	}
	210	if (diff == 0)
	211	goto done;
	212	}
	213	}
	214	}
	215
	216	done:
	217	writel(CCM_MIPI_PLL_CTRL_EN \| CCM_MIPI_PLL_CTRL_LDO_EN \|
	218	CCM_MIPI_PLL_CTRL_N(best_n) \| CCM_MIPI_PLL_CTRL_K(best_k) \|
	219	CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
	220	}
	221	#endif
	222
886a7b45 HG	223	#ifdef CONFIG_MACH_SUN8I_A33
	224	void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
	225	{
	226	struct sunxi_ccm_reg * const ccm =
	227	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	228
	229	if (sigma_delta_enable)
	230	writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
	231
	232	writel(CCM_PLL11_CTRL_EN \| CCM_PLL11_CTRL_UPD \|
	233	(sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) \|
	234	CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
	235
	236	while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
	237	;
	238	}
	239	#endif
	240
49043cba HG	241	unsigned int clock_get_pll3(void)
	242	{
	243	struct sunxi_ccm_reg *const ccm =
	244	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	245	uint32_t rval = readl(&ccm->pll3_cfg);
	246	int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
	247	int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
	248
	249	/* Multiply by 1000 after dividing by m to avoid integer overflows */
	250	return (24000 * n / m) * 1000;
	251	}
	252
14177e47 CYT	253	unsigned int clock_get_pll6(void)
	254	{
	255	struct sunxi_ccm_reg *const ccm =
	256	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	257	uint32_t rval = readl(&ccm->pll6_cfg);
	258	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
	259	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
	260	return 24000000 * n * k / 2;
	261	}
0bd51251	262
55ea98d8 HG	263	unsigned int clock_get_mipi_pll(void)
	264	{
	265	struct sunxi_ccm_reg *const ccm =
	266	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	267	uint32_t rval = readl(&ccm->mipi_pll_cfg);
	268	unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
	269	unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
	270	unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
	271	unsigned int src = clock_get_pll3();
	272
	273	/* Multiply by 1000 after dividing by m to avoid integer overflows */
	274	return ((src / 1000) * n * k / m) * 1000;
	275	}
	276
0bd51251 HG	277	void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
	278	{
	279	int pll = clock_get_pll6() * 2;
	280	int div = 1;
	281
	282	while ((pll / div) > hz)
	283	div++;
	284
	285	writel(CCM_DE_CTRL_GATE \| CCM_DE_CTRL_PLL6_2X \| CCM_DE_CTRL_M(div),
	286	clk_cfg);
	287	}