[people/ms/u-boot.git] / arch / arm / cpu / armv7 / sunxi / clock_sun6i.c

/*
 * sun6i specific clock code
 *
 * (C) Copyright 2007-2012
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>

#ifdef CONFIG_SPL_BUILD
void clock_init_safe(void)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	struct sunxi_prcm_reg * const prcm =
		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;

	/* Set PLL ldo voltage without this PLL6 does not work properly */
	clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
			PRCM_PLL_CTRL_LDO_KEY);
	clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
		PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);

	clock_set_pll1(408000000);

	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
	while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
		;

	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);

	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
	writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
}
#endif

void clock_init_uart(void)
{
#if CONFIG_CONS_INDEX < 5
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	/* uart clock source is apb2 */
	writel(APB2_CLK_SRC_OSC24M|
	       APB2_CLK_RATE_N_1|
	       APB2_CLK_RATE_M(1),
	       &ccm->apb2_div);

	/* open the clock for uart */
	setbits_le32(&ccm->apb2_gate,
		     CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
				       CONFIG_CONS_INDEX - 1));

	/* deassert uart reset */
	setbits_le32(&ccm->apb2_reset_cfg,
		     1 << (APB2_RESET_UART_SHIFT +
			   CONFIG_CONS_INDEX - 1));
#else
	/* enable R_PIO and R_UART clocks, and de-assert resets */
	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
#endif
}

int clock_twi_onoff(int port, int state)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	if (port > 3)
		return -1;

	/* set the apb clock gate for twi */
	if (state)
		setbits_le32(&ccm->apb2_gate,
			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
	else
		clrbits_le32(&ccm->apb2_gate,
			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));

	return 0;
}

#ifdef CONFIG_SPL_BUILD
void clock_set_pll1(unsigned int clk)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	const int p = 0;
	int k = 1;
	int m = 1;

	if (clk > 1152000000) {
		k = 2;
	} else if (clk > 768000000) {
		k = 3;
		m = 2;
	}

	/* Switch to 24MHz clock while changing PLL1 */
	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
	       ATB_DIV_2 << ATB_DIV_SHIFT |
	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
	       &ccm->cpu_axi_cfg);

	/*
	 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
	 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
	 */
	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
	       CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
	       CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
	sdelay(200);

	/* Switch CPU to PLL1 */
	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
	       ATB_DIV_2 << ATB_DIV_SHIFT |
	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
	       &ccm->cpu_axi_cfg);
}
#endif

void clock_set_pll3(unsigned int clk)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */

	if (clk == 0) {
		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
		return;
	}

	/* PLL3 rate = 24000000 * n / m */
	writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
	       CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
	       &ccm->pll3_cfg);
}

void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	const int max_n = 32;
	int k = 1, m = 2;

	if (sigma_delta_enable)
		writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);

	/* PLL5 rate = 24000000 * n * k / m */
	if (clk > 24000000 * k * max_n / m) {
		m = 1;
		if (clk > 24000000 * k * max_n / m)
			k = 2;
	}
	writel(CCM_PLL5_CTRL_EN |
	       (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
	       CCM_PLL5_CTRL_UPD |
	       CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
	       CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);

	udelay(5500);
}

#ifdef CONFIG_MACH_SUN6I
void clock_set_mipi_pll(unsigned int clk)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	unsigned int k, m, n, value, diff;
	unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
	unsigned int src = clock_get_pll3();

	/* All calculations are in KHz to avoid overflows */
	clk /= 1000;
	src /= 1000;

	/* Pick the closest lower clock */
	for (k = 1; k <= 4; k++) {
		for (m = 1; m <= 16; m++) {
			for (n = 1; n <= 16; n++) {
				value = src * n * k / m;
				if (value > clk)
					continue;

				diff = clk - value;
				if (diff < best_diff) {
					best_diff = diff;
					best_k = k;
					best_m = m;
					best_n = n;
				}
				if (diff == 0)
					goto done;
			}
		}
	}

done:
	writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
	       CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
	       CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
}
#endif

#ifdef CONFIG_MACH_SUN8I_A33
void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	if (sigma_delta_enable)
		writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);

	writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
	       (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
	       CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);

	while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
		;
}
#endif

unsigned int clock_get_pll3(void)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	uint32_t rval = readl(&ccm->pll3_cfg);
	int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
	int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;

	/* Multiply by 1000 after dividing by m to avoid integer overflows */
	return (24000 * n / m) * 1000;
}

unsigned int clock_get_pll6(void)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	uint32_t rval = readl(&ccm->pll6_cfg);
	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
	return 24000000 * n * k / 2;
}

unsigned int clock_get_mipi_pll(void)
{
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	uint32_t rval = readl(&ccm->mipi_pll_cfg);
	unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
	unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
	unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
	unsigned int src = clock_get_pll3();

	/* Multiply by 1000 after dividing by m to avoid integer overflows */
	return ((src / 1000) * n * k / m) * 1000;
}

void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
{
	int pll = clock_get_pll6() * 2;
	int div = 1;

	while ((pll / div) > hz)
		div++;

	writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
	       clk_cfg);
}
Commit	Line	Data
14177e47 CYT	1	/*
	2	* sun6i specific clock code
	3	*
	4	* (C) Copyright 2007-2012
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#include <common.h>
	14	#include <asm/io.h>
	15	#include <asm/arch/clock.h>
c757a50b	16	#include <asm/arch/prcm.h>
14177e47 CYT	17	#include <asm/arch/sys_proto.h>
14177e47 CYT	18
62c87ef2 HG	19	#ifdef CONFIG_SPL_BUILD
	20	void clock_init_safe(void)
	21	{
	22	struct sunxi_ccm_reg * const ccm =
	23	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	24	struct sunxi_prcm_reg * const prcm =
	25	(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
	26
	27	/* Set PLL ldo voltage without this PLL6 does not work properly */
	28	clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
	29	PRCM_PLL_CTRL_LDO_KEY);
	30	clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
	31	PRCM_PLL_CTRL_LDO_DIGITAL_EN \| PRCM_PLL_CTRL_LDO_ANALOG_EN \|
	32	PRCM_PLL_CTRL_EXT_OSC_EN \| PRCM_PLL_CTRL_LDO_OUT_L(1140));
	33	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
	34
	35	clock_set_pll1(408000000);
	36
62c87ef2	37	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
52d09311 SS	38	while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
	39	;
	40
	41	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
62c87ef2 HG	42
	43	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
	44	writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
	45	}
	46	#endif
	47
14177e47 CYT	48	void clock_init_uart(void)
14177e47 CYT	49	{
22b61834	50	#if CONFIG_CONS_INDEX < 5
14177e47 CYT	51	struct sunxi_ccm_reg *const ccm =
	52	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	53
	54	/* uart clock source is apb2 */
	55	writel(APB2_CLK_SRC_OSC24M\|
	56	APB2_CLK_RATE_N_1\|
	57	APB2_CLK_RATE_M(1),
	58	&ccm->apb2_div);
	59
	60	/* open the clock for uart */
	61	setbits_le32(&ccm->apb2_gate,
	62	CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
	63	CONFIG_CONS_INDEX - 1));
	64
	65	/* deassert uart reset */
	66	setbits_le32(&ccm->apb2_reset_cfg,
	67	1 << (APB2_RESET_UART_SHIFT +
	68	CONFIG_CONS_INDEX - 1));
c757a50b CYT	69	#else
	70	/* enable R_PIO and R_UART clocks, and de-assert resets */
	71	prcm_apb0_enable(PRCM_APB0_GATE_PIO \| PRCM_APB0_GATE_UART);
	72	#endif
14177e47 CYT	73	}
	74
	75	int clock_twi_onoff(int port, int state)
	76	{
	77	struct sunxi_ccm_reg *const ccm =
	78	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	79
	80	if (port > 3)
	81	return -1;
	82
	83	/* set the apb clock gate for twi */
	84	if (state)
	85	setbits_le32(&ccm->apb2_gate,
	86	CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
	87	else
	88	clrbits_le32(&ccm->apb2_gate,
	89	CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
	90
	91	return 0;
	92	}
	93
62c87ef2 HG	94	#ifdef CONFIG_SPL_BUILD
	95	void clock_set_pll1(unsigned int clk)
	96	{
	97	struct sunxi_ccm_reg * const ccm =
	98	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
25508ab2	99	const int p = 0;
62c87ef2 HG	100	int k = 1;
	101	int m = 1;
	102
	103	if (clk > 1152000000) {
	104	k = 2;
	105	} else if (clk > 768000000) {
	106	k = 3;
	107	m = 2;
	108	}
	109
	110	/* Switch to 24MHz clock while changing PLL1 */
	111	writel(AXI_DIV_3 << AXI_DIV_SHIFT \|
	112	ATB_DIV_2 << ATB_DIV_SHIFT \|
	113	CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
	114	&ccm->cpu_axi_cfg);
	115
25508ab2 HG	116	/*
	117	* sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
	118	* sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
	119	*/
	120	writel(CCM_PLL1_CTRL_EN \| CCM_PLL1_CTRL_P(p) \|
62c87ef2 HG	121	CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) \|
	122	CCM_PLL1_CTRL_K(k) \| CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
	123	sdelay(200);
	124
	125	/* Switch CPU to PLL1 */
	126	writel(AXI_DIV_3 << AXI_DIV_SHIFT \|
	127	ATB_DIV_2 << ATB_DIV_SHIFT \|
	128	CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
	129	&ccm->cpu_axi_cfg);
	130	}
	131	#endif
	132
0bd51251 HG	133	void clock_set_pll3(unsigned int clk)
	134	{
	135	struct sunxi_ccm_reg * const ccm =
	136	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	137	const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
	138
	139	if (clk == 0) {
	140	clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
	141	return;
	142	}
	143
	144	/* PLL3 rate = 24000000 * n / m */
	145	writel(CCM_PLL3_CTRL_EN \| CCM_PLL3_CTRL_INTEGER_MODE \|
	146	CCM_PLL3_CTRL_N(clk / (24000000 / m)) \| CCM_PLL3_CTRL_M(m),
	147	&ccm->pll3_cfg);
	148	}
	149
5af741f1	150	void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
62c87ef2 HG	151	{
	152	struct sunxi_ccm_reg * const ccm =
	153	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
1aac47bd HG	154	const int max_n = 32;
1aac47bd HG	155	int k = 1, m = 2;
62c87ef2	156
5af741f1 HG	157	if (sigma_delta_enable)
	158	writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
	159
62c87ef2	160	/* PLL5 rate = 24000000 * n * k / m */
1aac47bd HG	161	if (clk > 24000000 * k * max_n / m) {
	162	m = 1;
	163	if (clk > 24000000 * k * max_n / m)
	164	k = 2;
	165	}
5af741f1 HG	166	writel(CCM_PLL5_CTRL_EN \|
	167	(sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) \|
	168	CCM_PLL5_CTRL_UPD \|
62c87ef2 HG	169	CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) \|
	170	CCM_PLL5_CTRL_K(k) \| CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
	171
	172	udelay(5500);
	173	}
	174
55ea98d8 HG	175	#ifdef CONFIG_MACH_SUN6I
	176	void clock_set_mipi_pll(unsigned int clk)
	177	{
	178	struct sunxi_ccm_reg * const ccm =
	179	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	180	unsigned int k, m, n, value, diff;
	181	unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
	182	unsigned int src = clock_get_pll3();
	183
	184	/* All calculations are in KHz to avoid overflows */
	185	clk /= 1000;
	186	src /= 1000;
	187
	188	/* Pick the closest lower clock */
	189	for (k = 1; k <= 4; k++) {
	190	for (m = 1; m <= 16; m++) {
	191	for (n = 1; n <= 16; n++) {
	192	value = src * n * k / m;
	193	if (value > clk)
	194	continue;
	195
	196	diff = clk - value;
	197	if (diff < best_diff) {
	198	best_diff = diff;
	199	best_k = k;
	200	best_m = m;
	201	best_n = n;
	202	}
	203	if (diff == 0)
	204	goto done;
	205	}
	206	}
	207	}
	208
	209	done:
	210	writel(CCM_MIPI_PLL_CTRL_EN \| CCM_MIPI_PLL_CTRL_LDO_EN \|
	211	CCM_MIPI_PLL_CTRL_N(best_n) \| CCM_MIPI_PLL_CTRL_K(best_k) \|
	212	CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
	213	}
	214	#endif
	215
886a7b45 HG	216	#ifdef CONFIG_MACH_SUN8I_A33
	217	void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
	218	{
	219	struct sunxi_ccm_reg * const ccm =
	220	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	221
	222	if (sigma_delta_enable)
	223	writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
	224
	225	writel(CCM_PLL11_CTRL_EN \| CCM_PLL11_CTRL_UPD \|
	226	(sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) \|
	227	CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
	228
	229	while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
	230	;
	231	}
	232	#endif
	233
49043cba HG	234	unsigned int clock_get_pll3(void)
	235	{
	236	struct sunxi_ccm_reg *const ccm =
	237	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	238	uint32_t rval = readl(&ccm->pll3_cfg);
	239	int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
	240	int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
	241
	242	/* Multiply by 1000 after dividing by m to avoid integer overflows */
	243	return (24000 * n / m) * 1000;
	244	}
	245
14177e47 CYT	246	unsigned int clock_get_pll6(void)
	247	{
	248	struct sunxi_ccm_reg *const ccm =
	249	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	250	uint32_t rval = readl(&ccm->pll6_cfg);
	251	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
	252	int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
	253	return 24000000 * n * k / 2;
	254	}
0bd51251	255
55ea98d8 HG	256	unsigned int clock_get_mipi_pll(void)
	257	{
	258	struct sunxi_ccm_reg *const ccm =
	259	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	260	uint32_t rval = readl(&ccm->mipi_pll_cfg);
	261	unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
	262	unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
	263	unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
	264	unsigned int src = clock_get_pll3();
	265
	266	/* Multiply by 1000 after dividing by m to avoid integer overflows */
	267	return ((src / 1000) * n * k / m) * 1000;
	268	}
	269
0bd51251 HG	270	void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
	271	{
	272	int pll = clock_get_pll6() * 2;
	273	int div = 1;
	274
	275	while ((pll / div) > hz)
	276	div++;
	277
	278	writel(CCM_DE_CTRL_GATE \| CCM_DE_CTRL_PLL6_2X \| CCM_DE_CTRL_M(div),
	279	clk_cfg);
	280	}