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87f938c9 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/io.h> | |
26 | #include <asm-generic/gpio.h> | |
00a2749d | 27 | #include <asm/arch/tegra20.h> |
87f938c9 SG |
28 | #include <asm/arch/clk_rst.h> |
29 | #include <asm/arch/clock.h> | |
30 | #include <asm/arch/gpio.h> | |
31 | #include <asm/arch/pinmux.h> | |
32 | #include <asm/arch/sys_proto.h> | |
33 | #include <asm/arch/uart.h> | |
34 | #include <asm/arch/usb.h> | |
35 | #include <libfdt.h> | |
36 | #include <fdtdec.h> | |
37 | ||
38 | enum { | |
39 | USB_PORTS_MAX = 4, /* Maximum ports we allow */ | |
40 | }; | |
41 | ||
42 | /* Parameters we need for USB */ | |
43 | enum { | |
44 | PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ | |
45 | PARAM_DIVM, /* PLL INPUT DIVIDER */ | |
46 | PARAM_DIVP, /* POST DIVIDER (2^N) */ | |
47 | PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ | |
48 | PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ | |
49 | PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ | |
50 | PARAM_STABLE_COUNT, /* PLL-U STABLE count */ | |
51 | PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ | |
52 | PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ | |
53 | PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ | |
54 | PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ | |
55 | ||
56 | PARAM_COUNT | |
57 | }; | |
58 | ||
59 | /* Possible port types (dual role mode) */ | |
60 | enum dr_mode { | |
61 | DR_MODE_NONE = 0, | |
62 | DR_MODE_HOST, /* supports host operation */ | |
63 | DR_MODE_DEVICE, /* supports device operation */ | |
64 | DR_MODE_OTG, /* supports both */ | |
65 | }; | |
66 | ||
67 | /* Information about a USB port */ | |
68 | struct fdt_usb { | |
69 | struct usb_ctlr *reg; /* address of registers in physical memory */ | |
70 | unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ | |
71 | unsigned enabled:1; /* 1 to enable, 0 to disable */ | |
72 | unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ | |
73 | enum dr_mode dr_mode; /* dual role mode */ | |
74 | enum periph_id periph_id;/* peripheral id */ | |
75 | struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ | |
76 | }; | |
77 | ||
78 | static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ | |
79 | static unsigned port_count; /* Number of available ports */ | |
80 | static int port_current; /* Current port (-1 = none) */ | |
81 | ||
82 | /* | |
83 | * This table has USB timing parameters for each Oscillator frequency we | |
84 | * support. There are four sets of values: | |
85 | * | |
86 | * 1. PLLU configuration information (reference clock is osc/clk_m and | |
87 | * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). | |
88 | * | |
89 | * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz | |
90 | * ---------------------------------------------------------------------- | |
91 | * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) | |
92 | * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) | |
93 | * Filter frequency (MHz) 1 4.8 6 2 | |
94 | * CPCON 1100b 0011b 1100b 1100b | |
95 | * LFCON0 0 0 0 0 | |
96 | * | |
97 | * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: | |
98 | * | |
99 | * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz | |
100 | * --------------------------------------------------------------------------- | |
101 | * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) | |
102 | * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) | |
103 | * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) | |
104 | * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) | |
105 | * | |
106 | * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and | |
107 | * SessEnd. Each of these signals have their own debouncer and for each of | |
108 | * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or | |
109 | * BIAS_DEBOUNCE_B). | |
110 | * | |
111 | * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: | |
112 | * 0xffff -> No debouncing at all | |
113 | * <n> ms = <n> *1000 / (1/19.2MHz) / 4 | |
114 | * | |
115 | * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: | |
116 | * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 | |
117 | * | |
118 | * We need to use only DebounceA for BOOTROM. We don't need the DebounceB | |
119 | * values, so we can keep those to default. | |
120 | * | |
121 | * 4. The 20 microsecond delay after bias cell operation. | |
122 | */ | |
123 | static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { | |
124 | /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ | |
125 | { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, | |
126 | { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, | |
127 | { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, | |
128 | { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } | |
129 | }; | |
130 | ||
131 | /* UTMIP Idle Wait Delay */ | |
132 | static const u8 utmip_idle_wait_delay = 17; | |
133 | ||
134 | /* UTMIP Elastic limit */ | |
135 | static const u8 utmip_elastic_limit = 16; | |
136 | ||
137 | /* UTMIP High Speed Sync Start Delay */ | |
138 | static const u8 utmip_hs_sync_start_delay = 9; | |
139 | ||
22e73940 | 140 | /* Put the port into host mode */ |
87f938c9 SG |
141 | static void set_host_mode(struct fdt_usb *config) |
142 | { | |
22e73940 LS |
143 | /* |
144 | * If we are an OTG port, check if remote host is driving VBus and | |
145 | * bail out in this case. | |
146 | */ | |
147 | if (config->dr_mode == DR_MODE_OTG && | |
148 | (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) | |
149 | return; | |
150 | ||
151 | /* | |
152 | * If not driving, we set the GPIO to enable VBUS. We assume | |
153 | * that the pinmux is set up correctly for this. | |
154 | */ | |
155 | if (fdt_gpio_isvalid(&config->vbus_gpio)) { | |
156 | fdtdec_setup_gpio(&config->vbus_gpio); | |
157 | gpio_direction_output(config->vbus_gpio.gpio, | |
158 | (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? | |
159 | 0 : 1); | |
160 | debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, | |
161 | (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? | |
162 | "low" : "high"); | |
87f938c9 SG |
163 | } |
164 | } | |
165 | ||
166 | void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) | |
167 | { | |
168 | /* Reset the USB controller with 2us delay */ | |
169 | reset_periph(config->periph_id, 2); | |
170 | ||
171 | /* | |
172 | * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under | |
173 | * base address | |
174 | */ | |
175 | if (config->has_legacy_mode) | |
176 | setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); | |
177 | ||
178 | /* Put UTMIP1/3 in reset */ | |
179 | setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); | |
180 | ||
181 | /* Enable the UTMIP PHY */ | |
182 | if (config->utmi) | |
183 | setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); | |
184 | ||
185 | /* | |
186 | * TODO: where do we take the USB1 out of reset? The old code would | |
187 | * take USB3 out of reset, but not USB1. This code doesn't do either. | |
188 | */ | |
189 | } | |
190 | ||
191 | /* set up the USB controller with the parameters provided */ | |
192 | static int init_usb_controller(struct fdt_usb *config, | |
193 | struct usb_ctlr *usbctlr, const u32 timing[]) | |
194 | { | |
195 | u32 val; | |
196 | int loop_count; | |
197 | ||
198 | clock_enable(config->periph_id); | |
199 | ||
200 | /* Reset the usb controller */ | |
201 | usbf_reset_controller(config, usbctlr); | |
202 | ||
203 | /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ | |
204 | clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); | |
205 | ||
206 | /* Follow the crystal clock disable by >100ns delay */ | |
207 | udelay(1); | |
208 | ||
209 | /* | |
210 | * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP | |
211 | * mux must be switched to actually use a_sess_vld threshold. | |
212 | */ | |
213 | if (fdt_gpio_isvalid(&config->vbus_gpio)) { | |
214 | clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, | |
215 | VBUS_SENSE_CTL_MASK, | |
216 | VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); | |
217 | } | |
218 | ||
219 | /* | |
220 | * PLL Delay CONFIGURATION settings. The following parameters control | |
221 | * the bring up of the plls. | |
222 | */ | |
223 | val = readl(&usbctlr->utmip_misc_cfg1); | |
224 | clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, | |
225 | timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); | |
226 | clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, | |
227 | timing[PARAM_ACTIVE_DELAY_COUNT] << | |
228 | UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); | |
229 | writel(val, &usbctlr->utmip_misc_cfg1); | |
230 | ||
231 | /* Set PLL enable delay count and crystal frequency count */ | |
232 | val = readl(&usbctlr->utmip_pll_cfg1); | |
233 | clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, | |
234 | timing[PARAM_ENABLE_DELAY_COUNT] << | |
235 | UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); | |
236 | clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, | |
237 | timing[PARAM_XTAL_FREQ_COUNT] << | |
238 | UTMIP_XTAL_FREQ_COUNT_SHIFT); | |
239 | writel(val, &usbctlr->utmip_pll_cfg1); | |
240 | ||
241 | /* Setting the tracking length time */ | |
242 | clrsetbits_le32(&usbctlr->utmip_bias_cfg1, | |
243 | UTMIP_BIAS_PDTRK_COUNT_MASK, | |
244 | timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); | |
245 | ||
246 | /* Program debounce time for VBUS to become valid */ | |
247 | clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, | |
248 | UTMIP_DEBOUNCE_CFG0_MASK, | |
249 | timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); | |
250 | ||
251 | setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); | |
252 | ||
253 | /* Disable battery charge enabling bit */ | |
254 | setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); | |
255 | ||
256 | clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); | |
257 | setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); | |
258 | ||
259 | /* | |
260 | * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT | |
261 | * Setting these fields, together with default values of the | |
262 | * other fields, results in programming the registers below as | |
263 | * follows: | |
264 | * UTMIP_HSRX_CFG0 = 0x9168c000 | |
265 | * UTMIP_HSRX_CFG1 = 0x13 | |
266 | */ | |
267 | ||
268 | /* Set PLL enable delay count and Crystal frequency count */ | |
269 | val = readl(&usbctlr->utmip_hsrx_cfg0); | |
270 | clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, | |
271 | utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); | |
272 | clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, | |
273 | utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); | |
274 | writel(val, &usbctlr->utmip_hsrx_cfg0); | |
275 | ||
276 | /* Configure the UTMIP_HS_SYNC_START_DLY */ | |
277 | clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, | |
278 | UTMIP_HS_SYNC_START_DLY_MASK, | |
279 | utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); | |
280 | ||
281 | /* Preceed the crystal clock disable by >100ns delay. */ | |
282 | udelay(1); | |
283 | ||
284 | /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ | |
285 | setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); | |
286 | ||
287 | /* Finished the per-controller init. */ | |
288 | ||
289 | /* De-assert UTMIP_RESET to bring out of reset. */ | |
290 | clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); | |
291 | ||
292 | /* Wait for the phy clock to become valid in 100 ms */ | |
293 | for (loop_count = 100000; loop_count != 0; loop_count--) { | |
294 | if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) | |
295 | break; | |
296 | udelay(1); | |
297 | } | |
f857fff6 | 298 | if (!loop_count) |
87f938c9 SG |
299 | return -1; |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
304 | static void power_up_port(struct usb_ctlr *usbctlr) | |
305 | { | |
306 | /* Deassert power down state */ | |
307 | clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | | |
308 | UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); | |
309 | clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | | |
310 | UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); | |
311 | } | |
312 | ||
313 | static void config_clock(const u32 timing[]) | |
314 | { | |
315 | clock_start_pll(CLOCK_ID_USB, | |
316 | timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], | |
317 | timing[PARAM_CPCON], timing[PARAM_LFCON]); | |
318 | } | |
319 | ||
320 | /** | |
321 | * Add a new USB port to the list of available ports. | |
322 | * | |
323 | * @param config USB port configuration | |
324 | * @return 0 if ok, -1 if error (too many ports) | |
325 | */ | |
326 | static int add_port(struct fdt_usb *config, const u32 timing[]) | |
327 | { | |
328 | struct usb_ctlr *usbctlr = config->reg; | |
329 | ||
330 | if (port_count == USB_PORTS_MAX) { | |
331 | debug("tegrausb: Cannot register more than %d ports\n", | |
332 | USB_PORTS_MAX); | |
333 | return -1; | |
334 | } | |
335 | if (init_usb_controller(config, usbctlr, timing)) { | |
336 | debug("tegrausb: Cannot init port\n"); | |
337 | return -1; | |
338 | } | |
339 | if (config->utmi) { | |
340 | /* Disable ICUSB FS/LS transceiver */ | |
341 | clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); | |
342 | ||
343 | /* Select UTMI parallel interface */ | |
344 | clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, | |
345 | PTS_UTMI << PTS_SHIFT); | |
346 | clrbits_le32(&usbctlr->port_sc1, STS); | |
347 | power_up_port(usbctlr); | |
348 | } | |
349 | port[port_count++] = *config; | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor) | |
355 | { | |
356 | struct usb_ctlr *usbctlr; | |
357 | ||
358 | if (portnum >= port_count) | |
359 | return -1; | |
360 | tegrausb_stop_port(); | |
361 | set_host_mode(&port[portnum]); | |
362 | ||
363 | usbctlr = port[portnum].reg; | |
364 | *hccr = (u32)&usbctlr->cap_length; | |
365 | *hcor = (u32)&usbctlr->usb_cmd; | |
366 | port_current = portnum; | |
367 | return 0; | |
368 | } | |
369 | ||
370 | int tegrausb_stop_port(void) | |
371 | { | |
372 | struct usb_ctlr *usbctlr; | |
373 | ||
374 | if (port_current == -1) | |
375 | return -1; | |
376 | ||
377 | usbctlr = port[port_current].reg; | |
378 | ||
379 | /* Stop controller */ | |
380 | writel(0, &usbctlr->usb_cmd); | |
381 | udelay(1000); | |
382 | ||
383 | /* Initiate controller reset */ | |
384 | writel(2, &usbctlr->usb_cmd); | |
385 | udelay(1000); | |
386 | port_current = -1; | |
387 | return 0; | |
388 | } | |
389 | ||
390 | int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz, | |
391 | struct fdt_usb *config) | |
392 | { | |
393 | const char *phy, *mode; | |
394 | ||
395 | config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); | |
396 | mode = fdt_getprop(blob, node, "dr_mode", NULL); | |
397 | if (mode) { | |
398 | if (0 == strcmp(mode, "host")) | |
399 | config->dr_mode = DR_MODE_HOST; | |
400 | else if (0 == strcmp(mode, "peripheral")) | |
401 | config->dr_mode = DR_MODE_DEVICE; | |
402 | else if (0 == strcmp(mode, "otg")) | |
403 | config->dr_mode = DR_MODE_OTG; | |
404 | else { | |
405 | debug("%s: Cannot decode dr_mode '%s'\n", __func__, | |
406 | mode); | |
407 | return -FDT_ERR_NOTFOUND; | |
408 | } | |
409 | } else { | |
410 | config->dr_mode = DR_MODE_HOST; | |
411 | } | |
412 | ||
413 | phy = fdt_getprop(blob, node, "phy_type", NULL); | |
414 | config->utmi = phy && 0 == strcmp("utmi", phy); | |
415 | config->enabled = fdtdec_get_is_enabled(blob, node); | |
416 | config->has_legacy_mode = fdtdec_get_bool(blob, node, | |
417 | "nvidia,has-legacy-mode"); | |
418 | config->periph_id = clock_decode_periph_id(blob, node); | |
419 | if (config->periph_id == PERIPH_ID_NONE) { | |
420 | debug("%s: Missing/invalid peripheral ID\n", __func__); | |
421 | return -FDT_ERR_NOTFOUND; | |
422 | } | |
423 | fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); | |
424 | debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, " | |
425 | "dr_mode=%d\n", config->enabled, config->has_legacy_mode, | |
426 | config->utmi, config->periph_id, config->vbus_gpio.gpio, | |
427 | config->dr_mode); | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
432 | int board_usb_init(const void *blob) | |
433 | { | |
434 | struct fdt_usb config; | |
435 | unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC); | |
436 | enum clock_osc_freq freq; | |
437 | int node_list[USB_PORTS_MAX]; | |
438 | int node, count, i; | |
439 | ||
440 | /* Set up the USB clocks correctly based on our oscillator frequency */ | |
441 | freq = clock_get_osc_freq(); | |
442 | config_clock(usb_pll[freq]); | |
443 | ||
444 | /* count may return <0 on error */ | |
445 | count = fdtdec_find_aliases_for_id(blob, "usb", | |
446 | COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); | |
447 | for (i = 0; i < count; i++) { | |
448 | debug("USB %d: ", i); | |
449 | node = node_list[i]; | |
450 | if (!node) | |
451 | continue; | |
452 | if (fdt_decode_usb(blob, node, osc_freq, &config)) { | |
453 | debug("Cannot decode USB node %s\n", | |
454 | fdt_get_name(blob, node, NULL)); | |
455 | return -1; | |
456 | } | |
457 | ||
458 | if (add_port(&config, usb_pll[freq])) | |
459 | return -1; | |
460 | set_host_mode(&config); | |
461 | } | |
462 | port_current = -1; | |
463 | ||
464 | return 0; | |
465 | } |