]>
Commit | Line | Data |
---|---|---|
be72e0c8 JR |
1 | /* |
2 | * (C) Copyright 2009 ST-Ericsson | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
be72e0c8 JR |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/io.h> | |
9 | #include <asm/arch/hardware.h> | |
10 | ||
11 | DECLARE_GLOBAL_DATA_PTR; | |
12 | ||
13 | struct clkrst { | |
14 | unsigned int pcken; | |
15 | unsigned int pckdis; | |
16 | unsigned int kcken; | |
17 | unsigned int kckdis; | |
18 | }; | |
19 | ||
20 | static unsigned int clkrst_base[] = { | |
21 | U8500_CLKRST1_BASE, | |
22 | U8500_CLKRST2_BASE, | |
23 | U8500_CLKRST3_BASE, | |
24 | 0, | |
25 | U8500_CLKRST5_BASE, | |
26 | U8500_CLKRST6_BASE, | |
27 | U8500_CLKRST7_BASE, /* ED only */ | |
28 | }; | |
29 | ||
30 | /* Turn on peripheral clock at PRCC level */ | |
31 | void u8500_clock_enable(int periph, int cluster, int kern) | |
32 | { | |
33 | struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1]; | |
34 | ||
35 | if (kern != -1) | |
36 | writel(1 << kern, &clkrst->kcken); | |
37 | ||
38 | if (cluster != -1) | |
39 | writel(1 << cluster, &clkrst->pcken); | |
40 | } | |
81637e26 MP |
41 | |
42 | void db8500_clocks_init(void) | |
43 | { | |
44 | /* | |
45 | * Enable all clocks. This is u-boot, we can enable it all. There is no | |
46 | * powersave in u-boot. | |
47 | */ | |
48 | ||
49 | u8500_clock_enable(1, 9, -1); /* GPIO0 */ | |
50 | u8500_clock_enable(2, 11, -1);/* GPIO1 */ | |
51 | u8500_clock_enable(3, 8, -1); /* GPIO2 */ | |
52 | u8500_clock_enable(5, 1, -1); /* GPIO3 */ | |
53 | u8500_clock_enable(3, 6, 6); /* UART2 */ | |
54 | u8500_clock_enable(3, 3, 3); /* I2C0 */ | |
55 | u8500_clock_enable(1, 5, 5); /* SDI0 */ | |
56 | u8500_clock_enable(2, 4, 2); /* SDI4 */ | |
57 | u8500_clock_enable(6, 6, -1); /* MTU0 */ | |
58 | u8500_clock_enable(3, 4, 4); /* SDI2 */ | |
59 | ||
60 | /* | |
61 | * Enabling clocks for all devices which are AMBA devices in the | |
62 | * kernel. Otherwise they will not get probe()'d because the | |
63 | * peripheral ID register will not be powered. | |
64 | */ | |
65 | ||
66 | /* XXX: some of these differ between ED/V1 */ | |
67 | ||
68 | u8500_clock_enable(1, 1, 1); /* UART1 */ | |
69 | u8500_clock_enable(1, 0, 0); /* UART0 */ | |
70 | u8500_clock_enable(3, 2, 2); /* SSP1 */ | |
71 | u8500_clock_enable(3, 1, 1); /* SSP0 */ | |
72 | u8500_clock_enable(2, 8, -1); /* SPI0 */ | |
73 | u8500_clock_enable(2, 5, 3); /* MSP2 */ | |
74 | } |