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1 | /* |
2 | * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> | |
3 | * Copyright (C) 2012 Xilinx, Inc. All rights reserved. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
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6 | */ |
7 | #include <common.h> | |
00ed3458 | 8 | #include <asm/io.h> |
59c651f4 | 9 | #include <asm/arch/sys_proto.h> |
00ed3458 | 10 | #include <asm/arch/hardware.h> |
38b343dd | 11 | |
00ed3458 MS |
12 | void lowlevel_init(void) |
13 | { | |
14 | zynq_slcr_unlock(); | |
15 | /* remap DDR to zero, FILTERSTART */ | |
16 | writel(0, &scu_base->filter_start); | |
17 | ||
18 | /* Device config APB, unlock the PCAP */ | |
19 | writel(0x757BDF0D, &devcfg_base->unlock); | |
20 | writel(0xFFFFFFFF, &devcfg_base->rom_shadow); | |
21 | ||
22 | /* OCM_CFG, Mask out the ROM, map ram into upper addresses */ | |
23 | writel(0x1F, &slcr_base->ocm_cfg); | |
24 | /* FPGA_RST_CTRL, clear resets on AXI fabric ports */ | |
25 | writel(0x0, &slcr_base->fpga_rst_ctrl); | |
26 | /* TZ_DDR_RAM, Set DDR trust zone non-secure */ | |
27 | writel(0xFFFFFFFF, &slcr_base->trust_zone); | |
28 | /* Set urgent bits with register */ | |
29 | writel(0x0, &slcr_base->ddr_urgent_sel); | |
30 | /* Urgent write, ports S2/S3 */ | |
31 | writel(0xC, &slcr_base->ddr_urgent); | |
32 | ||
33 | zynq_slcr_lock(); | |
34 | } | |
38b343dd MS |
35 | |
36 | void reset_cpu(ulong addr) | |
37 | { | |
59c651f4 | 38 | zynq_slcr_cpu_reset(); |
38b343dd MS |
39 | while (1) |
40 | ; | |
41 | } |