[people/ms/u-boot.git] / arch / arm / cpu / armv7 / zynq / slcr.c

/*
 * Copyright (c) 2013 Xilinx Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>

#define SLCR_LOCK_MAGIC		0x767B
#define SLCR_UNLOCK_MAGIC	0xDF0D

#define SLCR_IDCODE_MASK	0x1F000
#define SLCR_IDCODE_SHIFT	12

static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */

void zynq_slcr_lock(void)
{
	if (!slcr_lock)
		writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
}

void zynq_slcr_unlock(void)
{
	if (slcr_lock)
		writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
}

/* Reset the entire system */
void zynq_slcr_cpu_reset(void)
{
	/*
	 * Unlock the SLCR then reset the system.
	 * Note that this seems to require raw i/o
	 * functions or there's a lockup?
	 */
	zynq_slcr_unlock();

	/*
	 * Clear 0x0F000000 bits of reboot status register to workaround
	 * the FSBL not loading the bitstream after soft-reboot
	 * This is a temporary solution until we know more.
	 */
	clrbits_le32(&slcr_base->reboot_status, 0xF000000);

	writel(1, &slcr_base->pss_rst_ctrl);
}

/* Setup clk for network */
void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
{
	zynq_slcr_unlock();

	if (gem_id > 1) {
		printf("Non existing GEM id %d\n", gem_id);
		goto out;
	}

	if (gem_id) {
		/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
		writel(clk, &slcr_base->gem1_clk_ctrl);
		/* Configure GEM_RCLK_CTRL */
		writel(rclk, &slcr_base->gem1_rclk_ctrl);
	} else {
		/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
		writel(clk, &slcr_base->gem0_clk_ctrl);
		/* Configure GEM_RCLK_CTRL */
		writel(rclk, &slcr_base->gem0_rclk_ctrl);
	}

out:
	zynq_slcr_lock();
}

void zynq_slcr_devcfg_disable(void)
{
	zynq_slcr_unlock();

	/* Disable AXI interface */
	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);

	/* Set Level Shifters DT618760 */
	writel(0xA, &slcr_base->lvl_shftr_en);

	zynq_slcr_lock();
}

void zynq_slcr_devcfg_enable(void)
{
	zynq_slcr_unlock();

	/* Set Level Shifters DT618760 */
	writel(0xF, &slcr_base->lvl_shftr_en);

	/* Disable AXI interface */
	writel(0x0, &slcr_base->fpga_rst_ctrl);

	zynq_slcr_lock();
}

u32 zynq_slcr_get_idcode(void)
{
	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
							SLCR_IDCODE_SHIFT;
}
Commit	Line	Data
59c651f4 MS	1	/*
	2	* Copyright (c) 2013 Xilinx Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
59c651f4 MS	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <malloc.h>
	10	#include <asm/arch/hardware.h>
	11
	12	#define SLCR_LOCK_MAGIC 0x767B
	13	#define SLCR_UNLOCK_MAGIC 0xDF0D
	14
d5dae85f MS	15	#define SLCR_IDCODE_MASK 0x1F000
	16	#define SLCR_IDCODE_SHIFT 12
	17
59c651f4 MS	18	static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
	19
	20	void zynq_slcr_lock(void)
	21	{
	22	if (!slcr_lock)
	23	writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
	24	}
	25
	26	void zynq_slcr_unlock(void)
	27	{
	28	if (slcr_lock)
	29	writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
	30	}
	31
	32	/* Reset the entire system */
	33	void zynq_slcr_cpu_reset(void)
	34	{
	35	/*
	36	* Unlock the SLCR then reset the system.
	37	* Note that this seems to require raw i/o
	38	* functions or there's a lockup?
	39	*/
	40	zynq_slcr_unlock();
	41
	42	/*
	43	* Clear 0x0F000000 bits of reboot status register to workaround
	44	* the FSBL not loading the bitstream after soft-reboot
	45	* This is a temporary solution until we know more.
	46	*/
	47	clrbits_le32(&slcr_base->reboot_status, 0xF000000);
	48
	49	writel(1, &slcr_base->pss_rst_ctrl);
	50	}
80243528 MS	51
	52	/* Setup clk for network */
	53	void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
	54	{
	55	zynq_slcr_unlock();
	56
	57	if (gem_id > 1) {
	58	printf("Non existing GEM id %d\n", gem_id);
	59	goto out;
	60	}
	61
	62	if (gem_id) {
	63	/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
	64	writel(clk, &slcr_base->gem1_clk_ctrl);
	65	/* Configure GEM_RCLK_CTRL */
	66	writel(rclk, &slcr_base->gem1_rclk_ctrl);
	67	} else {
	68	/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
	69	writel(clk, &slcr_base->gem0_clk_ctrl);
	70	/* Configure GEM_RCLK_CTRL */
	71	writel(rclk, &slcr_base->gem0_rclk_ctrl);
	72	}
	73
	74	out:
	75	zynq_slcr_lock();
	76	}
d5dae85f MS	77
	78	void zynq_slcr_devcfg_disable(void)
	79	{
	80	zynq_slcr_unlock();
	81
	82	/* Disable AXI interface */
	83	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
	84
	85	/* Set Level Shifters DT618760 */
	86	writel(0xA, &slcr_base->lvl_shftr_en);
	87
	88	zynq_slcr_lock();
	89	}
	90
	91	void zynq_slcr_devcfg_enable(void)
	92	{
	93	zynq_slcr_unlock();
	94
	95	/* Set Level Shifters DT618760 */
	96	writel(0xF, &slcr_base->lvl_shftr_en);
	97
	98	/* Disable AXI interface */
	99	writel(0x0, &slcr_base->fpga_rst_ctrl);
	100
	101	zynq_slcr_lock();
	102	}
	103
	104	u32 zynq_slcr_get_idcode(void)
	105	{
	106	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
	107	SLCR_IDCODE_SHIFT;
	108	}