[people/ms/u-boot.git] / arch / arm / cpu / armv7 / zynq / slcr.c

/*
 * Copyright (c) 2013 Xilinx Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clk.h>

#define SLCR_LOCK_MAGIC		0x767B
#define SLCR_UNLOCK_MAGIC	0xDF0D

#define SLCR_IDCODE_MASK	0x1F000
#define SLCR_IDCODE_SHIFT	12

static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */

void zynq_slcr_lock(void)
{
	if (!slcr_lock) {
		writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
		slcr_lock = 1;
	}
}

void zynq_slcr_unlock(void)
{
	if (slcr_lock) {
		writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
		slcr_lock = 0;
	}
}

/* Reset the entire system */
void zynq_slcr_cpu_reset(void)
{
	/*
	 * Unlock the SLCR then reset the system.
	 * Note that this seems to require raw i/o
	 * functions or there's a lockup?
	 */
	zynq_slcr_unlock();

	/*
	 * Clear 0x0F000000 bits of reboot status register to workaround
	 * the FSBL not loading the bitstream after soft-reboot
	 * This is a temporary solution until we know more.
	 */
	clrbits_le32(&slcr_base->reboot_status, 0xF000000);

	writel(1, &slcr_base->pss_rst_ctrl);
}

/* Setup clk for network */
void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
	int ret;

	zynq_slcr_unlock();

	if (gem_id > 1) {
		printf("Non existing GEM id %d\n", gem_id);
		goto out;
	}

	ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
	if (ret)
		goto out;

	if (gem_id) {
		/* Configure GEM_RCLK_CTRL */
		writel(1, &slcr_base->gem1_rclk_ctrl);
	} else {
		/* Configure GEM_RCLK_CTRL */
		writel(1, &slcr_base->gem0_rclk_ctrl);
	}
	udelay(100000);
out:
	zynq_slcr_lock();
}

void zynq_slcr_devcfg_disable(void)
{
	zynq_slcr_unlock();

	/* Disable AXI interface by asserting FPGA resets */
	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);

	/* Set Level Shifters DT618760 */
	writel(0xA, &slcr_base->lvl_shftr_en);

	zynq_slcr_lock();
}

void zynq_slcr_devcfg_enable(void)
{
	zynq_slcr_unlock();

	/* Set Level Shifters DT618760 */
	writel(0xF, &slcr_base->lvl_shftr_en);

	/* Enable AXI interface by de-asserting FPGA resets */
	writel(0x0, &slcr_base->fpga_rst_ctrl);

	zynq_slcr_lock();
}

u32 zynq_slcr_get_boot_mode(void)
{
	/* Get the bootmode register value */
	return readl(&slcr_base->boot_mode);
}

u32 zynq_slcr_get_idcode(void)
{
	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
							SLCR_IDCODE_SHIFT;
}
Commit	Line	Data
59c651f4 MS	1	/*
	2	* Copyright (c) 2013 Xilinx Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
59c651f4 MS	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <malloc.h>
	10	#include <asm/arch/hardware.h>
3b5b599f	11	#include <asm/arch/sys_proto.h>
97598fcf	12	#include <asm/arch/clk.h>
59c651f4 MS	13
	14	#define SLCR_LOCK_MAGIC 0x767B
	15	#define SLCR_UNLOCK_MAGIC 0xDF0D
	16
d5dae85f MS	17	#define SLCR_IDCODE_MASK 0x1F000
	18	#define SLCR_IDCODE_SHIFT 12
	19
59c651f4 MS	20	static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
	21
	22	void zynq_slcr_lock(void)
	23	{
2da7a745	24	if (!slcr_lock) {
59c651f4	25	writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
2da7a745 MS	26	slcr_lock = 1;
2da7a745 MS	27	}
59c651f4 MS	28	}
	29
	30	void zynq_slcr_unlock(void)
	31	{
2da7a745	32	if (slcr_lock) {
59c651f4	33	writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
2da7a745 MS	34	slcr_lock = 0;
2da7a745 MS	35	}
59c651f4 MS	36	}
	37
	38	/* Reset the entire system */
	39	void zynq_slcr_cpu_reset(void)
	40	{
	41	/*
	42	* Unlock the SLCR then reset the system.
	43	* Note that this seems to require raw i/o
	44	* functions or there's a lockup?
	45	*/
	46	zynq_slcr_unlock();
	47
	48	/*
	49	* Clear 0x0F000000 bits of reboot status register to workaround
	50	* the FSBL not loading the bitstream after soft-reboot
	51	* This is a temporary solution until we know more.
	52	*/
	53	clrbits_le32(&slcr_base->reboot_status, 0xF000000);
	54
	55	writel(1, &slcr_base->pss_rst_ctrl);
	56	}
80243528 MS	57
80243528 MS	58	/* Setup clk for network */
97598fcf	59	void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
80243528	60	{
97598fcf SB	61	int ret;
97598fcf SB	62
80243528 MS	63	zynq_slcr_unlock();
	64
	65	if (gem_id > 1) {
	66	printf("Non existing GEM id %d\n", gem_id);
	67	goto out;
	68	}
	69
97598fcf SB	70	ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
	71	if (ret)
	72	goto out;
	73
80243528	74	if (gem_id) {
80243528	75	/* Configure GEM_RCLK_CTRL */
1cd46ed2	76	writel(1, &slcr_base->gem1_rclk_ctrl);
80243528	77	} else {
80243528	78	/* Configure GEM_RCLK_CTRL */
1cd46ed2	79	writel(1, &slcr_base->gem0_rclk_ctrl);
80243528	80	}
39523bef	81	udelay(100000);
80243528 MS	82	out:
	83	zynq_slcr_lock();
	84	}
d5dae85f MS	85
	86	void zynq_slcr_devcfg_disable(void)
	87	{
	88	zynq_slcr_unlock();
	89
6e04769c	90	/* Disable AXI interface by asserting FPGA resets */
d5dae85f MS	91	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
	92
	93	/* Set Level Shifters DT618760 */
	94	writel(0xA, &slcr_base->lvl_shftr_en);
	95
	96	zynq_slcr_lock();
	97	}
	98
	99	void zynq_slcr_devcfg_enable(void)
	100	{
	101	zynq_slcr_unlock();
	102
	103	/* Set Level Shifters DT618760 */
	104	writel(0xF, &slcr_base->lvl_shftr_en);
	105
6e04769c	106	/* Enable AXI interface by de-asserting FPGA resets */
d5dae85f MS	107	writel(0x0, &slcr_base->fpga_rst_ctrl);
	108
	109	zynq_slcr_lock();
	110	}
	111
b3de9249 JT	112	u32 zynq_slcr_get_boot_mode(void)
	113	{
	114	/* Get the bootmode register value */
	115	return readl(&slcr_base->boot_mode);
	116	}
	117
d5dae85f MS	118	u32 zynq_slcr_get_idcode(void)
	119	{
	120	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
	121	SLCR_IDCODE_SHIFT;
	122	}