]>
Commit | Line | Data |
---|---|---|
0ae76531 DF |
1 | /* |
2 | * (C) Copyright 2013 | |
3 | * David Feng <fenghua@phytium.com.cn> | |
4 | * | |
5e2ec773 AG |
5 | * (C) Copyright 2016 |
6 | * Alexander Graf <agraf@suse.de> | |
7 | * | |
0ae76531 DF |
8 | * SPDX-License-Identifier: GPL-2.0+ |
9 | */ | |
10 | ||
11 | #include <common.h> | |
12 | #include <asm/system.h> | |
13 | #include <asm/armv8/mmu.h> | |
14 | ||
15 | DECLARE_GLOBAL_DATA_PTR; | |
16 | ||
17 | #ifndef CONFIG_SYS_DCACHE_OFF | |
94f7ff36 | 18 | |
5e2ec773 AG |
19 | /* |
20 | * With 4k page granule, a virtual address is split into 4 lookup parts | |
21 | * spanning 9 bits each: | |
22 | * | |
23 | * _______________________________________________ | |
24 | * | | | | | | | | |
25 | * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off | | |
26 | * |_______|_______|_______|_______|_______|_______| | |
27 | * 63-48 47-39 38-30 29-21 20-12 11-00 | |
28 | * | |
29 | * mask page size | |
30 | * | |
31 | * Lv0: FF8000000000 -- | |
32 | * Lv1: 7FC0000000 1G | |
33 | * Lv2: 3FE00000 2M | |
34 | * Lv3: 1FF000 4K | |
35 | * off: FFF | |
36 | */ | |
94f7ff36 | 37 | |
252cdb46 | 38 | u64 get_tcr(int el, u64 *pips, u64 *pva_bits) |
0691484a AG |
39 | { |
40 | u64 max_addr = 0; | |
41 | u64 ips, va_bits; | |
42 | u64 tcr; | |
43 | int i; | |
44 | ||
45 | /* Find the largest address we need to support */ | |
d473f0c6 | 46 | for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) |
0691484a AG |
47 | max_addr = max(max_addr, mem_map[i].base + mem_map[i].size); |
48 | ||
49 | /* Calculate the maximum physical (and thus virtual) address */ | |
50 | if (max_addr > (1ULL << 44)) { | |
51 | ips = 5; | |
52 | va_bits = 48; | |
53 | } else if (max_addr > (1ULL << 42)) { | |
54 | ips = 4; | |
55 | va_bits = 44; | |
56 | } else if (max_addr > (1ULL << 40)) { | |
57 | ips = 3; | |
58 | va_bits = 42; | |
59 | } else if (max_addr > (1ULL << 36)) { | |
60 | ips = 2; | |
61 | va_bits = 40; | |
62 | } else if (max_addr > (1ULL << 32)) { | |
63 | ips = 1; | |
64 | va_bits = 36; | |
65 | } else { | |
66 | ips = 0; | |
67 | va_bits = 32; | |
68 | } | |
69 | ||
70 | if (el == 1) { | |
9bb367a5 | 71 | tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; |
0691484a AG |
72 | } else if (el == 2) { |
73 | tcr = TCR_EL2_RSVD | (ips << 16); | |
74 | } else { | |
75 | tcr = TCR_EL3_RSVD | (ips << 16); | |
76 | } | |
77 | ||
78 | /* PTWs cacheable, inner/outer WBWA and inner shareable */ | |
5e2ec773 AG |
79 | tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA; |
80 | tcr |= TCR_T0SZ(va_bits); | |
0691484a AG |
81 | |
82 | if (pips) | |
83 | *pips = ips; | |
84 | if (pva_bits) | |
85 | *pva_bits = va_bits; | |
86 | ||
87 | return tcr; | |
88 | } | |
89 | ||
5e2ec773 AG |
90 | #define MAX_PTE_ENTRIES 512 |
91 | ||
92 | static int pte_type(u64 *pte) | |
93 | { | |
94 | return *pte & PTE_TYPE_MASK; | |
95 | } | |
96 | ||
97 | /* Returns the LSB number for a PTE on level <level> */ | |
98 | static int level2shift(int level) | |
99 | { | |
100 | /* Page is 12 bits wide, every level translates 9 bits */ | |
101 | return (12 + 9 * (3 - level)); | |
102 | } | |
103 | ||
104 | static u64 *find_pte(u64 addr, int level) | |
94f7ff36 | 105 | { |
5e2ec773 AG |
106 | int start_level = 0; |
107 | u64 *pte; | |
108 | u64 idx; | |
109 | u64 va_bits; | |
110 | int i; | |
111 | ||
112 | debug("addr=%llx level=%d\n", addr, level); | |
113 | ||
114 | get_tcr(0, NULL, &va_bits); | |
115 | if (va_bits < 39) | |
116 | start_level = 1; | |
117 | ||
118 | if (level < start_level) | |
119 | return NULL; | |
120 | ||
121 | /* Walk through all page table levels to find our PTE */ | |
122 | pte = (u64*)gd->arch.tlb_addr; | |
123 | for (i = start_level; i < 4; i++) { | |
124 | idx = (addr >> level2shift(i)) & 0x1FF; | |
125 | pte += idx; | |
126 | debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte); | |
127 | ||
128 | /* Found it */ | |
129 | if (i == level) | |
130 | return pte; | |
131 | /* PTE is no table (either invalid or block), can't traverse */ | |
132 | if (pte_type(pte) != PTE_TYPE_TABLE) | |
133 | return NULL; | |
134 | /* Off to the next level */ | |
135 | pte = (u64*)(*pte & 0x0000fffffffff000ULL); | |
136 | } | |
137 | ||
138 | /* Should never reach here */ | |
139 | return NULL; | |
140 | } | |
141 | ||
142 | /* Returns and creates a new full table (512 entries) */ | |
143 | static u64 *create_table(void) | |
144 | { | |
145 | u64 *new_table = (u64*)gd->arch.tlb_fillptr; | |
146 | u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64); | |
147 | ||
148 | /* Allocate MAX_PTE_ENTRIES pte entries */ | |
149 | gd->arch.tlb_fillptr += pt_len; | |
150 | ||
151 | if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size) | |
152 | panic("Insufficient RAM for page table: 0x%lx > 0x%lx. " | |
153 | "Please increase the size in get_page_table_size()", | |
154 | gd->arch.tlb_fillptr - gd->arch.tlb_addr, | |
155 | gd->arch.tlb_size); | |
156 | ||
157 | /* Mark all entries as invalid */ | |
158 | memset(new_table, 0, pt_len); | |
159 | ||
160 | return new_table; | |
161 | } | |
162 | ||
163 | static void set_pte_table(u64 *pte, u64 *table) | |
164 | { | |
165 | /* Point *pte to the new table */ | |
166 | debug("Setting %p to addr=%p\n", pte, table); | |
167 | *pte = PTE_TYPE_TABLE | (ulong)table; | |
168 | } | |
169 | ||
f733d466 YS |
170 | /* Splits a block PTE into table with subpages spanning the old block */ |
171 | static void split_block(u64 *pte, int level) | |
172 | { | |
173 | u64 old_pte = *pte; | |
174 | u64 *new_table; | |
175 | u64 i = 0; | |
176 | /* level describes the parent level, we need the child ones */ | |
177 | int levelshift = level2shift(level + 1); | |
178 | ||
179 | if (pte_type(pte) != PTE_TYPE_BLOCK) | |
180 | panic("PTE %p (%llx) is not a block. Some driver code wants to " | |
181 | "modify dcache settings for an range not covered in " | |
182 | "mem_map.", pte, old_pte); | |
183 | ||
184 | new_table = create_table(); | |
185 | debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table); | |
186 | ||
187 | for (i = 0; i < MAX_PTE_ENTRIES; i++) { | |
188 | new_table[i] = old_pte | (i << levelshift); | |
189 | ||
190 | /* Level 3 block PTEs have the table type */ | |
191 | if ((level + 1) == 3) | |
192 | new_table[i] |= PTE_TYPE_TABLE; | |
193 | ||
194 | debug("Setting new_table[%lld] = %llx\n", i, new_table[i]); | |
195 | } | |
196 | ||
197 | /* Set the new table into effect */ | |
198 | set_pte_table(pte, new_table); | |
199 | } | |
200 | ||
5e2ec773 AG |
201 | /* Add one mm_region map entry to the page tables */ |
202 | static void add_map(struct mm_region *map) | |
203 | { | |
204 | u64 *pte; | |
205 | u64 addr = map->base; | |
206 | u64 size = map->size; | |
207 | u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF; | |
208 | u64 blocksize; | |
209 | int level; | |
210 | u64 *new_table; | |
211 | ||
212 | while (size) { | |
213 | pte = find_pte(addr, 0); | |
214 | if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) { | |
215 | debug("Creating table for addr 0x%llx\n", addr); | |
216 | new_table = create_table(); | |
217 | set_pte_table(pte, new_table); | |
218 | } | |
219 | ||
220 | for (level = 1; level < 4; level++) { | |
221 | pte = find_pte(addr, level); | |
f733d466 YS |
222 | if (!pte) |
223 | panic("pte not found\n"); | |
5e2ec773 AG |
224 | blocksize = 1ULL << level2shift(level); |
225 | debug("Checking if pte fits for addr=%llx size=%llx " | |
226 | "blocksize=%llx\n", addr, size, blocksize); | |
227 | if (size >= blocksize && !(addr & (blocksize - 1))) { | |
228 | /* Page fits, create block PTE */ | |
229 | debug("Setting PTE %p to block addr=%llx\n", | |
230 | pte, addr); | |
231 | *pte = addr | attrs; | |
232 | addr += blocksize; | |
233 | size -= blocksize; | |
234 | break; | |
f733d466 | 235 | } else if (pte_type(pte) == PTE_TYPE_FAULT) { |
5e2ec773 AG |
236 | /* Page doesn't fit, create subpages */ |
237 | debug("Creating subtable for addr 0x%llx " | |
238 | "blksize=%llx\n", addr, blocksize); | |
239 | new_table = create_table(); | |
240 | set_pte_table(pte, new_table); | |
f733d466 YS |
241 | } else if (pte_type(pte) == PTE_TYPE_BLOCK) { |
242 | debug("Split block into subtable for addr 0x%llx blksize=0x%llx\n", | |
243 | addr, blocksize); | |
244 | split_block(pte, level); | |
5e2ec773 AG |
245 | } |
246 | } | |
247 | } | |
248 | } | |
249 | ||
5e2ec773 AG |
250 | enum pte_type { |
251 | PTE_INVAL, | |
252 | PTE_BLOCK, | |
253 | PTE_LEVEL, | |
254 | }; | |
255 | ||
256 | /* | |
257 | * This is a recursively called function to count the number of | |
258 | * page tables we need to cover a particular PTE range. If you | |
259 | * call this with level = -1 you basically get the full 48 bit | |
260 | * coverage. | |
261 | */ | |
262 | static int count_required_pts(u64 addr, int level, u64 maxaddr) | |
263 | { | |
264 | int levelshift = level2shift(level); | |
265 | u64 levelsize = 1ULL << levelshift; | |
266 | u64 levelmask = levelsize - 1; | |
267 | u64 levelend = addr + levelsize; | |
268 | int r = 0; | |
269 | int i; | |
270 | enum pte_type pte_type = PTE_INVAL; | |
271 | ||
d473f0c6 | 272 | for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) { |
5e2ec773 AG |
273 | struct mm_region *map = &mem_map[i]; |
274 | u64 start = map->base; | |
275 | u64 end = start + map->size; | |
276 | ||
277 | /* Check if the PTE would overlap with the map */ | |
278 | if (max(addr, start) <= min(levelend, end)) { | |
279 | start = max(addr, start); | |
280 | end = min(levelend, end); | |
281 | ||
282 | /* We need a sub-pt for this level */ | |
283 | if ((start & levelmask) || (end & levelmask)) { | |
284 | pte_type = PTE_LEVEL; | |
285 | break; | |
94f7ff36 ST |
286 | } |
287 | ||
5e2ec773 AG |
288 | /* Lv0 can not do block PTEs, so do levels here too */ |
289 | if (level <= 0) { | |
290 | pte_type = PTE_LEVEL; | |
291 | break; | |
292 | } | |
293 | ||
294 | /* PTE is active, but fits into a block */ | |
295 | pte_type = PTE_BLOCK; | |
94f7ff36 ST |
296 | } |
297 | } | |
5e2ec773 AG |
298 | |
299 | /* | |
300 | * Block PTEs at this level are already covered by the parent page | |
301 | * table, so we only need to count sub page tables. | |
302 | */ | |
303 | if (pte_type == PTE_LEVEL) { | |
304 | int sublevel = level + 1; | |
305 | u64 sublevelsize = 1ULL << level2shift(sublevel); | |
306 | ||
307 | /* Account for the new sub page table ... */ | |
308 | r = 1; | |
309 | ||
310 | /* ... and for all child page tables that one might have */ | |
311 | for (i = 0; i < MAX_PTE_ENTRIES; i++) { | |
312 | r += count_required_pts(addr, sublevel, maxaddr); | |
313 | addr += sublevelsize; | |
314 | ||
315 | if (addr >= maxaddr) { | |
316 | /* | |
317 | * We reached the end of address space, no need | |
318 | * to look any further. | |
319 | */ | |
320 | break; | |
321 | } | |
322 | } | |
323 | } | |
324 | ||
325 | return r; | |
326 | } | |
327 | ||
328 | /* Returns the estimated required size of all page tables */ | |
c05016ab | 329 | __weak u64 get_page_table_size(void) |
5e2ec773 AG |
330 | { |
331 | u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); | |
332 | u64 size = 0; | |
333 | u64 va_bits; | |
334 | int start_level = 0; | |
335 | ||
336 | get_tcr(0, NULL, &va_bits); | |
337 | if (va_bits < 39) | |
338 | start_level = 1; | |
339 | ||
340 | /* Account for all page tables we would need to cover our memory map */ | |
341 | size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits); | |
342 | ||
343 | /* | |
344 | * We need to duplicate our page table once to have an emergency pt to | |
345 | * resort to when splitting page tables later on | |
346 | */ | |
347 | size *= 2; | |
348 | ||
349 | /* | |
350 | * We may need to split page tables later on if dcache settings change, | |
351 | * so reserve up to 4 (random pick) page tables for that. | |
352 | */ | |
353 | size += one_pt * 4; | |
354 | ||
355 | return size; | |
356 | } | |
357 | ||
252cdb46 | 358 | void setup_pgtables(void) |
5e2ec773 AG |
359 | { |
360 | int i; | |
361 | ||
252cdb46 YS |
362 | if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr) |
363 | panic("Page table pointer not setup."); | |
364 | ||
5e2ec773 AG |
365 | /* |
366 | * Allocate the first level we're on with invalidate entries. | |
367 | * If the starting level is 0 (va_bits >= 39), then this is our | |
368 | * Lv0 page table, otherwise it's the entry Lv1 page table. | |
369 | */ | |
370 | create_table(); | |
371 | ||
372 | /* Now add all MMU table entries one after another to the table */ | |
d473f0c6 | 373 | for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) |
5e2ec773 | 374 | add_map(&mem_map[i]); |
5e2ec773 AG |
375 | } |
376 | ||
377 | static void setup_all_pgtables(void) | |
378 | { | |
379 | u64 tlb_addr = gd->arch.tlb_addr; | |
380 | ||
381 | /* Reset the fill ptr */ | |
382 | gd->arch.tlb_fillptr = tlb_addr; | |
383 | ||
384 | /* Create normal system page tables */ | |
385 | setup_pgtables(); | |
386 | ||
387 | /* Create emergency page tables */ | |
388 | gd->arch.tlb_addr = gd->arch.tlb_fillptr; | |
389 | setup_pgtables(); | |
390 | gd->arch.tlb_emerg = gd->arch.tlb_addr; | |
391 | gd->arch.tlb_addr = tlb_addr; | |
94f7ff36 ST |
392 | } |
393 | ||
0ae76531 | 394 | /* to activate the MMU we need to set up virtual memory */ |
3c6af3ba | 395 | __weak void mmu_setup(void) |
0ae76531 | 396 | { |
8b19dff5 | 397 | int el; |
0ae76531 | 398 | |
5e2ec773 AG |
399 | /* Set up page tables only once */ |
400 | if (!gd->arch.tlb_fillptr) | |
401 | setup_all_pgtables(); | |
0691484a AG |
402 | |
403 | el = current_el(); | |
404 | set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), | |
405 | MEMORY_ATTRIBUTES); | |
0691484a | 406 | |
0ae76531 DF |
407 | /* enable the mmu */ |
408 | set_sctlr(get_sctlr() | CR_M); | |
409 | } | |
410 | ||
411 | /* | |
412 | * Performs a invalidation of the entire data cache at all levels | |
413 | */ | |
414 | void invalidate_dcache_all(void) | |
415 | { | |
1e6ad55c | 416 | __asm_invalidate_dcache_all(); |
0ae76531 DF |
417 | } |
418 | ||
419 | /* | |
dcd468b8 YS |
420 | * Performs a clean & invalidation of the entire data cache at all levels. |
421 | * This function needs to be inline to avoid using stack. | |
422 | * __asm_flush_l3_cache return status of timeout | |
0ae76531 | 423 | */ |
dcd468b8 | 424 | inline void flush_dcache_all(void) |
0ae76531 | 425 | { |
dcd468b8 YS |
426 | int ret; |
427 | ||
0ae76531 | 428 | __asm_flush_dcache_all(); |
dcd468b8 YS |
429 | ret = __asm_flush_l3_cache(); |
430 | if (ret) | |
431 | debug("flushing dcache returns 0x%x\n", ret); | |
432 | else | |
433 | debug("flushing dcache successfully.\n"); | |
0ae76531 DF |
434 | } |
435 | ||
436 | /* | |
437 | * Invalidates range in all levels of D-cache/unified cache | |
438 | */ | |
439 | void invalidate_dcache_range(unsigned long start, unsigned long stop) | |
440 | { | |
441 | __asm_flush_dcache_range(start, stop); | |
442 | } | |
443 | ||
444 | /* | |
445 | * Flush range(clean & invalidate) from all levels of D-cache/unified cache | |
446 | */ | |
447 | void flush_dcache_range(unsigned long start, unsigned long stop) | |
448 | { | |
449 | __asm_flush_dcache_range(start, stop); | |
450 | } | |
451 | ||
452 | void dcache_enable(void) | |
453 | { | |
454 | /* The data cache is not active unless the mmu is enabled */ | |
455 | if (!(get_sctlr() & CR_M)) { | |
456 | invalidate_dcache_all(); | |
457 | __asm_invalidate_tlb_all(); | |
458 | mmu_setup(); | |
459 | } | |
460 | ||
461 | set_sctlr(get_sctlr() | CR_C); | |
462 | } | |
463 | ||
464 | void dcache_disable(void) | |
465 | { | |
466 | uint32_t sctlr; | |
467 | ||
468 | sctlr = get_sctlr(); | |
469 | ||
470 | /* if cache isn't enabled no need to disable */ | |
471 | if (!(sctlr & CR_C)) | |
472 | return; | |
473 | ||
474 | set_sctlr(sctlr & ~(CR_C|CR_M)); | |
475 | ||
476 | flush_dcache_all(); | |
477 | __asm_invalidate_tlb_all(); | |
478 | } | |
479 | ||
480 | int dcache_status(void) | |
481 | { | |
482 | return (get_sctlr() & CR_C) != 0; | |
483 | } | |
484 | ||
dad17fd5 SDPP |
485 | u64 *__weak arch_get_page_table(void) { |
486 | puts("No page table offset defined\n"); | |
487 | ||
488 | return NULL; | |
489 | } | |
490 | ||
5e2ec773 AG |
491 | static bool is_aligned(u64 addr, u64 size, u64 align) |
492 | { | |
493 | return !(addr & (align - 1)) && !(size & (align - 1)); | |
494 | } | |
495 | ||
496 | static u64 set_one_region(u64 start, u64 size, u64 attrs, int level) | |
497 | { | |
498 | int levelshift = level2shift(level); | |
499 | u64 levelsize = 1ULL << levelshift; | |
500 | u64 *pte = find_pte(start, level); | |
501 | ||
502 | /* Can we can just modify the current level block PTE? */ | |
503 | if (is_aligned(start, size, levelsize)) { | |
504 | *pte &= ~PMD_ATTRINDX_MASK; | |
505 | *pte |= attrs; | |
506 | debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level); | |
507 | ||
508 | return levelsize; | |
509 | } | |
510 | ||
511 | /* Unaligned or doesn't fit, maybe split block into table */ | |
512 | debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte); | |
513 | ||
514 | /* Maybe we need to split the block into a table */ | |
515 | if (pte_type(pte) == PTE_TYPE_BLOCK) | |
516 | split_block(pte, level); | |
517 | ||
518 | /* And then double-check it became a table or already is one */ | |
519 | if (pte_type(pte) != PTE_TYPE_TABLE) | |
520 | panic("PTE %p (%llx) for addr=%llx should be a table", | |
521 | pte, *pte, start); | |
522 | ||
523 | /* Roll on to the next page table level */ | |
524 | return 0; | |
525 | } | |
526 | ||
527 | void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, | |
528 | enum dcache_option option) | |
529 | { | |
530 | u64 attrs = PMD_ATTRINDX(option); | |
531 | u64 real_start = start; | |
532 | u64 real_size = size; | |
533 | ||
534 | debug("start=%lx size=%lx\n", (ulong)start, (ulong)size); | |
535 | ||
252cdb46 YS |
536 | if (!gd->arch.tlb_emerg) |
537 | panic("Emergency page table not setup."); | |
538 | ||
5e2ec773 AG |
539 | /* |
540 | * We can not modify page tables that we're currently running on, | |
541 | * so we first need to switch to the "emergency" page tables where | |
542 | * we can safely modify our primary page tables and then switch back | |
543 | */ | |
544 | __asm_switch_ttbr(gd->arch.tlb_emerg); | |
545 | ||
546 | /* | |
547 | * Loop through the address range until we find a page granule that fits | |
548 | * our alignment constraints, then set it to the new cache attributes | |
549 | */ | |
550 | while (size > 0) { | |
551 | int level; | |
552 | u64 r; | |
553 | ||
554 | for (level = 1; level < 4; level++) { | |
555 | r = set_one_region(start, size, attrs, level); | |
556 | if (r) { | |
557 | /* PTE successfully replaced */ | |
558 | size -= r; | |
559 | start += r; | |
560 | break; | |
561 | } | |
562 | } | |
563 | ||
564 | } | |
565 | ||
566 | /* We're done modifying page tables, switch back to our primary ones */ | |
567 | __asm_switch_ttbr(gd->arch.tlb_addr); | |
568 | ||
569 | /* | |
570 | * Make sure there's nothing stale in dcache for a region that might | |
571 | * have caches off now | |
572 | */ | |
573 | flush_dcache_range(real_start, real_start + real_size); | |
574 | } | |
94f7ff36 | 575 | |
0ae76531 DF |
576 | #else /* CONFIG_SYS_DCACHE_OFF */ |
577 | ||
19503c31 AG |
578 | /* |
579 | * For SPL builds, we may want to not have dcache enabled. Any real U-Boot | |
580 | * running however really wants to have dcache and the MMU active. Check that | |
581 | * everything is sane and give the developer a hint if it isn't. | |
582 | */ | |
583 | #ifndef CONFIG_SPL_BUILD | |
584 | #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache. | |
585 | #endif | |
586 | ||
0ae76531 DF |
587 | void invalidate_dcache_all(void) |
588 | { | |
589 | } | |
590 | ||
591 | void flush_dcache_all(void) | |
592 | { | |
593 | } | |
594 | ||
0ae76531 DF |
595 | void dcache_enable(void) |
596 | { | |
597 | } | |
598 | ||
599 | void dcache_disable(void) | |
600 | { | |
601 | } | |
602 | ||
603 | int dcache_status(void) | |
604 | { | |
605 | return 0; | |
606 | } | |
607 | ||
dad17fd5 SDPP |
608 | void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, |
609 | enum dcache_option option) | |
610 | { | |
611 | } | |
612 | ||
0ae76531 DF |
613 | #endif /* CONFIG_SYS_DCACHE_OFF */ |
614 | ||
615 | #ifndef CONFIG_SYS_ICACHE_OFF | |
616 | ||
617 | void icache_enable(void) | |
618 | { | |
1e6ad55c | 619 | __asm_invalidate_icache_all(); |
0ae76531 DF |
620 | set_sctlr(get_sctlr() | CR_I); |
621 | } | |
622 | ||
623 | void icache_disable(void) | |
624 | { | |
625 | set_sctlr(get_sctlr() & ~CR_I); | |
626 | } | |
627 | ||
628 | int icache_status(void) | |
629 | { | |
630 | return (get_sctlr() & CR_I) != 0; | |
631 | } | |
632 | ||
633 | void invalidate_icache_all(void) | |
634 | { | |
635 | __asm_invalidate_icache_all(); | |
636 | } | |
637 | ||
638 | #else /* CONFIG_SYS_ICACHE_OFF */ | |
639 | ||
640 | void icache_enable(void) | |
641 | { | |
642 | } | |
643 | ||
644 | void icache_disable(void) | |
645 | { | |
646 | } | |
647 | ||
648 | int icache_status(void) | |
649 | { | |
650 | return 0; | |
651 | } | |
652 | ||
653 | void invalidate_icache_all(void) | |
654 | { | |
655 | } | |
656 | ||
657 | #endif /* CONFIG_SYS_ICACHE_OFF */ | |
658 | ||
659 | /* | |
660 | * Enable dCache & iCache, whether cache is actually enabled | |
661 | * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF | |
662 | */ | |
2f78eae5 | 663 | void __weak enable_caches(void) |
0ae76531 DF |
664 | { |
665 | icache_enable(); | |
666 | dcache_enable(); | |
667 | } |