]>
Commit | Line | Data |
---|---|---|
9533acf3 | 1 | config ARCH_LS1012A |
4a444176 | 2 | bool |
ee2a5102 | 3 | select ARMV8_SET_SMPEN |
b6c97f4d | 4 | select ARM_ERRATA_855873 if !TFABOOT |
5c08d96f | 5 | select FSL_LAYERSCAPE |
fb2bf8c2 | 6 | select FSL_LSCH2 |
5afdcca0 | 7 | select GICV2 |
a2ac2b96 | 8 | select SKIP_LOWLEVEL_INIT |
30cf7f81 SD |
9 | select SYS_FSL_SRDS_1 |
10 | select SYS_HAS_SERDES | |
24aaa094 | 11 | select SYS_FSL_DDR_BE |
9533acf3 | 12 | select SYS_FSL_MMDC |
2a98944b | 13 | select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE |
819163c4 RW |
14 | select SYS_FSL_ERRATUM_A009798 |
15 | select SYS_FSL_ERRATUM_A008997 | |
16 | select SYS_FSL_ERRATUM_A009007 | |
17 | select SYS_FSL_ERRATUM_A009008 | |
a421192f | 18 | select ARCH_EARLY_INIT_R |
a5d67547 | 19 | select BOARD_EARLY_INIT_F |
942ecc8b | 20 | select SYS_I2C_MXC |
a0affb36 BL |
21 | select SYS_I2C_MXC_I2C1 if !DM_I2C |
22 | select SYS_I2C_MXC_I2C2 if !DM_I2C | |
7e3caa81 | 23 | imply PANIC_HANG |
d6b318de | 24 | imply TIMESTAMP |
0a37cf8f | 25 | |
d4ad111d YT |
26 | config ARCH_LS1028A |
27 | bool | |
28 | select ARMV8_SET_SMPEN | |
f8c5815c | 29 | select FSL_LAYERSCAPE |
d4ad111d | 30 | select FSL_LSCH3 |
5afdcca0 | 31 | select GICV3 |
d4ad111d YT |
32 | select NXP_LSCH3_2 |
33 | select SYS_FSL_HAS_CCI400 | |
34 | select SYS_FSL_SRDS_1 | |
35 | select SYS_HAS_SERDES | |
36 | select SYS_FSL_DDR | |
37 | select SYS_FSL_DDR_LE | |
38 | select SYS_FSL_DDR_VER_50 | |
39 | select SYS_FSL_HAS_DDR3 | |
40 | select SYS_FSL_HAS_DDR4 | |
41 | select SYS_FSL_HAS_SEC | |
42 | select SYS_FSL_SEC_COMPAT_5 | |
43 | select SYS_FSL_SEC_LE | |
44 | select FSL_TZASC_1 | |
f76750d1 | 45 | select FSL_TZPC_BP147 |
d4ad111d YT |
46 | select ARCH_EARLY_INIT_R |
47 | select BOARD_EARLY_INIT_F | |
48 | select SYS_I2C_MXC | |
3458a419 | 49 | select SYS_FSL_ERRATUM_A008997 |
d4ad111d YT |
50 | select SYS_FSL_ERRATUM_A009007 |
51 | select SYS_FSL_ERRATUM_A008514 if !TFABOOT | |
52 | select SYS_FSL_ERRATUM_A009663 if !TFABOOT | |
53 | select SYS_FSL_ERRATUM_A009942 if !TFABOOT | |
b4a59115 | 54 | select SYS_FSL_ERRATUM_A050382 |
bd7b8505 | 55 | select SYS_FSL_ERRATUM_A011334 |
d3b745f7 | 56 | select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND |
0d5b0711 | 57 | select RESV_RAM if GIC_V3_ITS |
d4ad111d YT |
58 | imply PANIC_HANG |
59 | ||
0a37cf8f | 60 | config ARCH_LS1043A |
4a444176 | 61 | bool |
ee2a5102 | 62 | select ARMV8_SET_SMPEN |
b6c97f4d | 63 | select ARM_ERRATA_855873 if !TFABOOT |
98ab831d | 64 | select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI) |
5c08d96f | 65 | select FSL_LAYERSCAPE |
fb2bf8c2 | 66 | select FSL_LSCH2 |
5afdcca0 | 67 | select GICV2 |
a968e9ad | 68 | select HAS_FSL_XHCI_USB if USB_HOST |
a2ac2b96 | 69 | select SKIP_LOWLEVEL_INIT |
30cf7f81 SD |
70 | select SYS_FSL_SRDS_1 |
71 | select SYS_HAS_SERDES | |
d26e34c4 | 72 | select SYS_FSL_DDR |
24aaa094 YS |
73 | select SYS_FSL_DDR_BE |
74 | select SYS_FSL_DDR_VER_50 | |
b6c97f4d | 75 | select SYS_FSL_ERRATUM_A008850 if !TFABOOT |
9d1cd910 | 76 | select SYS_FSL_ERRATUM_A008997 |
15d59b53 | 77 | select SYS_FSL_ERRATUM_A009007 |
2ab1553f | 78 | select SYS_FSL_ERRATUM_A009008 |
b6c97f4d RB |
79 | select SYS_FSL_ERRATUM_A009660 if !TFABOOT |
80 | select SYS_FSL_ERRATUM_A009663 if !TFABOOT | |
2a8a3539 | 81 | select SYS_FSL_ERRATUM_A009798 |
b6c97f4d | 82 | select SYS_FSL_ERRATUM_A009942 if !TFABOOT |
2a98944b | 83 | select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE |
0ea3671d | 84 | select SYS_FSL_ERRATUM_A010539 |
d26e34c4 YS |
85 | select SYS_FSL_HAS_DDR3 |
86 | select SYS_FSL_HAS_DDR4 | |
a421192f | 87 | select ARCH_EARLY_INIT_R |
a5d67547 | 88 | select BOARD_EARLY_INIT_F |
af0e08ca | 89 | select SYS_I2C_MXC |
fefac937 BL |
90 | select SYS_I2C_MXC_I2C1 if !DM_I2C |
91 | select SYS_I2C_MXC_I2C2 if !DM_I2C | |
92 | select SYS_I2C_MXC_I2C3 if !DM_I2C | |
93 | select SYS_I2C_MXC_I2C4 if !DM_I2C | |
6500ec7a | 94 | imply CMD_PCI |
d7d40f61 | 95 | imply ID_EEPROM |
9533acf3 | 96 | |
da28e58a | 97 | config ARCH_LS1046A |
4a444176 | 98 | bool |
ee2a5102 | 99 | select ARMV8_SET_SMPEN |
98ab831d | 100 | select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI) |
5c08d96f | 101 | select FSL_LAYERSCAPE |
fb2bf8c2 | 102 | select FSL_LSCH2 |
5afdcca0 | 103 | select GICV2 |
a968e9ad | 104 | select HAS_FSL_XHCI_USB if USB_HOST |
a2ac2b96 | 105 | select SKIP_LOWLEVEL_INIT |
30cf7f81 SD |
106 | select SYS_FSL_SRDS_1 |
107 | select SYS_HAS_SERDES | |
d26e34c4 | 108 | select SYS_FSL_DDR |
24aaa094 | 109 | select SYS_FSL_DDR_BE |
24aaa094 | 110 | select SYS_FSL_DDR_VER_50 |
b6c97f4d RB |
111 | select SYS_FSL_ERRATUM_A008336 if !TFABOOT |
112 | select SYS_FSL_ERRATUM_A008511 if !TFABOOT | |
113 | select SYS_FSL_ERRATUM_A008850 if !TFABOOT | |
9d1cd910 | 114 | select SYS_FSL_ERRATUM_A008997 |
15d59b53 | 115 | select SYS_FSL_ERRATUM_A009007 |
2ab1553f | 116 | select SYS_FSL_ERRATUM_A009008 |
2a8a3539 | 117 | select SYS_FSL_ERRATUM_A009798 |
ba1b6fb5 | 118 | select SYS_FSL_ERRATUM_A009801 |
b6c97f4d RB |
119 | select SYS_FSL_ERRATUM_A009803 if !TFABOOT |
120 | select SYS_FSL_ERRATUM_A009942 if !TFABOOT | |
121 | select SYS_FSL_ERRATUM_A010165 if !TFABOOT | |
0ea3671d | 122 | select SYS_FSL_ERRATUM_A010539 |
d26e34c4 | 123 | select SYS_FSL_HAS_DDR4 |
f534b8f5 | 124 | select SYS_FSL_SRDS_2 |
a421192f | 125 | select ARCH_EARLY_INIT_R |
a5d67547 | 126 | select BOARD_EARLY_INIT_F |
af0e08ca | 127 | select SYS_I2C_MXC |
bb1165f9 BL |
128 | select SYS_I2C_MXC_I2C1 if !DM_I2C |
129 | select SYS_I2C_MXC_I2C2 if !DM_I2C | |
130 | select SYS_I2C_MXC_I2C3 if !DM_I2C | |
131 | select SYS_I2C_MXC_I2C4 if !DM_I2C | |
d7d40f61 | 132 | imply ID_EEPROM |
fedb428c | 133 | imply SCSI |
9fd95ef0 | 134 | imply SCSI_AHCI |
55dabcc8 | 135 | imply SPL_SYS_I2C_LEGACY |
9533acf3 | 136 | |
6d9b82d0 AK |
137 | config ARCH_LS1088A |
138 | bool | |
139 | select ARMV8_SET_SMPEN | |
143af3c6 | 140 | select ARM_ERRATA_855873 if !TFABOOT |
98ab831d | 141 | select FSL_IFC |
5c08d96f | 142 | select FSL_LAYERSCAPE |
6d9b82d0 | 143 | select FSL_LSCH3 |
5afdcca0 | 144 | select GICV3 |
a2ac2b96 | 145 | select SKIP_LOWLEVEL_INIT |
30cf7f81 SD |
146 | select SYS_FSL_SRDS_1 |
147 | select SYS_HAS_SERDES | |
6d9b82d0 AK |
148 | select SYS_FSL_DDR |
149 | select SYS_FSL_DDR_LE | |
150 | select SYS_FSL_DDR_VER_50 | |
17d066fc AK |
151 | select SYS_FSL_EC1 |
152 | select SYS_FSL_EC2 | |
143af3c6 PG |
153 | select SYS_FSL_ERRATUM_A009803 if !TFABOOT |
154 | select SYS_FSL_ERRATUM_A009942 if !TFABOOT | |
155 | select SYS_FSL_ERRATUM_A010165 if !TFABOOT | |
156 | select SYS_FSL_ERRATUM_A008511 if !TFABOOT | |
157 | select SYS_FSL_ERRATUM_A008850 if !TFABOOT | |
7458c5e6 | 158 | select SYS_FSL_ERRATUM_A009007 |
6d9b82d0 AK |
159 | select SYS_FSL_HAS_CCI400 |
160 | select SYS_FSL_HAS_DDR4 | |
17d066fc | 161 | select SYS_FSL_HAS_RGMII |
6d9b82d0 AK |
162 | select SYS_FSL_HAS_SEC |
163 | select SYS_FSL_SEC_COMPAT_5 | |
164 | select SYS_FSL_SEC_LE | |
165 | select SYS_FSL_SRDS_1 | |
166 | select SYS_FSL_SRDS_2 | |
167 | select FSL_TZASC_1 | |
bbf5b252 RB |
168 | select FSL_TZASC_400 |
169 | select FSL_TZPC_BP147 | |
6d9b82d0 AK |
170 | select ARCH_EARLY_INIT_R |
171 | select BOARD_EARLY_INIT_F | |
942ecc8b | 172 | select SYS_I2C_MXC |
67d3a815 CH |
173 | select SYS_I2C_MXC_I2C1 if !TFABOOT |
174 | select SYS_I2C_MXC_I2C2 if !TFABOOT | |
175 | select SYS_I2C_MXC_I2C3 if !TFABOOT | |
176 | select SYS_I2C_MXC_I2C4 if !TFABOOT | |
0d5b0711 | 177 | select RESV_RAM if GIC_V3_ITS |
d7d40f61 | 178 | imply ID_EEPROM |
f65425fb | 179 | imply SCSI |
55dabcc8 | 180 | imply SPL_SYS_I2C_LEGACY |
7e3caa81 | 181 | imply PANIC_HANG |
6d9b82d0 | 182 | |
4a444176 YS |
183 | config ARCH_LS2080A |
184 | bool | |
ee2a5102 | 185 | select ARMV8_SET_SMPEN |
8dda2e2f TR |
186 | select ARM_ERRATA_826974 |
187 | select ARM_ERRATA_828024 | |
188 | select ARM_ERRATA_829520 | |
189 | select ARM_ERRATA_833471 | |
98ab831d | 190 | select FSL_IFC |
5c08d96f | 191 | select FSL_LAYERSCAPE |
fb2bf8c2 | 192 | select FSL_LSCH3 |
5afdcca0 | 193 | select GICV3 |
a2ac2b96 | 194 | select SKIP_LOWLEVEL_INIT |
30cf7f81 SD |
195 | select SYS_FSL_SRDS_1 |
196 | select SYS_HAS_SERDES | |
d26e34c4 | 197 | select SYS_FSL_DDR |
24aaa094 YS |
198 | select SYS_FSL_DDR_LE |
199 | select SYS_FSL_DDR_VER_50 | |
c055cee1 | 200 | select SYS_FSL_HAS_CCN504 |
f534b8f5 | 201 | select SYS_FSL_HAS_DP_DDR |
2c2e2c9e | 202 | select SYS_FSL_HAS_SEC |
d26e34c4 | 203 | select SYS_FSL_HAS_DDR4 |
2c2e2c9e | 204 | select SYS_FSL_SEC_COMPAT_5 |
90b80386 | 205 | select SYS_FSL_SEC_LE |
f534b8f5 | 206 | select SYS_FSL_SRDS_2 |
85a9a14e A |
207 | select FSL_TZASC_1 |
208 | select FSL_TZASC_2 | |
bbf5b252 RB |
209 | select FSL_TZASC_400 |
210 | select FSL_TZPC_BP147 | |
9570df03 RB |
211 | select SYS_FSL_ERRATUM_A008336 if !TFABOOT |
212 | select SYS_FSL_ERRATUM_A008511 if !TFABOOT | |
213 | select SYS_FSL_ERRATUM_A008514 if !TFABOOT | |
ba1b6fb5 | 214 | select SYS_FSL_ERRATUM_A008585 |
9d1cd910 | 215 | select SYS_FSL_ERRATUM_A008997 |
15d59b53 | 216 | select SYS_FSL_ERRATUM_A009007 |
2ab1553f | 217 | select SYS_FSL_ERRATUM_A009008 |
ba1b6fb5 | 218 | select SYS_FSL_ERRATUM_A009635 |
9570df03 | 219 | select SYS_FSL_ERRATUM_A009663 if !TFABOOT |
2a8a3539 | 220 | select SYS_FSL_ERRATUM_A009798 |
ba1b6fb5 | 221 | select SYS_FSL_ERRATUM_A009801 |
9570df03 RB |
222 | select SYS_FSL_ERRATUM_A009803 if !TFABOOT |
223 | select SYS_FSL_ERRATUM_A009942 if !TFABOOT | |
224 | select SYS_FSL_ERRATUM_A010165 if !TFABOOT | |
dd48f0bf | 225 | select SYS_FSL_ERRATUM_A009203 |
a421192f | 226 | select ARCH_EARLY_INIT_R |
a5d67547 | 227 | select BOARD_EARLY_INIT_F |
942ecc8b | 228 | select SYS_I2C_MXC |
292370df CH |
229 | select SYS_I2C_MXC_I2C1 if !TFABOOT |
230 | select SYS_I2C_MXC_I2C2 if !TFABOOT | |
231 | select SYS_I2C_MXC_I2C3 if !TFABOOT | |
232 | select SYS_I2C_MXC_I2C4 if !TFABOOT | |
0d5b0711 | 233 | select RESV_RAM if GIC_V3_ITS |
7325f6cf | 234 | imply DISTRO_DEFAULTS |
d7d40f61 | 235 | imply ID_EEPROM |
7e3caa81 | 236 | imply PANIC_HANG |
55dabcc8 | 237 | imply SPL_SYS_I2C_LEGACY |
fb2bf8c2 | 238 | |
3a187cff MA |
239 | config ARCH_LX2162A |
240 | bool | |
241 | select ARMV8_SET_SMPEN | |
33b02e93 TR |
242 | select FSL_DDR_BIST |
243 | select FSL_DDR_INTERACTIVE | |
75c995a1 | 244 | select FSL_LAYERSCAPE |
3a187cff | 245 | select FSL_LSCH3 |
f76750d1 | 246 | select FSL_TZPC_BP147 |
5afdcca0 | 247 | select GICV3 |
3a187cff MA |
248 | select NXP_LSCH3_2 |
249 | select SYS_HAS_SERDES | |
250 | select SYS_FSL_SRDS_1 | |
251 | select SYS_FSL_SRDS_2 | |
252 | select SYS_FSL_DDR | |
253 | select SYS_FSL_DDR_LE | |
254 | select SYS_FSL_DDR_VER_50 | |
255 | select SYS_FSL_EC1 | |
256 | select SYS_FSL_EC2 | |
390c73b4 | 257 | select SYS_FSL_ERRATUM_A050204 |
addec351 YL |
258 | select SYS_FSL_ERRATUM_A011334 |
259 | select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND | |
3a187cff MA |
260 | select SYS_FSL_HAS_RGMII |
261 | select SYS_FSL_HAS_SEC | |
262 | select SYS_FSL_HAS_CCN508 | |
263 | select SYS_FSL_HAS_DDR4 | |
264 | select SYS_FSL_SEC_COMPAT_5 | |
265 | select SYS_FSL_SEC_LE | |
7856cd5a | 266 | select SYS_PCI_64BIT if PCI |
3a187cff MA |
267 | select ARCH_EARLY_INIT_R |
268 | select BOARD_EARLY_INIT_F | |
269 | select SYS_I2C_MXC | |
270 | select RESV_RAM if GIC_V3_ITS | |
271 | imply DISTRO_DEFAULTS | |
272 | imply PANIC_HANG | |
273 | imply SCSI | |
274 | imply SCSI_AHCI | |
55dabcc8 | 275 | imply SPL_SYS_I2C_LEGACY |
3a187cff | 276 | |
4909b89e PJ |
277 | config ARCH_LX2160A |
278 | bool | |
279 | select ARMV8_SET_SMPEN | |
33b02e93 TR |
280 | select FSL_DDR_BIST |
281 | select FSL_DDR_INTERACTIVE | |
75c995a1 | 282 | select FSL_LAYERSCAPE |
4909b89e | 283 | select FSL_LSCH3 |
f76750d1 | 284 | select FSL_TZPC_BP147 |
5afdcca0 | 285 | select GICV3 |
a968e9ad | 286 | select HAS_FSL_XHCI_USB if USB_HOST |
4909b89e PJ |
287 | select NXP_LSCH3_2 |
288 | select SYS_HAS_SERDES | |
289 | select SYS_FSL_SRDS_1 | |
290 | select SYS_FSL_SRDS_2 | |
291 | select SYS_NXP_SRDS_3 | |
292 | select SYS_FSL_DDR | |
293 | select SYS_FSL_DDR_LE | |
294 | select SYS_FSL_DDR_VER_50 | |
295 | select SYS_FSL_EC1 | |
296 | select SYS_FSL_EC2 | |
390c73b4 | 297 | select SYS_FSL_ERRATUM_A050204 |
addec351 YL |
298 | select SYS_FSL_ERRATUM_A011334 |
299 | select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND | |
4909b89e PJ |
300 | select SYS_FSL_HAS_RGMII |
301 | select SYS_FSL_HAS_SEC | |
302 | select SYS_FSL_HAS_CCN508 | |
303 | select SYS_FSL_HAS_DDR4 | |
304 | select SYS_FSL_SEC_COMPAT_5 | |
305 | select SYS_FSL_SEC_LE | |
7856cd5a | 306 | select SYS_PCI_64BIT if PCI |
4909b89e PJ |
307 | select ARCH_EARLY_INIT_R |
308 | select BOARD_EARLY_INIT_F | |
309 | select SYS_I2C_MXC | |
0d5b0711 | 310 | select RESV_RAM if GIC_V3_ITS |
4909b89e | 311 | imply DISTRO_DEFAULTS |
d7d40f61 | 312 | imply ID_EEPROM |
4909b89e PJ |
313 | imply PANIC_HANG |
314 | imply SCSI | |
315 | imply SCSI_AHCI | |
55dabcc8 | 316 | imply SPL_SYS_I2C_LEGACY |
4909b89e | 317 | |
fb2bf8c2 YS |
318 | config FSL_LSCH2 |
319 | bool | |
a2ac2b96 | 320 | select SKIP_LOWLEVEL_INIT |
63b2316c | 321 | select SYS_FSL_HAS_CCI400 |
2c2e2c9e YS |
322 | select SYS_FSL_HAS_SEC |
323 | select SYS_FSL_SEC_COMPAT_5 | |
90b80386 | 324 | select SYS_FSL_SEC_BE |
fb2bf8c2 YS |
325 | |
326 | config FSL_LSCH3 | |
0d9d557d | 327 | select ARCH_MISC_INIT |
fb2bf8c2 YS |
328 | bool |
329 | ||
d6fdec21 PJ |
330 | config NXP_LSCH3_2 |
331 | bool | |
332 | ||
fb2bf8c2 YS |
333 | menu "Layerscape architecture" |
334 | depends on FSL_LSCH2 || FSL_LSCH3 | |
4a444176 | 335 | |
5c08d96f RB |
336 | config FSL_LAYERSCAPE |
337 | bool | |
338 | ||
fa18ed76 WS |
339 | config HAS_FEATURE_GIC64K_ALIGN |
340 | bool | |
341 | default y if ARCH_LS1043A | |
342 | ||
2ca84bf7 WS |
343 | config HAS_FEATURE_ENHANCED_MSI |
344 | bool | |
345 | default y if ARCH_LS1043A | |
fa18ed76 | 346 | |
2d16a1a6 | 347 | menu "Layerscape PPA" |
348 | config FSL_LS_PPA | |
349 | bool "FSL Layerscape PPA firmware support" | |
df88cb3b | 350 | depends on !ARMV8_PSCI |
0541527b | 351 | select ARMV8_SEC_FIRMWARE_SUPPORT |
daa92644 | 352 | select SEC_FIRMWARE_ARMV8_PSCI |
0541527b | 353 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 |
2d16a1a6 | 354 | help |
355 | The FSL Primary Protected Application (PPA) is a software component | |
356 | which is loaded during boot stage, and then remains resident in RAM | |
357 | and runs in the TrustZone after boot. | |
358 | Say y to enable it. | |
8e59778b YS |
359 | |
360 | config SPL_FSL_LS_PPA | |
361 | bool "FSL Layerscape PPA firmware support for SPL build" | |
362 | depends on !ARMV8_PSCI | |
363 | select SPL_ARMV8_SEC_FIRMWARE_SUPPORT | |
364 | select SEC_FIRMWARE_ARMV8_PSCI | |
365 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 | |
366 | help | |
367 | The FSL Primary Protected Application (PPA) is a software component | |
368 | which is loaded during boot stage, and then remains resident in RAM | |
369 | and runs in the TrustZone after boot. This is to load PPA during SPL | |
370 | stage instead of the RAM version of U-Boot. Once PPA is initialized, | |
371 | the rest of U-Boot (including RAM version) runs at EL2. | |
0541527b HZ |
372 | choice |
373 | prompt "FSL Layerscape PPA firmware loading-media select" | |
374 | depends on FSL_LS_PPA | |
77bbe55d HZ |
375 | default SYS_LS_PPA_FW_IN_MMC if SD_BOOT |
376 | default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT | |
0541527b HZ |
377 | default SYS_LS_PPA_FW_IN_XIP |
378 | ||
379 | config SYS_LS_PPA_FW_IN_XIP | |
380 | bool "XIP" | |
381 | help | |
382 | Say Y here if the PPA firmware locate at XIP flash, such | |
383 | as NOR or QSPI flash. | |
384 | ||
77bbe55d HZ |
385 | config SYS_LS_PPA_FW_IN_MMC |
386 | bool "eMMC or SD Card" | |
387 | help | |
388 | Say Y here if the PPA firmware locate at eMMC/SD card. | |
389 | ||
390 | config SYS_LS_PPA_FW_IN_NAND | |
391 | bool "NAND" | |
392 | help | |
393 | Say Y here if the PPA firmware locate at NAND flash. | |
394 | ||
0541527b HZ |
395 | endchoice |
396 | ||
9fa3a542 SG |
397 | config LS_PPA_ESBC_HDR_SIZE |
398 | hex "Length of PPA ESBC header" | |
399 | depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP | |
400 | default 0x2000 | |
401 | help | |
402 | Length (in bytes) of PPA ESBC header to be copied from MMC/SD or | |
403 | NAND to memory to validate PPA image. | |
404 | ||
2d16a1a6 | 405 | endmenu |
406 | ||
9d1cd910 RW |
407 | config SYS_FSL_ERRATUM_A008997 |
408 | bool "Workaround for USB PHY erratum A008997" | |
409 | ||
15d59b53 RW |
410 | config SYS_FSL_ERRATUM_A009007 |
411 | bool | |
412 | help | |
413 | Workaround for USB PHY erratum A009007 | |
414 | ||
2ab1553f RW |
415 | config SYS_FSL_ERRATUM_A009008 |
416 | bool "Workaround for USB PHY erratum A009008" | |
417 | ||
2a8a3539 RW |
418 | config SYS_FSL_ERRATUM_A009798 |
419 | bool "Workaround for USB PHY erratum A009798" | |
420 | ||
390c73b4 RW |
421 | config SYS_FSL_ERRATUM_A050204 |
422 | bool "Workaround for USB PHY erratum A050204" | |
0cfa00cd RW |
423 | help |
424 | USB3.0 Receiver needs to enable fixed equalization | |
425 | for each of PHY instances in an SOC. This is similar | |
3a187cff | 426 | to erratum A-009007, but this one is for LX2160A and LX2162A, |
0cfa00cd RW |
427 | and the register value is different. |
428 | ||
0a37cf8f YS |
429 | config SYS_FSL_ERRATUM_A010315 |
430 | bool "Workaround for PCIe erratum A010315" | |
0ea3671d HZ |
431 | |
432 | config SYS_FSL_ERRATUM_A010539 | |
433 | bool "Workaround for PIN MUX erratum A010539" | |
fb2bf8c2 | 434 | |
b4b60d06 YS |
435 | config MAX_CPUS |
436 | int "Maximum number of CPUs permitted for Layerscape" | |
d4ad111d | 437 | default 2 if ARCH_LS1028A |
b4b60d06 YS |
438 | default 4 if ARCH_LS1043A |
439 | default 4 if ARCH_LS1046A | |
440 | default 16 if ARCH_LS2080A | |
6d9b82d0 | 441 | default 8 if ARCH_LS1088A |
4909b89e | 442 | default 16 if ARCH_LX2160A |
3a187cff | 443 | default 16 if ARCH_LX2162A |
b4b60d06 YS |
444 | default 1 |
445 | help | |
446 | Set this number to the maximum number of possible CPUs in the SoC. | |
447 | SoCs may have multiple clusters with each cluster may have multiple | |
448 | ports. If some ports are reserved but higher ports are used for | |
449 | cores, count the reserved ports. This will allocate enough memory | |
450 | in spin table to properly handle all cores. | |
451 | ||
e088e587 MA |
452 | config EMC2305 |
453 | bool "Fan controller" | |
454 | help | |
455 | Enable the EMC2305 fan controller for configuration of fan | |
456 | speed. | |
457 | ||
5536c3c9 UA |
458 | config NXP_ESBC |
459 | bool "NXP_ESBC" | |
01f65d97 YS |
460 | help |
461 | Enable Freescale Secure Boot feature | |
462 | ||
dd2ad2f1 YY |
463 | config QSPI_AHB_INIT |
464 | bool "Init the QSPI AHB bus" | |
465 | help | |
466 | The default setting for QSPI AHB bus just support 3bytes addressing. | |
467 | But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB | |
468 | bus for those flashes to support the full QSPI flash size. | |
469 | ||
ce3bead6 KS |
470 | config FSPI_AHB_EN_4BYTE |
471 | bool "Enable 4-byte Fast Read command for AHB mode" | |
ce3bead6 KS |
472 | help |
473 | The default setting for FlexSPI AHB bus just supports 3-byte addressing. | |
474 | But some FlexSPI flash sizes are up to 64MBytes. | |
475 | This flag enables fast read command for AHB mode and modifies required | |
476 | LUT to support full FlexSPI flash. | |
477 | ||
63b2316c AK |
478 | config SYS_CCI400_OFFSET |
479 | hex "Offset for CCI400 base" | |
480 | depends on SYS_FSL_HAS_CCI400 | |
d4ad111d | 481 | default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A |
63b2316c AK |
482 | default 0x180000 if FSL_LSCH2 |
483 | help | |
484 | Offset for CCI400 base | |
485 | CCI400 base addr = CCSRBAR + CCI400_OFFSET | |
486 | ||
25af7dc1 YS |
487 | config SYS_FSL_IFC_BANK_COUNT |
488 | int "Maximum banks of Integrated flash controller" | |
6d9b82d0 | 489 | depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A |
25af7dc1 YS |
490 | default 4 if ARCH_LS1043A |
491 | default 4 if ARCH_LS1046A | |
6d9b82d0 | 492 | default 8 if ARCH_LS2080A || ARCH_LS1088A |
25af7dc1 | 493 | |
63b2316c AK |
494 | config SYS_FSL_HAS_CCI400 |
495 | bool | |
496 | ||
c055cee1 AK |
497 | config SYS_FSL_HAS_CCN504 |
498 | bool | |
499 | ||
4909b89e PJ |
500 | config SYS_FSL_HAS_CCN508 |
501 | bool | |
502 | ||
fd638102 YS |
503 | config SYS_FSL_HAS_DP_DDR |
504 | bool | |
505 | ||
f534b8f5 YS |
506 | config SYS_FSL_SRDS_1 |
507 | bool | |
508 | ||
509 | config SYS_FSL_SRDS_2 | |
510 | bool | |
511 | ||
6252faa0 PJ |
512 | config SYS_NXP_SRDS_3 |
513 | bool | |
514 | ||
f534b8f5 YS |
515 | config SYS_HAS_SERDES |
516 | bool | |
517 | ||
85a9a14e A |
518 | config FSL_TZASC_1 |
519 | bool | |
520 | ||
521 | config FSL_TZASC_2 | |
522 | bool | |
523 | ||
bbf5b252 RB |
524 | config FSL_TZASC_400 |
525 | bool | |
526 | ||
527 | config FSL_TZPC_BP147 | |
528 | bool | |
fb2bf8c2 | 529 | endmenu |
ba1b6fb5 | 530 | |
904110c7 HZ |
531 | menu "Layerscape clock tree configuration" |
532 | depends on FSL_LSCH2 || FSL_LSCH3 | |
533 | ||
904110c7 HZ |
534 | config CLUSTER_CLK_FREQ |
535 | int "Reference clock of core cluster" | |
536 | depends on ARCH_LS1012A | |
537 | default 100000000 | |
538 | help | |
539 | This number is the reference clock frequency of core PLL. | |
540 | For most platforms, the core PLL and Platform PLL have the same | |
541 | reference clock, but for some platforms, LS1012A for instance, | |
542 | they are provided sepatately. | |
543 | ||
544 | config SYS_FSL_PCLK_DIV | |
545 | int "Platform clock divider" | |
d4ad111d | 546 | default 1 if ARCH_LS1028A |
904110c7 HZ |
547 | default 1 if ARCH_LS1043A |
548 | default 1 if ARCH_LS1046A | |
6d9b82d0 | 549 | default 1 if ARCH_LS1088A |
904110c7 HZ |
550 | default 2 |
551 | help | |
552 | This is the divider that is used to derive Platform clock from | |
553 | Platform PLL, in another word: | |
554 | Platform_clk = Platform_PLL_freq / this_divider | |
555 | ||
556 | config SYS_FSL_DSPI_CLK_DIV | |
557 | int "DSPI clock divider" | |
558 | default 1 if ARCH_LS1043A | |
559 | default 2 | |
560 | help | |
561 | This is the divider that is used to derive DSPI clock from Platform | |
bf7aecce | 562 | clock, in another word DSPI_clk = Platform_clk / this_divider. |
904110c7 HZ |
563 | |
564 | config SYS_FSL_DUART_CLK_DIV | |
565 | int "DUART clock divider" | |
566 | default 1 if ARCH_LS1043A | |
4909b89e | 567 | default 4 if ARCH_LX2160A |
3a187cff | 568 | default 4 if ARCH_LX2162A |
904110c7 HZ |
569 | default 2 |
570 | help | |
571 | This is the divider that is used to derive DUART clock from Platform | |
572 | clock, in another word DUART_clk = Platform_clk / this_divider. | |
573 | ||
574 | config SYS_FSL_I2C_CLK_DIV | |
575 | int "I2C clock divider" | |
576 | default 1 if ARCH_LS1043A | |
71a2da3f CH |
577 | default 4 if ARCH_LS1012A |
578 | default 4 if ARCH_LS1028A | |
579 | default 8 if ARCH_LX2160A | |
3a187cff | 580 | default 8 if ARCH_LX2162A |
71a2da3f | 581 | default 8 if ARCH_LS1088A |
904110c7 HZ |
582 | default 2 |
583 | help | |
584 | This is the divider that is used to derive I2C clock from Platform | |
585 | clock, in another word I2C_clk = Platform_clk / this_divider. | |
586 | ||
587 | config SYS_FSL_IFC_CLK_DIV | |
588 | int "IFC clock divider" | |
589 | default 1 if ARCH_LS1043A | |
2f2a1975 CH |
590 | default 4 if ARCH_LS1012A |
591 | default 4 if ARCH_LS1028A | |
592 | default 8 if ARCH_LX2160A | |
3a187cff | 593 | default 8 if ARCH_LX2162A |
2f2a1975 | 594 | default 8 if ARCH_LS1088A |
904110c7 HZ |
595 | default 2 |
596 | help | |
597 | This is the divider that is used to derive IFC clock from Platform | |
598 | clock, in another word IFC_clk = Platform_clk / this_divider. | |
599 | ||
600 | config SYS_FSL_LPUART_CLK_DIV | |
601 | int "LPUART clock divider" | |
602 | default 1 if ARCH_LS1043A | |
603 | default 2 | |
604 | help | |
605 | This is the divider that is used to derive LPUART clock from Platform | |
606 | clock, in another word LPUART_clk = Platform_clk / this_divider. | |
607 | ||
608 | config SYS_FSL_SDHC_CLK_DIV | |
609 | int "SDHC clock divider" | |
610 | default 1 if ARCH_LS1043A | |
611 | default 1 if ARCH_LS1012A | |
612 | default 2 | |
613 | help | |
614 | This is the divider that is used to derive SDHC clock from Platform | |
615 | clock, in another word SDHC_clk = Platform_clk / this_divider. | |
945fad57 HZ |
616 | |
617 | config SYS_FSL_QMAN_CLK_DIV | |
618 | int "QMAN clock divider" | |
619 | default 1 if ARCH_LS1043A | |
620 | default 2 | |
621 | help | |
622 | This is the divider that is used to derive QMAN clock from Platform | |
623 | clock, in another word QMAN_clk = Platform_clk / this_divider. | |
904110c7 HZ |
624 | endmenu |
625 | ||
f2ccf7f7 YS |
626 | config RESV_RAM |
627 | bool | |
628 | help | |
629 | Reserve memory from the top, tracked by gd->arch.resv_ram. This | |
630 | reserved RAM can be used by special driver that resides in memory | |
631 | after U-Boot exits. It's up to implementation to allocate and allow | |
632 | access to this reserved memory. For example, the reserved RAM can | |
633 | be at the high end of physical memory. The reserve RAM may be | |
634 | excluded from memory bank(s) passed to OS, or marked as reserved. | |
635 | ||
17d066fc AK |
636 | config SYS_FSL_EC1 |
637 | bool | |
638 | help | |
4909b89e | 639 | Ethernet controller 1, this is connected to |
3a187cff | 640 | MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs |
17d066fc AK |
641 | Provides DPAA2 capabilities |
642 | ||
643 | config SYS_FSL_EC2 | |
644 | bool | |
645 | help | |
4909b89e | 646 | Ethernet controller 2, this is connected to |
3a187cff | 647 | MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs |
17d066fc AK |
648 | Provides DPAA2 capabilities |
649 | ||
ba1b6fb5 YS |
650 | config SYS_FSL_ERRATUM_A008336 |
651 | bool | |
652 | ||
653 | config SYS_FSL_ERRATUM_A008514 | |
654 | bool | |
655 | ||
656 | config SYS_FSL_ERRATUM_A008585 | |
657 | bool | |
658 | ||
659 | config SYS_FSL_ERRATUM_A008850 | |
660 | bool | |
661 | ||
dd48f0bf A |
662 | config SYS_FSL_ERRATUM_A009203 |
663 | bool | |
664 | ||
ba1b6fb5 YS |
665 | config SYS_FSL_ERRATUM_A009635 |
666 | bool | |
667 | ||
668 | config SYS_FSL_ERRATUM_A009660 | |
669 | bool | |
670 | ||
b4a59115 LT |
671 | config SYS_FSL_ERRATUM_A050382 |
672 | bool | |
17d066fc AK |
673 | |
674 | config SYS_FSL_HAS_RGMII | |
675 | bool | |
676 | depends on SYS_FSL_EC1 || SYS_FSL_EC2 | |
677 | ||
b529993e PT |
678 | config SPL_LDSCRIPT |
679 | default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A | |
4417e834 RW |
680 | |
681 | config HAS_FSL_XHCI_USB | |
682 | bool | |
4417e834 | 683 | help |
a968e9ad | 684 | For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use |
4417e834 | 685 | pins, select it when the pins are assigned to USB. |
504debcd RB |
686 | |
687 | config SYS_FSL_BOOTROM_BASE | |
688 | hex | |
689 | depends on FSL_LSCH2 | |
690 | default 0 | |
691 | ||
692 | config SYS_FSL_BOOTROM_SIZE | |
693 | hex | |
694 | depends on FSL_LSCH2 | |
695 | default 0x1000000 |