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Commit | Line | Data |
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2f78eae5 | 1 | /* |
9f3183d2 | 2 | * Copyright 2014-2015 Freescale Semiconductor, Inc. |
2f78eae5 YS |
3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/io.h> | |
99799220 | 9 | #include <asm/errno.h> |
2f78eae5 YS |
10 | #include <asm/system.h> |
11 | #include <asm/armv8/mmu.h> | |
12 | #include <asm/io.h> | |
9f3183d2 MH |
13 | #include <asm/arch/fsl_serdes.h> |
14 | #include <asm/arch/soc.h> | |
15 | #include <asm/arch/cpu.h> | |
16 | #include <asm/arch/speed.h> | |
17 | #ifdef CONFIG_MP | |
18 | #include <asm/arch/mp.h> | |
19 | #endif | |
20 | #include <fm_eth.h> | |
422cb08a | 21 | #include <fsl_debug_server.h> |
7b3bd9a7 | 22 | #include <fsl-mc/fsl_mc.h> |
8b06460e YL |
23 | #ifdef CONFIG_FSL_ESDHC |
24 | #include <fsl_esdhc.h> | |
25 | #endif | |
2f78eae5 YS |
26 | |
27 | DECLARE_GLOBAL_DATA_PTR; | |
28 | ||
5ad5823d | 29 | struct mm_region *mem_map = early_map; |
7985cdf7 | 30 | |
22629665 PK |
31 | void cpu_name(char *name) |
32 | { | |
33 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
34 | unsigned int i, svr, ver; | |
35 | ||
9f3183d2 | 36 | svr = gur_in32(&gur->svr); |
22629665 PK |
37 | ver = SVR_SOC_VER(svr); |
38 | ||
39 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) | |
40 | if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { | |
41 | strcpy(name, cpu_type_list[i].name); | |
42 | ||
43 | if (IS_E_PROCESSOR(svr)) | |
44 | strcat(name, "E"); | |
45 | break; | |
46 | } | |
47 | ||
48 | if (i == ARRAY_SIZE(cpu_type_list)) | |
49 | strcpy(name, "unknown"); | |
50 | } | |
51 | ||
2f78eae5 | 52 | #ifndef CONFIG_SYS_DCACHE_OFF |
99799220 AW |
53 | /* |
54 | * To start MMU before DDR is available, we create MMU table in SRAM. | |
55 | * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three | |
56 | * levels of translation tables here to cover 40-bit address space. | |
57 | * We use 4KB granule size, with 40 bits physical address, T0SZ=24 | |
5ad5823d YS |
58 | * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. |
59 | * Note, the debug print in cache_v8.c is not usable for debugging | |
60 | * these early MMU tables because UART is not yet available. | |
99799220 AW |
61 | */ |
62 | static inline void early_mmu_setup(void) | |
63 | { | |
5ad5823d | 64 | unsigned int el = current_el(); |
99799220 | 65 | |
5ad5823d YS |
66 | /* global data is already setup, no allocation yet */ |
67 | gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; | |
68 | gd->arch.tlb_fillptr = gd->arch.tlb_addr; | |
69 | gd->arch.tlb_size = EARLY_PGTABLE_SIZE; | |
99799220 | 70 | |
5ad5823d YS |
71 | /* Create early page tables */ |
72 | setup_pgtables(); | |
9f3183d2 | 73 | |
5ad5823d YS |
74 | /* point TTBR to the new table */ |
75 | set_ttbr_tcr_mair(el, gd->arch.tlb_addr, | |
76 | get_tcr(el, NULL, NULL) & | |
77 | ~(TCR_ORGN_MASK | TCR_IRGN_MASK), | |
9f3183d2 | 78 | MEMORY_ATTRIBUTES); |
c107c0c0 | 79 | |
5ad5823d | 80 | set_sctlr(get_sctlr() | CR_M); |
c107c0c0 | 81 | } |
c107c0c0 | 82 | |
2f78eae5 | 83 | /* |
99799220 AW |
84 | * The final tables look similar to early tables, but different in detail. |
85 | * These tables are in DRAM. Sub tables are added to enable cache for | |
86 | * QBMan and OCRAM. | |
87 | * | |
e61a7534 YS |
88 | * Put the MMU table in secure memory if gd->arch.secure_ram is valid. |
89 | * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. | |
2f78eae5 YS |
90 | */ |
91 | static inline void final_mmu_setup(void) | |
92 | { | |
5ad5823d | 93 | u64 tlb_addr_save = gd->arch.tlb_addr; |
c107c0c0 | 94 | unsigned int el = current_el(); |
c107c0c0 | 95 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
5ad5823d | 96 | int index; |
c107c0c0 | 97 | #endif |
2f78eae5 | 98 | |
5ad5823d | 99 | mem_map = final_map; |
2f78eae5 | 100 | |
c107c0c0 | 101 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
5ad5823d YS |
102 | if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { |
103 | if (el == 3) { | |
104 | /* | |
105 | * Only use gd->arch.secure_ram if the address is | |
106 | * recalculated. Align to 4KB for MMU table. | |
107 | */ | |
108 | /* put page tables in secure ram */ | |
109 | index = ARRAY_SIZE(final_map) - 2; | |
110 | gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; | |
111 | final_map[index].virt = gd->arch.secure_ram & ~0x3; | |
112 | final_map[index].phys = final_map[index].virt; | |
113 | final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; | |
114 | final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; | |
e61a7534 | 115 | gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; |
5ad5823d | 116 | tlb_addr_save = gd->arch.tlb_addr; |
c107c0c0 | 117 | } else { |
5ad5823d YS |
118 | /* Use allocated (board_f.c) memory for TLB */ |
119 | tlb_addr_save = gd->arch.tlb_allocated; | |
120 | gd->arch.tlb_addr = tlb_addr_save; | |
c107c0c0 YS |
121 | } |
122 | } | |
123 | #endif | |
2f78eae5 | 124 | |
5ad5823d YS |
125 | /* Reset the fill ptr */ |
126 | gd->arch.tlb_fillptr = tlb_addr_save; | |
127 | ||
128 | /* Create normal system page tables */ | |
129 | setup_pgtables(); | |
130 | ||
131 | /* Create emergency page tables */ | |
132 | gd->arch.tlb_addr = gd->arch.tlb_fillptr; | |
133 | gd->arch.tlb_emerg = gd->arch.tlb_addr; | |
134 | setup_pgtables(); | |
135 | gd->arch.tlb_addr = tlb_addr_save; | |
136 | ||
2f78eae5 | 137 | /* flush new MMU table */ |
5ad5823d YS |
138 | flush_dcache_range(gd->arch.tlb_addr, |
139 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
2f78eae5 YS |
140 | |
141 | /* point TTBR to the new table */ | |
5ad5823d | 142 | set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), |
db14f11d | 143 | MEMORY_ATTRIBUTES); |
2f78eae5 YS |
144 | /* |
145 | * MMU is already enabled, just need to invalidate TLB to load the | |
146 | * new table. The new table is compatible with the current table, if | |
147 | * MMU somehow walks through the new table before invalidation TLB, | |
148 | * it still works. So we don't need to turn off MMU here. | |
149 | */ | |
150 | } | |
151 | ||
c05016ab AG |
152 | u64 get_page_table_size(void) |
153 | { | |
154 | return 0x10000; | |
155 | } | |
156 | ||
2f78eae5 YS |
157 | int arch_cpu_init(void) |
158 | { | |
159 | icache_enable(); | |
160 | __asm_invalidate_dcache_all(); | |
161 | __asm_invalidate_tlb_all(); | |
162 | early_mmu_setup(); | |
163 | set_sctlr(get_sctlr() | CR_C); | |
164 | return 0; | |
165 | } | |
166 | ||
2f78eae5 YS |
167 | /* |
168 | * This function is called from lib/board.c. | |
169 | * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. | |
170 | * There is no need to disable d-cache for this operation. | |
171 | */ | |
172 | void enable_caches(void) | |
173 | { | |
174 | final_mmu_setup(); | |
175 | __asm_invalidate_tlb_all(); | |
176 | } | |
177 | #endif | |
178 | ||
179 | static inline u32 initiator_type(u32 cluster, int init_id) | |
180 | { | |
181 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
182 | u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; | |
9f3183d2 | 183 | u32 type = 0; |
2f78eae5 | 184 | |
9f3183d2 | 185 | type = gur_in32(&gur->tp_ityp[idx]); |
2f78eae5 YS |
186 | if (type & TP_ITYP_AV) |
187 | return type; | |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
192 | u32 cpu_mask(void) | |
193 | { | |
194 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
195 | int i = 0, count = 0; | |
196 | u32 cluster, type, mask = 0; | |
197 | ||
198 | do { | |
199 | int j; | |
9f3183d2 MH |
200 | |
201 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
2f78eae5 YS |
202 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
203 | type = initiator_type(cluster, j); | |
204 | if (type) { | |
205 | if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) | |
206 | mask |= 1 << count; | |
207 | count++; | |
208 | } | |
209 | } | |
210 | i++; | |
9f3183d2 | 211 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); |
2f78eae5 YS |
212 | |
213 | return mask; | |
214 | } | |
215 | ||
216 | /* | |
217 | * Return the number of cores on this SOC. | |
218 | */ | |
219 | int cpu_numcores(void) | |
220 | { | |
221 | return hweight32(cpu_mask()); | |
222 | } | |
223 | ||
224 | int fsl_qoriq_core_to_cluster(unsigned int core) | |
225 | { | |
226 | struct ccsr_gur __iomem *gur = | |
227 | (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
228 | int i = 0, count = 0; | |
229 | u32 cluster; | |
230 | ||
231 | do { | |
232 | int j; | |
9f3183d2 MH |
233 | |
234 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
2f78eae5 YS |
235 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
236 | if (initiator_type(cluster, j)) { | |
237 | if (count == core) | |
238 | return i; | |
239 | count++; | |
240 | } | |
241 | } | |
242 | i++; | |
9f3183d2 | 243 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); |
2f78eae5 YS |
244 | |
245 | return -1; /* cannot identify the cluster */ | |
246 | } | |
247 | ||
248 | u32 fsl_qoriq_core_to_type(unsigned int core) | |
249 | { | |
250 | struct ccsr_gur __iomem *gur = | |
251 | (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
252 | int i = 0, count = 0; | |
253 | u32 cluster, type; | |
254 | ||
255 | do { | |
256 | int j; | |
9f3183d2 MH |
257 | |
258 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
2f78eae5 YS |
259 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
260 | type = initiator_type(cluster, j); | |
261 | if (type) { | |
262 | if (count == core) | |
263 | return type; | |
264 | count++; | |
265 | } | |
266 | } | |
267 | i++; | |
9f3183d2 | 268 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); |
2f78eae5 YS |
269 | |
270 | return -1; /* cannot identify the cluster */ | |
271 | } | |
272 | ||
6fb522dc SD |
273 | uint get_svr(void) |
274 | { | |
275 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
276 | ||
277 | return gur_in32(&gur->svr); | |
278 | } | |
279 | ||
2f78eae5 YS |
280 | #ifdef CONFIG_DISPLAY_CPUINFO |
281 | int print_cpuinfo(void) | |
282 | { | |
d27bf906 | 283 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
2f78eae5 YS |
284 | struct sys_info sysinfo; |
285 | char buf[32]; | |
286 | unsigned int i, core; | |
3c1d218a | 287 | u32 type, rcw, svr = gur_in32(&gur->svr); |
2f78eae5 | 288 | |
22629665 PK |
289 | puts("SoC: "); |
290 | ||
291 | cpu_name(buf); | |
3c1d218a | 292 | printf(" %s (0x%x)\n", buf, svr); |
22629665 | 293 | memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); |
2f78eae5 YS |
294 | get_sys_info(&sysinfo); |
295 | puts("Clock Configuration:"); | |
296 | for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { | |
297 | if (!(i % 3)) | |
298 | puts("\n "); | |
299 | type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); | |
300 | printf("CPU%d(%s):%-4s MHz ", core, | |
301 | type == TY_ITYP_VER_A7 ? "A7 " : | |
302 | (type == TY_ITYP_VER_A53 ? "A53" : | |
303 | (type == TY_ITYP_VER_A57 ? "A57" : " ")), | |
304 | strmhz(buf, sysinfo.freq_processor[core])); | |
305 | } | |
306 | printf("\n Bus: %-4s MHz ", | |
307 | strmhz(buf, sysinfo.freq_systembus)); | |
d4c711f0 | 308 | printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); |
e8297341 SX |
309 | #ifdef CONFIG_SYS_DPAA_FMAN |
310 | printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); | |
311 | #endif | |
44937214 | 312 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
3c1d218a YS |
313 | if (soc_has_dp_ddr()) { |
314 | printf(" DP-DDR: %-4s MT/s", | |
315 | strmhz(buf, sysinfo.freq_ddrbus2)); | |
316 | } | |
9f3183d2 | 317 | #endif |
2f78eae5 YS |
318 | puts("\n"); |
319 | ||
9f3183d2 MH |
320 | /* |
321 | * Display the RCW, so that no one gets confused as to what RCW | |
d27bf906 BS |
322 | * we're actually using for this boot. |
323 | */ | |
324 | puts("Reset Configuration Word (RCW):"); | |
325 | for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { | |
9f3183d2 | 326 | rcw = gur_in32(&gur->rcwsr[i]); |
d27bf906 | 327 | if ((i % 4) == 0) |
9f3183d2 | 328 | printf("\n %08x:", i * 4); |
d27bf906 BS |
329 | printf(" %08x", rcw); |
330 | } | |
331 | puts("\n"); | |
332 | ||
2f78eae5 YS |
333 | return 0; |
334 | } | |
335 | #endif | |
b940ca64 | 336 | |
8b06460e YL |
337 | #ifdef CONFIG_FSL_ESDHC |
338 | int cpu_mmc_init(bd_t *bis) | |
339 | { | |
340 | return fsl_esdhc_mmc_init(bis); | |
341 | } | |
342 | #endif | |
343 | ||
b940ca64 GR |
344 | int cpu_eth_init(bd_t *bis) |
345 | { | |
346 | int error = 0; | |
347 | ||
348 | #ifdef CONFIG_FSL_MC_ENET | |
a2a55e51 | 349 | error = fsl_mc_ldpaa_init(bis); |
e8297341 SX |
350 | #endif |
351 | #ifdef CONFIG_FMAN_ENET | |
352 | fm_standard_init(bis); | |
b940ca64 GR |
353 | #endif |
354 | return error; | |
355 | } | |
40f8dec5 | 356 | |
40f8dec5 YS |
357 | int arch_early_init_r(void) |
358 | { | |
9f3183d2 MH |
359 | #ifdef CONFIG_MP |
360 | int rv = 1; | |
b4017364 PK |
361 | #endif |
362 | ||
363 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 | |
364 | erratum_a009635(); | |
365 | #endif | |
40f8dec5 | 366 | |
b4017364 | 367 | #ifdef CONFIG_MP |
9f3183d2 | 368 | rv = fsl_layerscape_wake_seconday_cores(); |
40f8dec5 YS |
369 | if (rv) |
370 | printf("Did not wake secondary cores\n"); | |
9f3183d2 | 371 | #endif |
40f8dec5 | 372 | |
31d34c6c ML |
373 | #ifdef CONFIG_SYS_HAS_SERDES |
374 | fsl_serdes_init(); | |
e8297341 SX |
375 | #endif |
376 | #ifdef CONFIG_FMAN_ENET | |
377 | fman_enet_init(); | |
31d34c6c | 378 | #endif |
40f8dec5 YS |
379 | return 0; |
380 | } | |
207774b2 YS |
381 | |
382 | int timer_init(void) | |
383 | { | |
384 | u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; | |
9f3183d2 | 385 | #ifdef CONFIG_FSL_LSCH3 |
207774b2 | 386 | u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; |
9f3183d2 | 387 | #endif |
a758177f YC |
388 | #ifdef CONFIG_LS2080A |
389 | u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; | |
390 | #endif | |
207774b2 YS |
391 | #ifdef COUNTER_FREQUENCY_REAL |
392 | unsigned long cntfrq = COUNTER_FREQUENCY_REAL; | |
393 | ||
394 | /* Update with accurate clock frequency */ | |
395 | asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); | |
396 | #endif | |
397 | ||
9f3183d2 | 398 | #ifdef CONFIG_FSL_LSCH3 |
207774b2 YS |
399 | /* Enable timebase for all clusters. |
400 | * It is safe to do so even some clusters are not enabled. | |
401 | */ | |
402 | out_le32(cltbenr, 0xf); | |
9f3183d2 | 403 | #endif |
207774b2 | 404 | |
a758177f YC |
405 | #ifdef CONFIG_LS2080A |
406 | /* | |
407 | * In certain Layerscape SoCs, the clock for each core's | |
408 | * has an enable bit in the PMU Physical Core Time Base Enable | |
409 | * Register (PCTBENR), which allows the watchdog to operate. | |
410 | */ | |
411 | setbits_le32(pctbenr, 0xff); | |
412 | #endif | |
413 | ||
207774b2 YS |
414 | /* Enable clock for timer |
415 | * This is a global setting. | |
416 | */ | |
417 | out_le32(cntcr, 0x1); | |
418 | ||
419 | return 0; | |
420 | } | |
05d2e21b | 421 | |
422 | void reset_cpu(ulong addr) | |
423 | { | |
424 | u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; | |
425 | u32 val; | |
426 | ||
427 | /* Raise RESET_REQ_B */ | |
9f3183d2 | 428 | val = scfg_in32(rstcr); |
05d2e21b | 429 | val |= 0x02; |
9f3183d2 | 430 | scfg_out32(rstcr, val); |
05d2e21b | 431 | } |
c0492141 YS |
432 | |
433 | phys_size_t board_reserve_ram_top(phys_size_t ram_size) | |
434 | { | |
435 | phys_size_t ram_top = ram_size; | |
436 | ||
437 | #ifdef CONFIG_SYS_MEM_TOP_HIDE | |
438 | #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function | |
439 | #endif | |
440 | /* Carve the Debug Server private DRAM block from the end of DRAM */ | |
441 | #ifdef CONFIG_FSL_DEBUG_SERVER | |
442 | ram_top -= debug_server_get_dram_block_size(); | |
443 | #endif | |
444 | ||
445 | /* Carve the MC private DRAM block from the end of DRAM */ | |
446 | #ifdef CONFIG_FSL_MC_ENET | |
447 | ram_top -= mc_get_dram_block_size(); | |
448 | ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); | |
449 | #endif | |
450 | ||
451 | return ram_top; | |
452 | } |