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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
2f78eae5 | 2 | /* |
8976556a | 3 | * Copyright 2017-2021 NXP |
9f3183d2 | 4 | * Copyright 2014-2015 Freescale Semiconductor, Inc. |
2f78eae5 YS |
5 | */ |
6 | ||
7 | #include <common.h> | |
2f8a6db5 | 8 | #include <clock_legacy.h> |
b5981474 | 9 | #include <cpu_func.h> |
3a7d5571 | 10 | #include <env.h> |
9b4a205f | 11 | #include <init.h> |
db41d65a | 12 | #include <hang.h> |
f7ae49fc | 13 | #include <log.h> |
90526e9f | 14 | #include <net.h> |
2189d5f1 | 15 | #include <vsprintf.h> |
90526e9f | 16 | #include <asm/cache.h> |
401d1c4f | 17 | #include <asm/global_data.h> |
2f78eae5 | 18 | #include <asm/io.h> |
25a5818f | 19 | #include <asm/ptrace.h> |
cb14cc88 | 20 | #include <linux/arm-smccc.h> |
1221ce45 | 21 | #include <linux/errno.h> |
2f78eae5 | 22 | #include <asm/system.h> |
9cce5663 | 23 | #include <fm_eth.h> |
2f78eae5 YS |
24 | #include <asm/armv8/mmu.h> |
25 | #include <asm/io.h> | |
9f3183d2 MH |
26 | #include <asm/arch/fsl_serdes.h> |
27 | #include <asm/arch/soc.h> | |
28 | #include <asm/arch/cpu.h> | |
29 | #include <asm/arch/speed.h> | |
63b2316c | 30 | #include <fsl_immap.h> |
9f3183d2 | 31 | #include <asm/arch/mp.h> |
78d57842 | 32 | #include <efi_loader.h> |
7b3bd9a7 | 33 | #include <fsl-mc/fsl_mc.h> |
8b06460e YL |
34 | #ifdef CONFIG_FSL_ESDHC |
35 | #include <fsl_esdhc.h> | |
36 | #endif | |
032d5bb4 | 37 | #include <asm/armv8/sec_firmware.h> |
02fb2761 | 38 | #ifdef CONFIG_SYS_FSL_DDR |
f9147d63 | 39 | #include <fsl_ddr_sdram.h> |
02fb2761 SL |
40 | #include <fsl_ddr.h> |
41 | #endif | |
6e2941d7 | 42 | #include <asm/arch/clock.h> |
2db53cfe | 43 | #include <hwconfig.h> |
44262327 | 44 | #include <fsl_qbman.h> |
2f78eae5 | 45 | |
4c417384 | 46 | #ifdef CONFIG_TFABOOT |
f3998fdc | 47 | #include <env_internal.h> |
2141d250 PG |
48 | #ifdef CONFIG_CHAIN_OF_TRUST |
49 | #include <fsl_validate.h> | |
50 | #endif | |
4c417384 | 51 | #endif |
68a6aa85 | 52 | #include <linux/mii.h> |
8976556a | 53 | #include <dm.h> |
4c417384 | 54 | |
2f78eae5 YS |
55 | DECLARE_GLOBAL_DATA_PTR; |
56 | ||
d171c707 YS |
57 | static struct cpu_type cpu_type_list[] = { |
58 | CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), | |
59 | CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), | |
60 | CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), | |
61 | CPU_TYPE_ENTRY(LS2088A, LS2088A, 8), | |
62 | CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), | |
63 | CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), | |
64 | CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), | |
65 | CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), | |
66 | CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), | |
67 | CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), | |
ec88ff80 | 68 | CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4), |
d171c707 | 69 | CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), |
ec88ff80 | 70 | CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2), |
d171c707 YS |
71 | CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), |
72 | CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), | |
73 | CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), | |
74 | CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), | |
6ed69523 YT |
75 | CPU_TYPE_ENTRY(LS1017A, LS1017A, 1), |
76 | CPU_TYPE_ENTRY(LS1018A, LS1018A, 1), | |
77 | CPU_TYPE_ENTRY(LS1027A, LS1027A, 2), | |
d4ad111d | 78 | CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), |
d171c707 YS |
79 | CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), |
80 | CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), | |
81 | CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), | |
82 | CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), | |
4909b89e PJ |
83 | CPU_TYPE_ENTRY(LX2160A, LX2160A, 16), |
84 | CPU_TYPE_ENTRY(LX2120A, LX2120A, 12), | |
85 | CPU_TYPE_ENTRY(LX2080A, LX2080A, 8), | |
3a187cff MA |
86 | CPU_TYPE_ENTRY(LX2162A, LX2162A, 16), |
87 | CPU_TYPE_ENTRY(LX2122A, LX2122A, 12), | |
88 | CPU_TYPE_ENTRY(LX2082A, LX2082A, 8), | |
d171c707 YS |
89 | }; |
90 | ||
91 | #define EARLY_PGTABLE_SIZE 0x5000 | |
92 | static struct mm_region early_map[] = { | |
93 | #ifdef CONFIG_FSL_LSCH3 | |
94 | { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, | |
95 | CONFIG_SYS_FSL_CCSR_SIZE, | |
96 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
97 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
98 | }, | |
99 | { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, | |
100 | SYS_FSL_OCRAM_SPACE_SIZE, | |
101 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE | |
102 | }, | |
103 | { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, | |
104 | CONFIG_SYS_FSL_QSPI_SIZE1, | |
105 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, | |
106 | #ifdef CONFIG_FSL_IFC | |
107 | /* For IFC Region #1, only the first 4MB is cache-enabled */ | |
108 | { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, | |
109 | CONFIG_SYS_FSL_IFC_SIZE1_1, | |
110 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE | |
111 | }, | |
112 | { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, | |
113 | CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, | |
114 | CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, | |
115 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | |
116 | }, | |
117 | { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, | |
118 | CONFIG_SYS_FSL_IFC_SIZE1, | |
119 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | |
120 | }, | |
121 | #endif | |
122 | { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, | |
123 | CONFIG_SYS_FSL_DRAM_SIZE1, | |
535d76a1 RB |
124 | #if defined(CONFIG_TFABOOT) || \ |
125 | (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) | |
d171c707 YS |
126 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
127 | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ | |
128 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | | |
129 | #endif | |
130 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
131 | }, | |
132 | #ifdef CONFIG_FSL_IFC | |
133 | /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ | |
134 | { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, | |
135 | CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, | |
136 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | |
137 | }, | |
138 | #endif | |
139 | { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, | |
140 | CONFIG_SYS_FSL_DCSR_SIZE, | |
141 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
142 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
143 | }, | |
144 | { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, | |
145 | CONFIG_SYS_FSL_DRAM_SIZE2, | |
146 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | | |
147 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
148 | }, | |
d6fdec21 PJ |
149 | #ifdef CONFIG_SYS_FSL_DRAM_BASE3 |
150 | { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, | |
151 | CONFIG_SYS_FSL_DRAM_SIZE3, | |
152 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | | |
153 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
154 | }, | |
155 | #endif | |
d171c707 YS |
156 | #elif defined(CONFIG_FSL_LSCH2) |
157 | { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, | |
158 | CONFIG_SYS_FSL_CCSR_SIZE, | |
159 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
160 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
161 | }, | |
162 | { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, | |
163 | SYS_FSL_OCRAM_SPACE_SIZE, | |
164 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE | |
165 | }, | |
166 | { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, | |
167 | CONFIG_SYS_FSL_DCSR_SIZE, | |
168 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
169 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
170 | }, | |
171 | { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, | |
172 | CONFIG_SYS_FSL_QSPI_SIZE, | |
173 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | |
174 | }, | |
175 | #ifdef CONFIG_FSL_IFC | |
176 | { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, | |
177 | CONFIG_SYS_FSL_IFC_SIZE, | |
178 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | |
179 | }, | |
180 | #endif | |
181 | { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, | |
182 | CONFIG_SYS_FSL_DRAM_SIZE1, | |
535d76a1 RB |
183 | #if defined(CONFIG_TFABOOT) || \ |
184 | (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) | |
d171c707 YS |
185 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
186 | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ | |
187 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | | |
188 | #endif | |
189 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
190 | }, | |
191 | { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, | |
192 | CONFIG_SYS_FSL_DRAM_SIZE2, | |
193 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | | |
194 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
195 | }, | |
196 | #endif | |
197 | {}, /* list terminator */ | |
198 | }; | |
199 | ||
200 | static struct mm_region final_map[] = { | |
201 | #ifdef CONFIG_FSL_LSCH3 | |
202 | { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, | |
203 | CONFIG_SYS_FSL_CCSR_SIZE, | |
204 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
205 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
206 | }, | |
207 | { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, | |
208 | SYS_FSL_OCRAM_SPACE_SIZE, | |
209 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE | |
210 | }, | |
211 | { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, | |
212 | CONFIG_SYS_FSL_DRAM_SIZE1, | |
213 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
214 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
215 | }, | |
216 | { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, | |
217 | CONFIG_SYS_FSL_QSPI_SIZE1, | |
218 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
219 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
220 | }, | |
221 | { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, | |
222 | CONFIG_SYS_FSL_QSPI_SIZE2, | |
223 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
224 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
225 | }, | |
226 | #ifdef CONFIG_FSL_IFC | |
227 | { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, | |
228 | CONFIG_SYS_FSL_IFC_SIZE2, | |
229 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
230 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
231 | }, | |
232 | #endif | |
233 | { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, | |
234 | CONFIG_SYS_FSL_DCSR_SIZE, | |
235 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
236 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
237 | }, | |
238 | { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, | |
239 | CONFIG_SYS_FSL_MC_SIZE, | |
240 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
241 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
242 | }, | |
243 | { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, | |
244 | CONFIG_SYS_FSL_NI_SIZE, | |
245 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
246 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
247 | }, | |
248 | /* For QBMAN portal, only the first 64MB is cache-enabled */ | |
249 | { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, | |
250 | CONFIG_SYS_FSL_QBMAN_SIZE_1, | |
251 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
252 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS | |
253 | }, | |
254 | { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, | |
255 | CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, | |
256 | CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, | |
257 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
258 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
259 | }, | |
260 | { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, | |
261 | CONFIG_SYS_PCIE1_PHYS_SIZE, | |
262 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
263 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
264 | }, | |
265 | { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, | |
266 | CONFIG_SYS_PCIE2_PHYS_SIZE, | |
267 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
268 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
269 | }, | |
d4ad111d | 270 | #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR |
d171c707 YS |
271 | { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, |
272 | CONFIG_SYS_PCIE3_PHYS_SIZE, | |
273 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
274 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
275 | }, | |
d4ad111d | 276 | #endif |
8348e798 | 277 | #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR |
d171c707 YS |
278 | { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, |
279 | CONFIG_SYS_PCIE4_PHYS_SIZE, | |
280 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
281 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
282 | }, | |
059d9422 HZ |
283 | #endif |
284 | #ifdef SYS_PCIE5_PHYS_ADDR | |
285 | { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR, | |
286 | SYS_PCIE5_PHYS_SIZE, | |
287 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
288 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
289 | }, | |
290 | #endif | |
291 | #ifdef SYS_PCIE6_PHYS_ADDR | |
292 | { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR, | |
293 | SYS_PCIE6_PHYS_SIZE, | |
294 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
295 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
296 | }, | |
d171c707 YS |
297 | #endif |
298 | { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, | |
299 | CONFIG_SYS_FSL_WRIOP1_SIZE, | |
300 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
301 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
302 | }, | |
303 | { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, | |
304 | CONFIG_SYS_FSL_AIOP1_SIZE, | |
305 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
306 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
307 | }, | |
308 | { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, | |
309 | CONFIG_SYS_FSL_PEBUF_SIZE, | |
310 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
311 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
312 | }, | |
313 | { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, | |
314 | CONFIG_SYS_FSL_DRAM_SIZE2, | |
315 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
316 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
317 | }, | |
d6fdec21 PJ |
318 | #ifdef CONFIG_SYS_FSL_DRAM_BASE3 |
319 | { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, | |
320 | CONFIG_SYS_FSL_DRAM_SIZE3, | |
321 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
322 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
323 | }, | |
324 | #endif | |
d171c707 YS |
325 | #elif defined(CONFIG_FSL_LSCH2) |
326 | { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, | |
327 | CONFIG_SYS_FSL_BOOTROM_SIZE, | |
328 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
329 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
330 | }, | |
331 | { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, | |
332 | CONFIG_SYS_FSL_CCSR_SIZE, | |
333 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
334 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
335 | }, | |
336 | { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, | |
337 | SYS_FSL_OCRAM_SPACE_SIZE, | |
338 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE | |
339 | }, | |
340 | { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, | |
341 | CONFIG_SYS_FSL_DCSR_SIZE, | |
342 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
343 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
344 | }, | |
345 | { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, | |
346 | CONFIG_SYS_FSL_QSPI_SIZE, | |
347 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
348 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
349 | }, | |
350 | #ifdef CONFIG_FSL_IFC | |
351 | { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, | |
352 | CONFIG_SYS_FSL_IFC_SIZE, | |
353 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | |
354 | }, | |
355 | #endif | |
356 | { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, | |
357 | CONFIG_SYS_FSL_DRAM_SIZE1, | |
358 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
359 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
360 | }, | |
361 | { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, | |
362 | CONFIG_SYS_FSL_QBMAN_SIZE, | |
363 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
364 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
365 | }, | |
366 | { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, | |
367 | CONFIG_SYS_FSL_DRAM_SIZE2, | |
368 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
369 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
370 | }, | |
371 | { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, | |
372 | CONFIG_SYS_PCIE1_PHYS_SIZE, | |
373 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
374 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
375 | }, | |
376 | { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, | |
377 | CONFIG_SYS_PCIE2_PHYS_SIZE, | |
378 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
379 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
380 | }, | |
d4ad111d | 381 | #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR |
d171c707 YS |
382 | { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, |
383 | CONFIG_SYS_PCIE3_PHYS_SIZE, | |
384 | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
385 | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
386 | }, | |
d4ad111d | 387 | #endif |
d171c707 YS |
388 | { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, |
389 | CONFIG_SYS_FSL_DRAM_SIZE3, | |
390 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
391 | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | |
392 | }, | |
393 | #endif | |
394 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE | |
395 | {}, /* space holder for secure mem */ | |
396 | #endif | |
397 | {}, | |
398 | }; | |
399 | ||
5ad5823d | 400 | struct mm_region *mem_map = early_map; |
7985cdf7 | 401 | |
22629665 PK |
402 | void cpu_name(char *name) |
403 | { | |
404 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
405 | unsigned int i, svr, ver; | |
406 | ||
9f3183d2 | 407 | svr = gur_in32(&gur->svr); |
22629665 PK |
408 | ver = SVR_SOC_VER(svr); |
409 | ||
410 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) | |
411 | if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { | |
412 | strcpy(name, cpu_type_list[i].name); | |
3a187cff | 413 | #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) |
4909b89e PJ |
414 | if (IS_C_PROCESSOR(svr)) |
415 | strcat(name, "C"); | |
416 | #endif | |
22629665 PK |
417 | |
418 | if (IS_E_PROCESSOR(svr)) | |
419 | strcat(name, "E"); | |
5d1a7a9d WS |
420 | |
421 | sprintf(name + strlen(name), " Rev%d.%d", | |
422 | SVR_MAJ(svr), SVR_MIN(svr)); | |
22629665 PK |
423 | break; |
424 | } | |
425 | ||
426 | if (i == ARRAY_SIZE(cpu_type_list)) | |
427 | strcpy(name, "unknown"); | |
428 | } | |
429 | ||
10015025 | 430 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
99799220 AW |
431 | /* |
432 | * To start MMU before DDR is available, we create MMU table in SRAM. | |
433 | * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three | |
434 | * levels of translation tables here to cover 40-bit address space. | |
435 | * We use 4KB granule size, with 40 bits physical address, T0SZ=24 | |
5ad5823d YS |
436 | * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. |
437 | * Note, the debug print in cache_v8.c is not usable for debugging | |
438 | * these early MMU tables because UART is not yet available. | |
99799220 AW |
439 | */ |
440 | static inline void early_mmu_setup(void) | |
441 | { | |
5ad5823d | 442 | unsigned int el = current_el(); |
99799220 | 443 | |
5ad5823d | 444 | /* global data is already setup, no allocation yet */ |
e3506480 PG |
445 | if (el == 3) |
446 | gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; | |
447 | else | |
448 | gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; | |
5ad5823d YS |
449 | gd->arch.tlb_fillptr = gd->arch.tlb_addr; |
450 | gd->arch.tlb_size = EARLY_PGTABLE_SIZE; | |
99799220 | 451 | |
5ad5823d YS |
452 | /* Create early page tables */ |
453 | setup_pgtables(); | |
9f3183d2 | 454 | |
5ad5823d YS |
455 | /* point TTBR to the new table */ |
456 | set_ttbr_tcr_mair(el, gd->arch.tlb_addr, | |
457 | get_tcr(el, NULL, NULL) & | |
458 | ~(TCR_ORGN_MASK | TCR_IRGN_MASK), | |
9f3183d2 | 459 | MEMORY_ATTRIBUTES); |
c107c0c0 | 460 | |
5ad5823d | 461 | set_sctlr(get_sctlr() | CR_M); |
c107c0c0 | 462 | } |
c107c0c0 | 463 | |
3d8553f0 HZ |
464 | static void fix_pcie_mmu_map(void) |
465 | { | |
4a3ab193 | 466 | #ifdef CONFIG_ARCH_LS2080A |
3d8553f0 HZ |
467 | unsigned int i; |
468 | u32 svr, ver; | |
469 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
470 | ||
471 | svr = gur_in32(&gur->svr); | |
472 | ver = SVR_SOC_VER(svr); | |
473 | ||
474 | /* Fix PCIE base and size for LS2088A */ | |
475 | if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) || | |
e809e747 PJ |
476 | (ver == SVR_LS2048A) || (ver == SVR_LS2044A) || |
477 | (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { | |
3d8553f0 HZ |
478 | for (i = 0; i < ARRAY_SIZE(final_map); i++) { |
479 | switch (final_map[i].phys) { | |
480 | case CONFIG_SYS_PCIE1_PHYS_ADDR: | |
481 | final_map[i].phys = 0x2000000000ULL; | |
482 | final_map[i].virt = 0x2000000000ULL; | |
483 | final_map[i].size = 0x800000000ULL; | |
484 | break; | |
485 | case CONFIG_SYS_PCIE2_PHYS_ADDR: | |
486 | final_map[i].phys = 0x2800000000ULL; | |
487 | final_map[i].virt = 0x2800000000ULL; | |
488 | final_map[i].size = 0x800000000ULL; | |
489 | break; | |
d4ad111d | 490 | #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR |
3d8553f0 HZ |
491 | case CONFIG_SYS_PCIE3_PHYS_ADDR: |
492 | final_map[i].phys = 0x3000000000ULL; | |
493 | final_map[i].virt = 0x3000000000ULL; | |
494 | final_map[i].size = 0x800000000ULL; | |
495 | break; | |
d4ad111d | 496 | #endif |
8348e798 | 497 | #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR |
3d8553f0 HZ |
498 | case CONFIG_SYS_PCIE4_PHYS_ADDR: |
499 | final_map[i].phys = 0x3800000000ULL; | |
500 | final_map[i].virt = 0x3800000000ULL; | |
501 | final_map[i].size = 0x800000000ULL; | |
502 | break; | |
8348e798 | 503 | #endif |
3d8553f0 HZ |
504 | default: |
505 | break; | |
506 | } | |
507 | } | |
508 | } | |
509 | #endif | |
510 | } | |
511 | ||
2f78eae5 | 512 | /* |
99799220 AW |
513 | * The final tables look similar to early tables, but different in detail. |
514 | * These tables are in DRAM. Sub tables are added to enable cache for | |
515 | * QBMan and OCRAM. | |
516 | * | |
e61a7534 YS |
517 | * Put the MMU table in secure memory if gd->arch.secure_ram is valid. |
518 | * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. | |
2f78eae5 YS |
519 | */ |
520 | static inline void final_mmu_setup(void) | |
521 | { | |
5ad5823d | 522 | u64 tlb_addr_save = gd->arch.tlb_addr; |
c107c0c0 | 523 | unsigned int el = current_el(); |
5ad5823d | 524 | int index; |
2f78eae5 | 525 | |
3d8553f0 HZ |
526 | /* fix the final_map before filling in the block entries */ |
527 | fix_pcie_mmu_map(); | |
528 | ||
5ad5823d | 529 | mem_map = final_map; |
2f78eae5 | 530 | |
24f55496 YS |
531 | /* Update mapping for DDR to actual size */ |
532 | for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) { | |
533 | /* | |
534 | * Find the entry for DDR mapping and update the address and | |
535 | * size. Zero-sized mapping will be skipped when creating MMU | |
536 | * table. | |
537 | */ | |
538 | switch (final_map[index].virt) { | |
539 | case CONFIG_SYS_FSL_DRAM_BASE1: | |
540 | final_map[index].virt = gd->bd->bi_dram[0].start; | |
541 | final_map[index].phys = gd->bd->bi_dram[0].start; | |
542 | final_map[index].size = gd->bd->bi_dram[0].size; | |
543 | break; | |
544 | #ifdef CONFIG_SYS_FSL_DRAM_BASE2 | |
545 | case CONFIG_SYS_FSL_DRAM_BASE2: | |
546 | #if (CONFIG_NR_DRAM_BANKS >= 2) | |
547 | final_map[index].virt = gd->bd->bi_dram[1].start; | |
548 | final_map[index].phys = gd->bd->bi_dram[1].start; | |
549 | final_map[index].size = gd->bd->bi_dram[1].size; | |
550 | #else | |
551 | final_map[index].size = 0; | |
552 | #endif | |
553 | break; | |
554 | #endif | |
555 | #ifdef CONFIG_SYS_FSL_DRAM_BASE3 | |
556 | case CONFIG_SYS_FSL_DRAM_BASE3: | |
557 | #if (CONFIG_NR_DRAM_BANKS >= 3) | |
558 | final_map[index].virt = gd->bd->bi_dram[2].start; | |
559 | final_map[index].phys = gd->bd->bi_dram[2].start; | |
560 | final_map[index].size = gd->bd->bi_dram[2].size; | |
561 | #else | |
562 | final_map[index].size = 0; | |
563 | #endif | |
564 | break; | |
565 | #endif | |
566 | default: | |
567 | break; | |
568 | } | |
569 | } | |
570 | ||
c107c0c0 | 571 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
5ad5823d YS |
572 | if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { |
573 | if (el == 3) { | |
574 | /* | |
575 | * Only use gd->arch.secure_ram if the address is | |
576 | * recalculated. Align to 4KB for MMU table. | |
577 | */ | |
578 | /* put page tables in secure ram */ | |
579 | index = ARRAY_SIZE(final_map) - 2; | |
580 | gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; | |
581 | final_map[index].virt = gd->arch.secure_ram & ~0x3; | |
582 | final_map[index].phys = final_map[index].virt; | |
583 | final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; | |
584 | final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; | |
e61a7534 | 585 | gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; |
5ad5823d | 586 | tlb_addr_save = gd->arch.tlb_addr; |
c107c0c0 | 587 | } else { |
5ad5823d YS |
588 | /* Use allocated (board_f.c) memory for TLB */ |
589 | tlb_addr_save = gd->arch.tlb_allocated; | |
590 | gd->arch.tlb_addr = tlb_addr_save; | |
c107c0c0 YS |
591 | } |
592 | } | |
593 | #endif | |
2f78eae5 | 594 | |
5ad5823d YS |
595 | /* Reset the fill ptr */ |
596 | gd->arch.tlb_fillptr = tlb_addr_save; | |
597 | ||
598 | /* Create normal system page tables */ | |
599 | setup_pgtables(); | |
600 | ||
601 | /* Create emergency page tables */ | |
602 | gd->arch.tlb_addr = gd->arch.tlb_fillptr; | |
603 | gd->arch.tlb_emerg = gd->arch.tlb_addr; | |
604 | setup_pgtables(); | |
605 | gd->arch.tlb_addr = tlb_addr_save; | |
606 | ||
a045a0c3 YS |
607 | /* Disable cache and MMU */ |
608 | dcache_disable(); /* TLBs are invalidated */ | |
609 | invalidate_icache_all(); | |
2f78eae5 YS |
610 | |
611 | /* point TTBR to the new table */ | |
5ad5823d | 612 | set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), |
db14f11d | 613 | MEMORY_ATTRIBUTES); |
a045a0c3 | 614 | |
ed7a3943 | 615 | set_sctlr(get_sctlr() | CR_M); |
2f78eae5 YS |
616 | } |
617 | ||
c05016ab AG |
618 | u64 get_page_table_size(void) |
619 | { | |
620 | return 0x10000; | |
621 | } | |
622 | ||
2f78eae5 YS |
623 | int arch_cpu_init(void) |
624 | { | |
399e2bb6 YS |
625 | /* |
626 | * This function is called before U-Boot relocates itself to speed up | |
627 | * on system running. It is not necessary to run if performance is not | |
628 | * critical. Skip if MMU is already enabled by SPL or other means. | |
629 | */ | |
630 | if (get_sctlr() & CR_M) | |
631 | return 0; | |
632 | ||
2f78eae5 YS |
633 | icache_enable(); |
634 | __asm_invalidate_dcache_all(); | |
635 | __asm_invalidate_tlb_all(); | |
636 | early_mmu_setup(); | |
637 | set_sctlr(get_sctlr() | CR_C); | |
638 | return 0; | |
639 | } | |
640 | ||
85cdf38e HZ |
641 | void mmu_setup(void) |
642 | { | |
643 | final_mmu_setup(); | |
644 | } | |
645 | ||
2f78eae5 | 646 | /* |
85cdf38e HZ |
647 | * This function is called from common/board_r.c. |
648 | * It recreates MMU table in main memory. | |
2f78eae5 YS |
649 | */ |
650 | void enable_caches(void) | |
651 | { | |
85cdf38e | 652 | mmu_setup(); |
2f78eae5 | 653 | __asm_invalidate_tlb_all(); |
85cdf38e HZ |
654 | icache_enable(); |
655 | dcache_enable(); | |
2f78eae5 | 656 | } |
10015025 | 657 | #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ |
4c417384 RB |
658 | |
659 | #ifdef CONFIG_TFABOOT | |
660 | enum boot_src __get_boot_src(u32 porsr1) | |
661 | { | |
662 | enum boot_src src = BOOT_SOURCE_RESERVED; | |
663 | u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT; | |
d6fdec21 | 664 | #if !defined(CONFIG_NXP_LSCH3_2) |
4c417384 RB |
665 | u32 val; |
666 | #endif | |
667 | debug("%s: rcw_src 0x%x\n", __func__, rcw_src); | |
668 | ||
669 | #if defined(CONFIG_FSL_LSCH3) | |
d6fdec21 | 670 | #if defined(CONFIG_NXP_LSCH3_2) |
4c417384 RB |
671 | switch (rcw_src) { |
672 | case RCW_SRC_SDHC1_VAL: | |
673 | src = BOOT_SOURCE_SD_MMC; | |
674 | break; | |
675 | case RCW_SRC_SDHC2_VAL: | |
676 | src = BOOT_SOURCE_SD_MMC2; | |
677 | break; | |
678 | case RCW_SRC_I2C1_VAL: | |
679 | src = BOOT_SOURCE_I2C1_EXTENDED; | |
680 | break; | |
681 | case RCW_SRC_FLEXSPI_NAND2K_VAL: | |
682 | src = BOOT_SOURCE_XSPI_NAND; | |
683 | break; | |
684 | case RCW_SRC_FLEXSPI_NAND4K_VAL: | |
685 | src = BOOT_SOURCE_XSPI_NAND; | |
686 | break; | |
687 | case RCW_SRC_RESERVED_1_VAL: | |
688 | src = BOOT_SOURCE_RESERVED; | |
689 | break; | |
690 | case RCW_SRC_FLEXSPI_NOR_24B: | |
691 | src = BOOT_SOURCE_XSPI_NOR; | |
692 | break; | |
693 | default: | |
694 | src = BOOT_SOURCE_RESERVED; | |
695 | } | |
696 | #else | |
697 | val = rcw_src & RCW_SRC_TYPE_MASK; | |
698 | if (val == RCW_SRC_NOR_VAL) { | |
699 | val = rcw_src & NOR_TYPE_MASK; | |
700 | ||
701 | switch (val) { | |
702 | case NOR_16B_VAL: | |
703 | case NOR_32B_VAL: | |
704 | src = BOOT_SOURCE_IFC_NOR; | |
705 | break; | |
706 | default: | |
707 | src = BOOT_SOURCE_RESERVED; | |
708 | } | |
709 | } else { | |
710 | /* RCW SRC Serial Flash */ | |
711 | val = rcw_src & RCW_SRC_SERIAL_MASK; | |
712 | switch (val) { | |
713 | case RCW_SRC_QSPI_VAL: | |
714 | /* RCW SRC Serial NOR (QSPI) */ | |
715 | src = BOOT_SOURCE_QSPI_NOR; | |
716 | break; | |
717 | case RCW_SRC_SD_CARD_VAL: | |
718 | /* RCW SRC SD Card */ | |
719 | src = BOOT_SOURCE_SD_MMC; | |
720 | break; | |
721 | case RCW_SRC_EMMC_VAL: | |
722 | /* RCW SRC EMMC */ | |
d23da2ae | 723 | src = BOOT_SOURCE_SD_MMC; |
4c417384 RB |
724 | break; |
725 | case RCW_SRC_I2C1_VAL: | |
726 | /* RCW SRC I2C1 Extended */ | |
727 | src = BOOT_SOURCE_I2C1_EXTENDED; | |
728 | break; | |
729 | default: | |
730 | src = BOOT_SOURCE_RESERVED; | |
731 | } | |
732 | } | |
2f78eae5 | 733 | #endif |
4c417384 RB |
734 | #elif defined(CONFIG_FSL_LSCH2) |
735 | /* RCW SRC NAND */ | |
736 | val = rcw_src & RCW_SRC_NAND_MASK; | |
737 | if (val == RCW_SRC_NAND_VAL) { | |
738 | val = rcw_src & NAND_RESERVED_MASK; | |
739 | if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2) | |
740 | src = BOOT_SOURCE_IFC_NAND; | |
741 | ||
742 | } else { | |
743 | /* RCW SRC NOR */ | |
744 | val = rcw_src & RCW_SRC_NOR_MASK; | |
745 | if (val == NOR_8B_VAL || val == NOR_16B_VAL) { | |
746 | src = BOOT_SOURCE_IFC_NOR; | |
747 | } else { | |
748 | switch (rcw_src) { | |
749 | case QSPI_VAL1: | |
750 | case QSPI_VAL2: | |
751 | src = BOOT_SOURCE_QSPI_NOR; | |
752 | break; | |
753 | case SD_VAL: | |
754 | src = BOOT_SOURCE_SD_MMC; | |
755 | break; | |
756 | default: | |
757 | src = BOOT_SOURCE_RESERVED; | |
758 | } | |
759 | } | |
760 | } | |
761 | #endif | |
56db948b YS |
762 | |
763 | if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src) | |
764 | src = BOOT_SOURCE_QSPI_NOR; | |
765 | ||
4c417384 RB |
766 | debug("%s: src 0x%x\n", __func__, src); |
767 | return src; | |
768 | } | |
769 | ||
770 | enum boot_src get_boot_src(void) | |
771 | { | |
cb14cc88 | 772 | struct arm_smccc_res res; |
56db948b | 773 | u32 porsr1 = 0; |
4c417384 RB |
774 | |
775 | #if defined(CONFIG_FSL_LSCH3) | |
776 | u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; | |
4c417384 RB |
777 | #elif defined(CONFIG_FSL_LSCH2) |
778 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
56db948b YS |
779 | #endif |
780 | ||
781 | if (current_el() == 2) { | |
cb14cc88 MW |
782 | arm_smccc_smc(SIP_SVC_RCW, 0, 0, 0, 0, 0, 0, 0, &res); |
783 | if (!res.a0) | |
784 | porsr1 = res.a1; | |
56db948b YS |
785 | } |
786 | ||
787 | if (current_el() == 3 || !porsr1) { | |
788 | #ifdef CONFIG_FSL_LSCH3 | |
789 | porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); | |
790 | #elif defined(CONFIG_FSL_LSCH2) | |
791 | porsr1 = in_be32(&gur->porsr1); | |
4c417384 | 792 | #endif |
56db948b YS |
793 | } |
794 | ||
4c417384 RB |
795 | debug("%s: porsr1 0x%x\n", __func__, porsr1); |
796 | ||
797 | return __get_boot_src(porsr1); | |
798 | } | |
799 | ||
800 | #ifdef CONFIG_ENV_IS_IN_MMC | |
801 | int mmc_get_env_dev(void) | |
802 | { | |
803 | enum boot_src src = get_boot_src(); | |
804 | int dev = CONFIG_SYS_MMC_ENV_DEV; | |
805 | ||
806 | switch (src) { | |
807 | case BOOT_SOURCE_SD_MMC: | |
808 | dev = 0; | |
809 | break; | |
810 | case BOOT_SOURCE_SD_MMC2: | |
811 | dev = 1; | |
812 | break; | |
813 | default: | |
814 | break; | |
815 | } | |
816 | ||
817 | return dev; | |
818 | } | |
819 | #endif | |
820 | ||
dfb6da55 | 821 | enum env_location arch_env_get_location(enum env_operation op, int prio) |
4c417384 RB |
822 | { |
823 | enum boot_src src = get_boot_src(); | |
824 | enum env_location env_loc = ENVL_NOWHERE; | |
825 | ||
826 | if (prio) | |
827 | return ENVL_UNKNOWN; | |
828 | ||
d9532e80 UA |
829 | #ifdef CONFIG_ENV_IS_NOWHERE |
830 | return env_loc; | |
2141d250 PG |
831 | #endif |
832 | ||
4c417384 RB |
833 | switch (src) { |
834 | case BOOT_SOURCE_IFC_NOR: | |
835 | env_loc = ENVL_FLASH; | |
836 | break; | |
837 | case BOOT_SOURCE_QSPI_NOR: | |
838 | /* FALLTHROUGH */ | |
839 | case BOOT_SOURCE_XSPI_NOR: | |
840 | env_loc = ENVL_SPI_FLASH; | |
841 | break; | |
842 | case BOOT_SOURCE_IFC_NAND: | |
843 | /* FALLTHROUGH */ | |
844 | case BOOT_SOURCE_QSPI_NAND: | |
845 | /* FALLTHROUGH */ | |
846 | case BOOT_SOURCE_XSPI_NAND: | |
847 | env_loc = ENVL_NAND; | |
848 | break; | |
849 | case BOOT_SOURCE_SD_MMC: | |
850 | /* FALLTHROUGH */ | |
851 | case BOOT_SOURCE_SD_MMC2: | |
852 | env_loc = ENVL_MMC; | |
853 | break; | |
854 | case BOOT_SOURCE_I2C1_EXTENDED: | |
855 | /* FALLTHROUGH */ | |
856 | default: | |
857 | break; | |
858 | } | |
859 | ||
860 | return env_loc; | |
861 | } | |
862 | #endif /* CONFIG_TFABOOT */ | |
2f78eae5 | 863 | |
e87c673c | 864 | u32 initiator_type(u32 cluster, int init_id) |
2f78eae5 YS |
865 | { |
866 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
867 | u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; | |
9f3183d2 | 868 | u32 type = 0; |
2f78eae5 | 869 | |
9f3183d2 | 870 | type = gur_in32(&gur->tp_ityp[idx]); |
2f78eae5 YS |
871 | if (type & TP_ITYP_AV) |
872 | return type; | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
ef9a5fd8 YS |
877 | u32 cpu_pos_mask(void) |
878 | { | |
879 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
880 | int i = 0; | |
881 | u32 cluster, type, mask = 0; | |
882 | ||
883 | do { | |
884 | int j; | |
885 | ||
886 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
887 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { | |
888 | type = initiator_type(cluster, j); | |
889 | if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)) | |
890 | mask |= 1 << (i * TP_INIT_PER_CLUSTER + j); | |
891 | } | |
892 | i++; | |
893 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); | |
894 | ||
895 | return mask; | |
896 | } | |
897 | ||
2f78eae5 YS |
898 | u32 cpu_mask(void) |
899 | { | |
900 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
901 | int i = 0, count = 0; | |
902 | u32 cluster, type, mask = 0; | |
903 | ||
904 | do { | |
905 | int j; | |
9f3183d2 MH |
906 | |
907 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
2f78eae5 YS |
908 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
909 | type = initiator_type(cluster, j); | |
910 | if (type) { | |
911 | if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) | |
912 | mask |= 1 << count; | |
913 | count++; | |
914 | } | |
915 | } | |
916 | i++; | |
9f3183d2 | 917 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); |
2f78eae5 YS |
918 | |
919 | return mask; | |
920 | } | |
921 | ||
922 | /* | |
923 | * Return the number of cores on this SOC. | |
924 | */ | |
925 | int cpu_numcores(void) | |
926 | { | |
927 | return hweight32(cpu_mask()); | |
928 | } | |
929 | ||
930 | int fsl_qoriq_core_to_cluster(unsigned int core) | |
931 | { | |
932 | struct ccsr_gur __iomem *gur = | |
933 | (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
934 | int i = 0, count = 0; | |
935 | u32 cluster; | |
936 | ||
937 | do { | |
938 | int j; | |
9f3183d2 MH |
939 | |
940 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
2f78eae5 YS |
941 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
942 | if (initiator_type(cluster, j)) { | |
943 | if (count == core) | |
944 | return i; | |
945 | count++; | |
946 | } | |
947 | } | |
948 | i++; | |
9f3183d2 | 949 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); |
2f78eae5 YS |
950 | |
951 | return -1; /* cannot identify the cluster */ | |
952 | } | |
953 | ||
954 | u32 fsl_qoriq_core_to_type(unsigned int core) | |
955 | { | |
956 | struct ccsr_gur __iomem *gur = | |
957 | (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
958 | int i = 0, count = 0; | |
959 | u32 cluster, type; | |
960 | ||
961 | do { | |
962 | int j; | |
9f3183d2 MH |
963 | |
964 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
2f78eae5 YS |
965 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
966 | type = initiator_type(cluster, j); | |
967 | if (type) { | |
968 | if (count == core) | |
969 | return type; | |
970 | count++; | |
971 | } | |
972 | } | |
973 | i++; | |
9f3183d2 | 974 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); |
2f78eae5 YS |
975 | |
976 | return -1; /* cannot identify the cluster */ | |
977 | } | |
978 | ||
f6a70b3a | 979 | #ifndef CONFIG_FSL_LSCH3 |
6fb522dc SD |
980 | uint get_svr(void) |
981 | { | |
982 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
983 | ||
984 | return gur_in32(&gur->svr); | |
985 | } | |
f6a70b3a | 986 | #endif |
6fb522dc | 987 | |
2f78eae5 YS |
988 | #ifdef CONFIG_DISPLAY_CPUINFO |
989 | int print_cpuinfo(void) | |
990 | { | |
d27bf906 | 991 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
2f78eae5 YS |
992 | struct sys_info sysinfo; |
993 | char buf[32]; | |
994 | unsigned int i, core; | |
3c1d218a | 995 | u32 type, rcw, svr = gur_in32(&gur->svr); |
2f78eae5 | 996 | |
22629665 PK |
997 | puts("SoC: "); |
998 | ||
999 | cpu_name(buf); | |
3c1d218a | 1000 | printf(" %s (0x%x)\n", buf, svr); |
22629665 | 1001 | memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); |
2f78eae5 YS |
1002 | get_sys_info(&sysinfo); |
1003 | puts("Clock Configuration:"); | |
1004 | for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { | |
1005 | if (!(i % 3)) | |
1006 | puts("\n "); | |
1007 | type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); | |
1008 | printf("CPU%d(%s):%-4s MHz ", core, | |
1009 | type == TY_ITYP_VER_A7 ? "A7 " : | |
1010 | (type == TY_ITYP_VER_A53 ? "A53" : | |
79119a4d AW |
1011 | (type == TY_ITYP_VER_A57 ? "A57" : |
1012 | (type == TY_ITYP_VER_A72 ? "A72" : " "))), | |
2f78eae5 YS |
1013 | strmhz(buf, sysinfo.freq_processor[core])); |
1014 | } | |
904110c7 | 1015 | /* Display platform clock as Bus frequency. */ |
2f78eae5 | 1016 | printf("\n Bus: %-4s MHz ", |
904110c7 | 1017 | strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV)); |
d4c711f0 | 1018 | printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); |
e8297341 SX |
1019 | #ifdef CONFIG_SYS_DPAA_FMAN |
1020 | printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); | |
1021 | #endif | |
44937214 | 1022 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
3c1d218a YS |
1023 | if (soc_has_dp_ddr()) { |
1024 | printf(" DP-DDR: %-4s MT/s", | |
1025 | strmhz(buf, sysinfo.freq_ddrbus2)); | |
1026 | } | |
9f3183d2 | 1027 | #endif |
2f78eae5 YS |
1028 | puts("\n"); |
1029 | ||
9f3183d2 MH |
1030 | /* |
1031 | * Display the RCW, so that no one gets confused as to what RCW | |
d27bf906 BS |
1032 | * we're actually using for this boot. |
1033 | */ | |
1034 | puts("Reset Configuration Word (RCW):"); | |
1035 | for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { | |
9f3183d2 | 1036 | rcw = gur_in32(&gur->rcwsr[i]); |
d27bf906 | 1037 | if ((i % 4) == 0) |
9f3183d2 | 1038 | printf("\n %08x:", i * 4); |
d27bf906 BS |
1039 | printf(" %08x", rcw); |
1040 | } | |
1041 | puts("\n"); | |
1042 | ||
2f78eae5 YS |
1043 | return 0; |
1044 | } | |
1045 | #endif | |
b940ca64 | 1046 | |
8b06460e | 1047 | #ifdef CONFIG_FSL_ESDHC |
b75d8dc5 | 1048 | int cpu_mmc_init(struct bd_info *bis) |
8b06460e YL |
1049 | { |
1050 | return fsl_esdhc_mmc_init(bis); | |
1051 | } | |
1052 | #endif | |
1053 | ||
b75d8dc5 | 1054 | int cpu_eth_init(struct bd_info *bis) |
b940ca64 GR |
1055 | { |
1056 | int error = 0; | |
1057 | ||
1f55a938 | 1058 | #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) |
a2a55e51 | 1059 | error = fsl_mc_ldpaa_init(bis); |
e8297341 SX |
1060 | #endif |
1061 | #ifdef CONFIG_FMAN_ENET | |
1062 | fm_standard_init(bis); | |
b940ca64 GR |
1063 | #endif |
1064 | return error; | |
1065 | } | |
40f8dec5 | 1066 | |
84c2e044 | 1067 | int check_psci(void) |
40f8dec5 | 1068 | { |
026f30ec | 1069 | unsigned int psci_ver; |
b4017364 | 1070 | |
026f30ec YT |
1071 | psci_ver = sec_firmware_support_psci_version(); |
1072 | if (psci_ver == PSCI_INVALID_VER) | |
1073 | return 1; | |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
2db53cfe PK |
1078 | static void config_core_prefetch(void) |
1079 | { | |
1080 | char *buf = NULL; | |
1081 | char buffer[HWCONFIG_BUFFER_SIZE]; | |
1082 | const char *prefetch_arg = NULL; | |
cb14cc88 | 1083 | struct arm_smccc_res res; |
2db53cfe PK |
1084 | size_t arglen; |
1085 | unsigned int mask; | |
2db53cfe PK |
1086 | |
1087 | if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) | |
1088 | buf = buffer; | |
812ff53c PB |
1089 | else |
1090 | return; | |
2db53cfe PK |
1091 | |
1092 | prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable", | |
1093 | &arglen, buf); | |
1094 | ||
1095 | if (prefetch_arg) { | |
1096 | mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff; | |
1097 | if (mask & 0x1) { | |
1098 | printf("Core0 prefetch can't be disabled\n"); | |
1099 | return; | |
1100 | } | |
1101 | ||
1102 | #define SIP_PREFETCH_DISABLE_64 0xC200FF13 | |
cb14cc88 MW |
1103 | arm_smccc_smc(SIP_PREFETCH_DISABLE_64, mask, 0, 0, 0, 0, 0, 0, |
1104 | &res); | |
2db53cfe | 1105 | |
cb14cc88 | 1106 | if (res.a0) |
2db53cfe PK |
1107 | printf("Prefetch disable config failed for mask "); |
1108 | else | |
1109 | printf("Prefetch disable config passed for mask "); | |
1110 | printf("0x%x\n", mask); | |
1111 | } | |
1112 | } | |
1113 | ||
3499dd03 AM |
1114 | #ifdef CONFIG_PCIE_ECAM_GENERIC |
1115 | __weak void set_ecam_icids(void) | |
1116 | { | |
1117 | } | |
1118 | #endif | |
1119 | ||
026f30ec YT |
1120 | int arch_early_init_r(void) |
1121 | { | |
b4017364 | 1122 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 |
eea1cb77 PJ |
1123 | u32 svr_dev_id; |
1124 | /* | |
1125 | * erratum A009635 is valid only for LS2080A SoC and | |
1126 | * its personalitiesi | |
1127 | */ | |
a8f33034 W |
1128 | svr_dev_id = get_svr(); |
1129 | if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) | |
eea1cb77 | 1130 | erratum_a009635(); |
b4017364 | 1131 | #endif |
02fb2761 SL |
1132 | #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) |
1133 | erratum_a009942_check_cpo(); | |
1134 | #endif | |
026f30ec YT |
1135 | if (check_psci()) { |
1136 | debug("PSCI: PSCI does not exist.\n"); | |
1137 | ||
1138 | /* if PSCI does not exist, boot secondary cores here */ | |
1139 | if (fsl_layerscape_wake_seconday_cores()) | |
032d5bb4 HZ |
1140 | printf("Did not wake secondary cores\n"); |
1141 | } | |
40f8dec5 | 1142 | |
2db53cfe PK |
1143 | config_core_prefetch(); |
1144 | ||
31d34c6c ML |
1145 | #ifdef CONFIG_SYS_HAS_SERDES |
1146 | fsl_serdes_init(); | |
e8297341 | 1147 | #endif |
2e53759d PB |
1148 | #ifdef CONFIG_SYS_FSL_HAS_RGMII |
1149 | /* some dpmacs in armv8a based freescale layerscape SOCs can be | |
77b11f76 | 1150 | * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via |
2e53759d PB |
1151 | * EC*_PMUX(rgmii) bits in RCW. |
1152 | * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from | |
1153 | * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits | |
c760095a RIC |
1154 | * Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes |
1155 | * precedence over SerDes protocol. i.e. in LX2160A if we select serdes | |
1156 | * protocol that configures dpmac17 as SGMII and set the EC1_PMUX as | |
1157 | * RGMII, then the dpmac is RGMII and not SGMII. | |
2e53759d | 1158 | * |
c760095a RIC |
1159 | * Therefore, even thought fsl_rgmii_init is after fsl_serdes_init |
1160 | * function of SOC, the dpmac will be enabled as RGMII even if it was | |
1161 | * also enabled before as SGMII. If ECx_PMUX is not configured for | |
1162 | * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init(). | |
2e53759d PB |
1163 | */ |
1164 | fsl_rgmii_init(); | |
1165 | #endif | |
e8297341 | 1166 | #ifdef CONFIG_FMAN_ENET |
6eb32a03 | 1167 | #ifndef CONFIG_DM_ETH |
e8297341 | 1168 | fman_enet_init(); |
44262327 | 1169 | #endif |
6eb32a03 | 1170 | #endif |
44262327 AM |
1171 | #ifdef CONFIG_SYS_DPAA_QBMAN |
1172 | setup_qbman_portals(); | |
3499dd03 AM |
1173 | #endif |
1174 | #ifdef CONFIG_PCIE_ECAM_GENERIC | |
1175 | set_ecam_icids(); | |
31d34c6c | 1176 | #endif |
40f8dec5 YS |
1177 | return 0; |
1178 | } | |
207774b2 YS |
1179 | |
1180 | int timer_init(void) | |
1181 | { | |
1182 | u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; | |
9f3183d2 | 1183 | #ifdef CONFIG_FSL_LSCH3 |
207774b2 | 1184 | u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; |
9f3183d2 | 1185 | #endif |
0490cab5 TS |
1186 | #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ |
1187 | defined(CONFIG_ARCH_LS1028A) | |
a758177f | 1188 | u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; |
f6b96ff6 | 1189 | u32 svr_dev_id; |
a758177f | 1190 | #endif |
207774b2 YS |
1191 | #ifdef COUNTER_FREQUENCY_REAL |
1192 | unsigned long cntfrq = COUNTER_FREQUENCY_REAL; | |
1193 | ||
1194 | /* Update with accurate clock frequency */ | |
399e2bb6 YS |
1195 | if (current_el() == 3) |
1196 | asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); | |
207774b2 YS |
1197 | #endif |
1198 | ||
9f3183d2 | 1199 | #ifdef CONFIG_FSL_LSCH3 |
207774b2 YS |
1200 | /* Enable timebase for all clusters. |
1201 | * It is safe to do so even some clusters are not enabled. | |
1202 | */ | |
1203 | out_le32(cltbenr, 0xf); | |
9f3183d2 | 1204 | #endif |
207774b2 | 1205 | |
0490cab5 TS |
1206 | #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ |
1207 | defined(CONFIG_ARCH_LS1028A) | |
a758177f YC |
1208 | /* |
1209 | * In certain Layerscape SoCs, the clock for each core's | |
1210 | * has an enable bit in the PMU Physical Core Time Base Enable | |
1211 | * Register (PCTBENR), which allows the watchdog to operate. | |
1212 | */ | |
1213 | setbits_le32(pctbenr, 0xff); | |
f6b96ff6 PJ |
1214 | /* |
1215 | * For LS2080A SoC and its personalities, timer controller | |
1216 | * offset is different | |
1217 | */ | |
a8f33034 W |
1218 | svr_dev_id = get_svr(); |
1219 | if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) | |
f6b96ff6 PJ |
1220 | cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR; |
1221 | ||
a758177f YC |
1222 | #endif |
1223 | ||
207774b2 YS |
1224 | /* Enable clock for timer |
1225 | * This is a global setting. | |
1226 | */ | |
1227 | out_le32(cntcr, 0x1); | |
1228 | ||
1229 | return 0; | |
1230 | } | |
05d2e21b | 1231 | |
78d57842 AG |
1232 | __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; |
1233 | ||
35b65dd8 | 1234 | void __efi_runtime reset_cpu(void) |
05d2e21b | 1235 | { |
3a187cff | 1236 | #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) |
d31f3a1b MA |
1237 | /* clear the RST_REQ_MSK and SW_RST_REQ */ |
1238 | out_le32(rstcr, 0x0); | |
1239 | ||
1240 | /* initiate the sw reset request */ | |
1241 | out_le32(rstcr, 0x1); | |
4909b89e | 1242 | #else |
d31f3a1b MA |
1243 | u32 val; |
1244 | ||
05d2e21b | 1245 | /* Raise RESET_REQ_B */ |
9f3183d2 | 1246 | val = scfg_in32(rstcr); |
05d2e21b | 1247 | val |= 0x02; |
9f3183d2 | 1248 | scfg_out32(rstcr, val); |
4909b89e | 1249 | #endif |
05d2e21b | 1250 | } |
c0492141 | 1251 | |
28f9393b | 1252 | #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET) |
78d57842 AG |
1253 | |
1254 | void __efi_runtime EFIAPI efi_reset_system( | |
1255 | enum efi_reset_type reset_type, | |
1256 | efi_status_t reset_status, | |
1257 | unsigned long data_size, void *reset_data) | |
1258 | { | |
1259 | switch (reset_type) { | |
1260 | case EFI_RESET_COLD: | |
1261 | case EFI_RESET_WARM: | |
482fc90c | 1262 | case EFI_RESET_PLATFORM_SPECIFIC: |
35b65dd8 | 1263 | reset_cpu(); |
78d57842 AG |
1264 | break; |
1265 | case EFI_RESET_SHUTDOWN: | |
1266 | /* Nothing we can do */ | |
1267 | break; | |
1268 | } | |
1269 | ||
1270 | while (1) { } | |
1271 | } | |
1272 | ||
22c793e6 | 1273 | efi_status_t efi_reset_system_init(void) |
78d57842 | 1274 | { |
22c793e6 | 1275 | return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr)); |
78d57842 AG |
1276 | } |
1277 | ||
1278 | #endif | |
1279 | ||
e9303a41 YS |
1280 | /* |
1281 | * Calculate reserved memory with given memory bank | |
1282 | * Return aligned memory size on success | |
1283 | * Return (ram_size + needed size) for failure | |
1284 | */ | |
c0492141 YS |
1285 | phys_size_t board_reserve_ram_top(phys_size_t ram_size) |
1286 | { | |
1287 | phys_size_t ram_top = ram_size; | |
1288 | ||
1f55a938 | 1289 | #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) |
e9303a41 YS |
1290 | ram_top = mc_get_dram_block_size(); |
1291 | if (ram_top > ram_size) | |
1292 | return ram_size + ram_top; | |
1293 | ||
1294 | ram_top = ram_size - ram_top; | |
36cc0de0 | 1295 | /* The start address of MC reserved memory needs to be aligned. */ |
c0492141 YS |
1296 | ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); |
1297 | #endif | |
1298 | ||
36cc0de0 YS |
1299 | return ram_size - ram_top; |
1300 | } | |
1301 | ||
1302 | phys_size_t get_effective_memsize(void) | |
1303 | { | |
1304 | phys_size_t ea_size, rem = 0; | |
1305 | ||
1306 | /* | |
1307 | * For ARMv8 SoCs, DDR memory is split into two or three regions. The | |
710d0cd7 SG |
1308 | * first region is 2GB space at 0x8000_0000. Secure memory needs to |
1309 | * allocated from first region. If the memory extends to the second | |
1310 | * region (or the third region if applicable), Management Complex (MC) | |
1311 | * memory should be put into the highest region, i.e. the end of DDR | |
1312 | * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so | |
1313 | * U-Boot doesn't relocate itself into higher address. Should DDR be | |
1314 | * configured to skip the first region, this function needs to be | |
1315 | * adjusted. | |
36cc0de0 YS |
1316 | */ |
1317 | if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { | |
1318 | ea_size = CONFIG_MAX_MEM_MAPPED; | |
1319 | rem = gd->ram_size - ea_size; | |
1320 | } else { | |
1321 | ea_size = gd->ram_size; | |
1322 | } | |
1323 | ||
1324 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE | |
1325 | /* Check if we have enough space for secure memory */ | |
710d0cd7 SG |
1326 | if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) |
1327 | ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; | |
1328 | else | |
1329 | printf("Error: No enough space for secure memory.\n"); | |
36cc0de0 YS |
1330 | #endif |
1331 | /* Check if we have enough memory for MC */ | |
1332 | if (rem < board_reserve_ram_top(rem)) { | |
1333 | /* Not enough memory in high region to reserve */ | |
e9303a41 YS |
1334 | if (ea_size > board_reserve_ram_top(ea_size)) |
1335 | ea_size -= board_reserve_ram_top(ea_size); | |
36cc0de0 YS |
1336 | else |
1337 | printf("Error: No enough space for reserved memory.\n"); | |
1338 | } | |
1339 | ||
1340 | return ea_size; | |
1341 | } | |
1342 | ||
681d489e RB |
1343 | #ifdef CONFIG_TFABOOT |
1344 | phys_size_t tfa_get_dram_size(void) | |
1345 | { | |
cb14cc88 | 1346 | struct arm_smccc_res res; |
681d489e | 1347 | |
cb14cc88 MW |
1348 | arm_smccc_smc(SMC_DRAM_BANK_INFO, -1, 0, 0, 0, 0, 0, 0, &res); |
1349 | if (res.a0) | |
681d489e RB |
1350 | return 0; |
1351 | ||
cb14cc88 | 1352 | return res.a1; |
681d489e RB |
1353 | } |
1354 | ||
1355 | static int tfa_dram_init_banksize(void) | |
1356 | { | |
1357 | int i = 0, ret = 0; | |
681d489e | 1358 | phys_size_t dram_size = tfa_get_dram_size(); |
cb14cc88 | 1359 | struct arm_smccc_res res; |
681d489e RB |
1360 | |
1361 | debug("dram_size %llx\n", dram_size); | |
1362 | ||
1363 | if (!dram_size) | |
1364 | return -EINVAL; | |
1365 | ||
1366 | do { | |
cb14cc88 MW |
1367 | arm_smccc_smc(SMC_DRAM_BANK_INFO, i, 0, 0, 0, 0, 0, 0, &res); |
1368 | if (res.a0) { | |
681d489e RB |
1369 | ret = -EINVAL; |
1370 | break; | |
1371 | } | |
1372 | ||
cb14cc88 MW |
1373 | debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2); |
1374 | gd->bd->bi_dram[i].start = res.a1; | |
1375 | gd->bd->bi_dram[i].size = res.a2; | |
681d489e RB |
1376 | |
1377 | dram_size -= gd->bd->bi_dram[i].size; | |
1378 | ||
1379 | i++; | |
1380 | } while (dram_size); | |
1381 | ||
1382 | if (i > 0) | |
1383 | ret = 0; | |
1384 | ||
6ebd4883 | 1385 | #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) |
681d489e RB |
1386 | /* Assign memory for MC */ |
1387 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
1388 | if (gd->bd->bi_dram[2].size >= | |
1389 | board_reserve_ram_top(gd->bd->bi_dram[2].size)) { | |
1390 | gd->arch.resv_ram = gd->bd->bi_dram[2].start + | |
1391 | gd->bd->bi_dram[2].size - | |
1392 | board_reserve_ram_top(gd->bd->bi_dram[2].size); | |
1393 | } else | |
1394 | #endif | |
1395 | { | |
1396 | if (gd->bd->bi_dram[1].size >= | |
1397 | board_reserve_ram_top(gd->bd->bi_dram[1].size)) { | |
1398 | gd->arch.resv_ram = gd->bd->bi_dram[1].start + | |
1399 | gd->bd->bi_dram[1].size - | |
1400 | board_reserve_ram_top(gd->bd->bi_dram[1].size); | |
1401 | } else if (gd->bd->bi_dram[0].size > | |
1402 | board_reserve_ram_top(gd->bd->bi_dram[0].size)) { | |
1403 | gd->arch.resv_ram = gd->bd->bi_dram[0].start + | |
1404 | gd->bd->bi_dram[0].size - | |
1405 | board_reserve_ram_top(gd->bd->bi_dram[0].size); | |
1406 | } | |
1407 | } | |
6ebd4883 | 1408 | #endif /* CONFIG_RESV_RAM */ |
681d489e RB |
1409 | |
1410 | return ret; | |
1411 | } | |
1412 | #endif | |
1413 | ||
76b00aca | 1414 | int dram_init_banksize(void) |
36cc0de0 YS |
1415 | { |
1416 | #ifdef CONFIG_SYS_DP_DDR_BASE_PHY | |
1417 | phys_size_t dp_ddr_size; | |
1418 | #endif | |
1419 | ||
681d489e RB |
1420 | #ifdef CONFIG_TFABOOT |
1421 | if (!tfa_dram_init_banksize()) | |
1422 | return 0; | |
1423 | #endif | |
36cc0de0 YS |
1424 | /* |
1425 | * gd->ram_size has the total size of DDR memory, less reserved secure | |
1426 | * memory. The DDR extends from low region to high region(s) presuming | |
1427 | * no hole is created with DDR configuration. gd->arch.secure_ram tracks | |
1428 | * the location of secure memory. gd->arch.resv_ram tracks the location | |
7eb40f0f YS |
1429 | * of reserved memory for Management Complex (MC). Because gd->ram_size |
1430 | * is reduced by this function if secure memory is reserved, checking | |
1431 | * gd->arch.secure_ram should be done to avoid running it repeatedly. | |
36cc0de0 | 1432 | */ |
7eb40f0f YS |
1433 | |
1434 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE | |
1435 | if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { | |
1436 | debug("No need to run again, skip %s\n", __func__); | |
1437 | ||
1438 | return 0; | |
1439 | } | |
1440 | #endif | |
1441 | ||
36cc0de0 YS |
1442 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
1443 | if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { | |
1444 | gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; | |
1445 | gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; | |
1446 | gd->bd->bi_dram[1].size = gd->ram_size - | |
1447 | CONFIG_SYS_DDR_BLOCK1_SIZE; | |
1448 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
1449 | if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { | |
1450 | gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; | |
1451 | gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - | |
1452 | CONFIG_SYS_DDR_BLOCK2_SIZE; | |
1453 | gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; | |
1454 | } | |
1455 | #endif | |
1456 | } else { | |
1457 | gd->bd->bi_dram[0].size = gd->ram_size; | |
1458 | } | |
1459 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE | |
710d0cd7 SG |
1460 | if (gd->bd->bi_dram[0].size > |
1461 | CONFIG_SYS_MEM_RESERVE_SECURE) { | |
1462 | gd->bd->bi_dram[0].size -= | |
1463 | CONFIG_SYS_MEM_RESERVE_SECURE; | |
1464 | gd->arch.secure_ram = gd->bd->bi_dram[0].start + | |
1465 | gd->bd->bi_dram[0].size; | |
36cc0de0 YS |
1466 | gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; |
1467 | gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; | |
36cc0de0 YS |
1468 | } |
1469 | #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ | |
1470 | ||
6ebd4883 | 1471 | #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) |
36cc0de0 YS |
1472 | /* Assign memory for MC */ |
1473 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
1474 | if (gd->bd->bi_dram[2].size >= | |
1475 | board_reserve_ram_top(gd->bd->bi_dram[2].size)) { | |
1476 | gd->arch.resv_ram = gd->bd->bi_dram[2].start + | |
1477 | gd->bd->bi_dram[2].size - | |
1478 | board_reserve_ram_top(gd->bd->bi_dram[2].size); | |
1479 | } else | |
1480 | #endif | |
1481 | { | |
1482 | if (gd->bd->bi_dram[1].size >= | |
1483 | board_reserve_ram_top(gd->bd->bi_dram[1].size)) { | |
1484 | gd->arch.resv_ram = gd->bd->bi_dram[1].start + | |
1485 | gd->bd->bi_dram[1].size - | |
1486 | board_reserve_ram_top(gd->bd->bi_dram[1].size); | |
1487 | } else if (gd->bd->bi_dram[0].size > | |
1488 | board_reserve_ram_top(gd->bd->bi_dram[0].size)) { | |
1489 | gd->arch.resv_ram = gd->bd->bi_dram[0].start + | |
1490 | gd->bd->bi_dram[0].size - | |
1491 | board_reserve_ram_top(gd->bd->bi_dram[0].size); | |
1492 | } | |
1493 | } | |
6ebd4883 | 1494 | #endif /* CONFIG_RESV_RAM */ |
36cc0de0 YS |
1495 | |
1496 | #ifdef CONFIG_SYS_DP_DDR_BASE_PHY | |
1497 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
1498 | #error "This SoC shouldn't have DP DDR" | |
1499 | #endif | |
1500 | if (soc_has_dp_ddr()) { | |
1501 | /* initialize DP-DDR here */ | |
1502 | puts("DP-DDR: "); | |
1503 | /* | |
1504 | * DDR controller use 0 as the base address for binding. | |
1505 | * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. | |
1506 | */ | |
1507 | dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, | |
1508 | CONFIG_DP_DDR_CTRL, | |
1509 | CONFIG_DP_DDR_NUM_CTRLS, | |
1510 | CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, | |
1511 | NULL, NULL, NULL); | |
1512 | if (dp_ddr_size) { | |
1513 | gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; | |
1514 | gd->bd->bi_dram[2].size = dp_ddr_size; | |
1515 | } else { | |
1516 | puts("Not detected"); | |
1517 | } | |
1518 | } | |
1519 | #endif | |
76b00aca | 1520 | |
7eb40f0f YS |
1521 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
1522 | debug("%s is called. gd->ram_size is reduced to %lu\n", | |
1523 | __func__, (ulong)gd->ram_size); | |
1524 | #endif | |
1525 | ||
76b00aca | 1526 | return 0; |
36cc0de0 YS |
1527 | } |
1528 | ||
9b5e6396 | 1529 | #if CONFIG_IS_ENABLED(EFI_LOADER) |
36cc0de0 YS |
1530 | void efi_add_known_memory(void) |
1531 | { | |
1532 | int i; | |
714497e3 | 1533 | phys_addr_t ram_start; |
36cc0de0 | 1534 | phys_size_t ram_size; |
36cc0de0 YS |
1535 | |
1536 | /* Add RAM */ | |
1537 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
1538 | #ifdef CONFIG_SYS_DP_DDR_BASE_PHY | |
1539 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
1540 | #error "This SoC shouldn't have DP DDR" | |
1541 | #endif | |
1542 | if (i == 2) | |
1543 | continue; /* skip DP-DDR */ | |
1544 | #endif | |
1545 | ram_start = gd->bd->bi_dram[i].start; | |
1546 | ram_size = gd->bd->bi_dram[i].size; | |
1547 | #ifdef CONFIG_RESV_RAM | |
1548 | if (gd->arch.resv_ram >= ram_start && | |
1549 | gd->arch.resv_ram < ram_start + ram_size) | |
1550 | ram_size = gd->arch.resv_ram - ram_start; | |
1551 | #endif | |
714497e3 MW |
1552 | efi_add_memory_map(ram_start, ram_size, |
1553 | EFI_CONVENTIONAL_MEMORY); | |
36cc0de0 | 1554 | } |
c0492141 | 1555 | } |
36cc0de0 | 1556 | #endif |
4961eafc YS |
1557 | |
1558 | /* | |
1559 | * Before DDR size is known, early MMU table have DDR mapped as device memory | |
1560 | * to avoid speculative access. To relocate U-Boot to DDR, "normal memory" | |
1561 | * needs to be set for these mappings. | |
1562 | * If a special case configures DDR with holes in the mapping, the holes need | |
1563 | * to be marked as invalid. This is not implemented in this function. | |
1564 | */ | |
1565 | void update_early_mmu_table(void) | |
1566 | { | |
1567 | if (!gd->arch.tlb_addr) | |
1568 | return; | |
1569 | ||
1570 | if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { | |
1571 | mmu_change_region_attr( | |
1572 | CONFIG_SYS_SDRAM_BASE, | |
1573 | gd->ram_size, | |
1574 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
1575 | PTE_BLOCK_OUTER_SHARE | | |
1576 | PTE_BLOCK_NS | | |
1577 | PTE_TYPE_VALID); | |
1578 | } else { | |
1579 | mmu_change_region_attr( | |
1580 | CONFIG_SYS_SDRAM_BASE, | |
1581 | CONFIG_SYS_DDR_BLOCK1_SIZE, | |
1582 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
1583 | PTE_BLOCK_OUTER_SHARE | | |
1584 | PTE_BLOCK_NS | | |
1585 | PTE_TYPE_VALID); | |
1586 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
1587 | #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE | |
1588 | #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" | |
1589 | #endif | |
1590 | if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > | |
1591 | CONFIG_SYS_DDR_BLOCK2_SIZE) { | |
1592 | mmu_change_region_attr( | |
1593 | CONFIG_SYS_DDR_BLOCK2_BASE, | |
1594 | CONFIG_SYS_DDR_BLOCK2_SIZE, | |
1595 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
1596 | PTE_BLOCK_OUTER_SHARE | | |
1597 | PTE_BLOCK_NS | | |
1598 | PTE_TYPE_VALID); | |
1599 | mmu_change_region_attr( | |
1600 | CONFIG_SYS_DDR_BLOCK3_BASE, | |
1601 | gd->ram_size - | |
1602 | CONFIG_SYS_DDR_BLOCK1_SIZE - | |
1603 | CONFIG_SYS_DDR_BLOCK2_SIZE, | |
1604 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
1605 | PTE_BLOCK_OUTER_SHARE | | |
1606 | PTE_BLOCK_NS | | |
1607 | PTE_TYPE_VALID); | |
1608 | } else | |
1609 | #endif | |
1610 | { | |
1611 | mmu_change_region_attr( | |
1612 | CONFIG_SYS_DDR_BLOCK2_BASE, | |
1613 | gd->ram_size - | |
1614 | CONFIG_SYS_DDR_BLOCK1_SIZE, | |
1615 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
1616 | PTE_BLOCK_OUTER_SHARE | | |
1617 | PTE_BLOCK_NS | | |
1618 | PTE_TYPE_VALID); | |
1619 | } | |
1620 | } | |
1621 | } | |
1622 | ||
1623 | __weak int dram_init(void) | |
1624 | { | |
f9147d63 | 1625 | #ifdef CONFIG_SYS_FSL_DDR |
3eace37e | 1626 | fsl_initdram(); |
535d76a1 RB |
1627 | #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ |
1628 | defined(CONFIG_SPL_BUILD) | |
4961eafc YS |
1629 | /* This will break-before-make MMU for DDR */ |
1630 | update_early_mmu_table(); | |
f9147d63 | 1631 | #endif |
4961eafc YS |
1632 | #endif |
1633 | ||
1634 | return 0; | |
1635 | } | |
0d9d557d AM |
1636 | |
1637 | #ifdef CONFIG_ARCH_MISC_INIT | |
1638 | __weak int serdes_misc_init(void) | |
1639 | { | |
1640 | return 0; | |
1641 | } | |
1642 | ||
1643 | int arch_misc_init(void) | |
1644 | { | |
8976556a GJ |
1645 | if (IS_ENABLED(CONFIG_FSL_CAAM)) { |
1646 | struct udevice *dev; | |
1647 | int ret; | |
1648 | ||
1649 | ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); | |
1650 | if (ret) | |
cda8f873 | 1651 | printf("Failed to initialize caam_jr: %d\n", ret); |
8976556a | 1652 | } |
0d9d557d AM |
1653 | serdes_misc_init(); |
1654 | ||
1655 | return 0; | |
1656 | } | |
1657 | #endif |