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Commit | Line | Data |
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2f78eae5 | 1 | /* |
9f3183d2 | 2 | * Copyright 2014-2015 Freescale Semiconductor, Inc. |
2f78eae5 YS |
3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/io.h> | |
1221ce45 | 9 | #include <linux/errno.h> |
2f78eae5 YS |
10 | #include <asm/system.h> |
11 | #include <asm/armv8/mmu.h> | |
12 | #include <asm/io.h> | |
9f3183d2 MH |
13 | #include <asm/arch/fsl_serdes.h> |
14 | #include <asm/arch/soc.h> | |
15 | #include <asm/arch/cpu.h> | |
16 | #include <asm/arch/speed.h> | |
17 | #ifdef CONFIG_MP | |
18 | #include <asm/arch/mp.h> | |
19 | #endif | |
78d57842 | 20 | #include <efi_loader.h> |
9f3183d2 | 21 | #include <fm_eth.h> |
7b3bd9a7 | 22 | #include <fsl-mc/fsl_mc.h> |
8b06460e YL |
23 | #ifdef CONFIG_FSL_ESDHC |
24 | #include <fsl_esdhc.h> | |
25 | #endif | |
032d5bb4 HZ |
26 | #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT |
27 | #include <asm/armv8/sec_firmware.h> | |
28 | #endif | |
02fb2761 SL |
29 | #ifdef CONFIG_SYS_FSL_DDR |
30 | #include <fsl_ddr.h> | |
31 | #endif | |
2f78eae5 YS |
32 | |
33 | DECLARE_GLOBAL_DATA_PTR; | |
34 | ||
5ad5823d | 35 | struct mm_region *mem_map = early_map; |
7985cdf7 | 36 | |
22629665 PK |
37 | void cpu_name(char *name) |
38 | { | |
39 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
40 | unsigned int i, svr, ver; | |
41 | ||
9f3183d2 | 42 | svr = gur_in32(&gur->svr); |
22629665 PK |
43 | ver = SVR_SOC_VER(svr); |
44 | ||
45 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) | |
46 | if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { | |
47 | strcpy(name, cpu_type_list[i].name); | |
48 | ||
49 | if (IS_E_PROCESSOR(svr)) | |
50 | strcat(name, "E"); | |
5d1a7a9d WS |
51 | |
52 | sprintf(name + strlen(name), " Rev%d.%d", | |
53 | SVR_MAJ(svr), SVR_MIN(svr)); | |
22629665 PK |
54 | break; |
55 | } | |
56 | ||
57 | if (i == ARRAY_SIZE(cpu_type_list)) | |
58 | strcpy(name, "unknown"); | |
59 | } | |
60 | ||
2f78eae5 | 61 | #ifndef CONFIG_SYS_DCACHE_OFF |
99799220 AW |
62 | /* |
63 | * To start MMU before DDR is available, we create MMU table in SRAM. | |
64 | * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three | |
65 | * levels of translation tables here to cover 40-bit address space. | |
66 | * We use 4KB granule size, with 40 bits physical address, T0SZ=24 | |
5ad5823d YS |
67 | * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. |
68 | * Note, the debug print in cache_v8.c is not usable for debugging | |
69 | * these early MMU tables because UART is not yet available. | |
99799220 AW |
70 | */ |
71 | static inline void early_mmu_setup(void) | |
72 | { | |
5ad5823d | 73 | unsigned int el = current_el(); |
99799220 | 74 | |
5ad5823d YS |
75 | /* global data is already setup, no allocation yet */ |
76 | gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; | |
77 | gd->arch.tlb_fillptr = gd->arch.tlb_addr; | |
78 | gd->arch.tlb_size = EARLY_PGTABLE_SIZE; | |
99799220 | 79 | |
5ad5823d YS |
80 | /* Create early page tables */ |
81 | setup_pgtables(); | |
9f3183d2 | 82 | |
5ad5823d YS |
83 | /* point TTBR to the new table */ |
84 | set_ttbr_tcr_mair(el, gd->arch.tlb_addr, | |
85 | get_tcr(el, NULL, NULL) & | |
86 | ~(TCR_ORGN_MASK | TCR_IRGN_MASK), | |
9f3183d2 | 87 | MEMORY_ATTRIBUTES); |
c107c0c0 | 88 | |
5ad5823d | 89 | set_sctlr(get_sctlr() | CR_M); |
c107c0c0 | 90 | } |
c107c0c0 | 91 | |
2f78eae5 | 92 | /* |
99799220 AW |
93 | * The final tables look similar to early tables, but different in detail. |
94 | * These tables are in DRAM. Sub tables are added to enable cache for | |
95 | * QBMan and OCRAM. | |
96 | * | |
e61a7534 YS |
97 | * Put the MMU table in secure memory if gd->arch.secure_ram is valid. |
98 | * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. | |
2f78eae5 YS |
99 | */ |
100 | static inline void final_mmu_setup(void) | |
101 | { | |
5ad5823d | 102 | u64 tlb_addr_save = gd->arch.tlb_addr; |
c107c0c0 | 103 | unsigned int el = current_el(); |
5ad5823d | 104 | int index; |
2f78eae5 | 105 | |
5ad5823d | 106 | mem_map = final_map; |
2f78eae5 | 107 | |
24f55496 YS |
108 | /* Update mapping for DDR to actual size */ |
109 | for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) { | |
110 | /* | |
111 | * Find the entry for DDR mapping and update the address and | |
112 | * size. Zero-sized mapping will be skipped when creating MMU | |
113 | * table. | |
114 | */ | |
115 | switch (final_map[index].virt) { | |
116 | case CONFIG_SYS_FSL_DRAM_BASE1: | |
117 | final_map[index].virt = gd->bd->bi_dram[0].start; | |
118 | final_map[index].phys = gd->bd->bi_dram[0].start; | |
119 | final_map[index].size = gd->bd->bi_dram[0].size; | |
120 | break; | |
121 | #ifdef CONFIG_SYS_FSL_DRAM_BASE2 | |
122 | case CONFIG_SYS_FSL_DRAM_BASE2: | |
123 | #if (CONFIG_NR_DRAM_BANKS >= 2) | |
124 | final_map[index].virt = gd->bd->bi_dram[1].start; | |
125 | final_map[index].phys = gd->bd->bi_dram[1].start; | |
126 | final_map[index].size = gd->bd->bi_dram[1].size; | |
127 | #else | |
128 | final_map[index].size = 0; | |
129 | #endif | |
130 | break; | |
131 | #endif | |
132 | #ifdef CONFIG_SYS_FSL_DRAM_BASE3 | |
133 | case CONFIG_SYS_FSL_DRAM_BASE3: | |
134 | #if (CONFIG_NR_DRAM_BANKS >= 3) | |
135 | final_map[index].virt = gd->bd->bi_dram[2].start; | |
136 | final_map[index].phys = gd->bd->bi_dram[2].start; | |
137 | final_map[index].size = gd->bd->bi_dram[2].size; | |
138 | #else | |
139 | final_map[index].size = 0; | |
140 | #endif | |
141 | break; | |
142 | #endif | |
143 | default: | |
144 | break; | |
145 | } | |
146 | } | |
147 | ||
c107c0c0 | 148 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
5ad5823d YS |
149 | if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { |
150 | if (el == 3) { | |
151 | /* | |
152 | * Only use gd->arch.secure_ram if the address is | |
153 | * recalculated. Align to 4KB for MMU table. | |
154 | */ | |
155 | /* put page tables in secure ram */ | |
156 | index = ARRAY_SIZE(final_map) - 2; | |
157 | gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; | |
158 | final_map[index].virt = gd->arch.secure_ram & ~0x3; | |
159 | final_map[index].phys = final_map[index].virt; | |
160 | final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; | |
161 | final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; | |
e61a7534 | 162 | gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; |
5ad5823d | 163 | tlb_addr_save = gd->arch.tlb_addr; |
c107c0c0 | 164 | } else { |
5ad5823d YS |
165 | /* Use allocated (board_f.c) memory for TLB */ |
166 | tlb_addr_save = gd->arch.tlb_allocated; | |
167 | gd->arch.tlb_addr = tlb_addr_save; | |
c107c0c0 YS |
168 | } |
169 | } | |
170 | #endif | |
2f78eae5 | 171 | |
5ad5823d YS |
172 | /* Reset the fill ptr */ |
173 | gd->arch.tlb_fillptr = tlb_addr_save; | |
174 | ||
175 | /* Create normal system page tables */ | |
176 | setup_pgtables(); | |
177 | ||
178 | /* Create emergency page tables */ | |
179 | gd->arch.tlb_addr = gd->arch.tlb_fillptr; | |
180 | gd->arch.tlb_emerg = gd->arch.tlb_addr; | |
181 | setup_pgtables(); | |
182 | gd->arch.tlb_addr = tlb_addr_save; | |
183 | ||
a045a0c3 YS |
184 | /* Disable cache and MMU */ |
185 | dcache_disable(); /* TLBs are invalidated */ | |
186 | invalidate_icache_all(); | |
2f78eae5 YS |
187 | |
188 | /* point TTBR to the new table */ | |
5ad5823d | 189 | set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), |
db14f11d | 190 | MEMORY_ATTRIBUTES); |
a045a0c3 | 191 | |
ed7a3943 | 192 | set_sctlr(get_sctlr() | CR_M); |
2f78eae5 YS |
193 | } |
194 | ||
c05016ab AG |
195 | u64 get_page_table_size(void) |
196 | { | |
197 | return 0x10000; | |
198 | } | |
199 | ||
2f78eae5 YS |
200 | int arch_cpu_init(void) |
201 | { | |
202 | icache_enable(); | |
203 | __asm_invalidate_dcache_all(); | |
204 | __asm_invalidate_tlb_all(); | |
205 | early_mmu_setup(); | |
206 | set_sctlr(get_sctlr() | CR_C); | |
207 | return 0; | |
208 | } | |
209 | ||
85cdf38e HZ |
210 | void mmu_setup(void) |
211 | { | |
212 | final_mmu_setup(); | |
213 | } | |
214 | ||
2f78eae5 | 215 | /* |
85cdf38e HZ |
216 | * This function is called from common/board_r.c. |
217 | * It recreates MMU table in main memory. | |
2f78eae5 YS |
218 | */ |
219 | void enable_caches(void) | |
220 | { | |
85cdf38e | 221 | mmu_setup(); |
2f78eae5 | 222 | __asm_invalidate_tlb_all(); |
85cdf38e HZ |
223 | icache_enable(); |
224 | dcache_enable(); | |
2f78eae5 YS |
225 | } |
226 | #endif | |
227 | ||
e87c673c | 228 | u32 initiator_type(u32 cluster, int init_id) |
2f78eae5 YS |
229 | { |
230 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
231 | u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; | |
9f3183d2 | 232 | u32 type = 0; |
2f78eae5 | 233 | |
9f3183d2 | 234 | type = gur_in32(&gur->tp_ityp[idx]); |
2f78eae5 YS |
235 | if (type & TP_ITYP_AV) |
236 | return type; | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
ef9a5fd8 YS |
241 | u32 cpu_pos_mask(void) |
242 | { | |
243 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
244 | int i = 0; | |
245 | u32 cluster, type, mask = 0; | |
246 | ||
247 | do { | |
248 | int j; | |
249 | ||
250 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
251 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { | |
252 | type = initiator_type(cluster, j); | |
253 | if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)) | |
254 | mask |= 1 << (i * TP_INIT_PER_CLUSTER + j); | |
255 | } | |
256 | i++; | |
257 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); | |
258 | ||
259 | return mask; | |
260 | } | |
261 | ||
2f78eae5 YS |
262 | u32 cpu_mask(void) |
263 | { | |
264 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
265 | int i = 0, count = 0; | |
266 | u32 cluster, type, mask = 0; | |
267 | ||
268 | do { | |
269 | int j; | |
9f3183d2 MH |
270 | |
271 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
2f78eae5 YS |
272 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
273 | type = initiator_type(cluster, j); | |
274 | if (type) { | |
275 | if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) | |
276 | mask |= 1 << count; | |
277 | count++; | |
278 | } | |
279 | } | |
280 | i++; | |
9f3183d2 | 281 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); |
2f78eae5 YS |
282 | |
283 | return mask; | |
284 | } | |
285 | ||
286 | /* | |
287 | * Return the number of cores on this SOC. | |
288 | */ | |
289 | int cpu_numcores(void) | |
290 | { | |
291 | return hweight32(cpu_mask()); | |
292 | } | |
293 | ||
294 | int fsl_qoriq_core_to_cluster(unsigned int core) | |
295 | { | |
296 | struct ccsr_gur __iomem *gur = | |
297 | (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
298 | int i = 0, count = 0; | |
299 | u32 cluster; | |
300 | ||
301 | do { | |
302 | int j; | |
9f3183d2 MH |
303 | |
304 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
2f78eae5 YS |
305 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
306 | if (initiator_type(cluster, j)) { | |
307 | if (count == core) | |
308 | return i; | |
309 | count++; | |
310 | } | |
311 | } | |
312 | i++; | |
9f3183d2 | 313 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); |
2f78eae5 YS |
314 | |
315 | return -1; /* cannot identify the cluster */ | |
316 | } | |
317 | ||
318 | u32 fsl_qoriq_core_to_type(unsigned int core) | |
319 | { | |
320 | struct ccsr_gur __iomem *gur = | |
321 | (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
322 | int i = 0, count = 0; | |
323 | u32 cluster, type; | |
324 | ||
325 | do { | |
326 | int j; | |
9f3183d2 MH |
327 | |
328 | cluster = gur_in32(&gur->tp_cluster[i].lower); | |
2f78eae5 YS |
329 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { |
330 | type = initiator_type(cluster, j); | |
331 | if (type) { | |
332 | if (count == core) | |
333 | return type; | |
334 | count++; | |
335 | } | |
336 | } | |
337 | i++; | |
9f3183d2 | 338 | } while ((cluster & TP_CLUSTER_EOC) == 0x0); |
2f78eae5 YS |
339 | |
340 | return -1; /* cannot identify the cluster */ | |
341 | } | |
342 | ||
f6a70b3a | 343 | #ifndef CONFIG_FSL_LSCH3 |
6fb522dc SD |
344 | uint get_svr(void) |
345 | { | |
346 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
347 | ||
348 | return gur_in32(&gur->svr); | |
349 | } | |
f6a70b3a | 350 | #endif |
6fb522dc | 351 | |
2f78eae5 YS |
352 | #ifdef CONFIG_DISPLAY_CPUINFO |
353 | int print_cpuinfo(void) | |
354 | { | |
d27bf906 | 355 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
2f78eae5 YS |
356 | struct sys_info sysinfo; |
357 | char buf[32]; | |
358 | unsigned int i, core; | |
3c1d218a | 359 | u32 type, rcw, svr = gur_in32(&gur->svr); |
2f78eae5 | 360 | |
22629665 PK |
361 | puts("SoC: "); |
362 | ||
363 | cpu_name(buf); | |
3c1d218a | 364 | printf(" %s (0x%x)\n", buf, svr); |
22629665 | 365 | memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); |
2f78eae5 YS |
366 | get_sys_info(&sysinfo); |
367 | puts("Clock Configuration:"); | |
368 | for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { | |
369 | if (!(i % 3)) | |
370 | puts("\n "); | |
371 | type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); | |
372 | printf("CPU%d(%s):%-4s MHz ", core, | |
373 | type == TY_ITYP_VER_A7 ? "A7 " : | |
374 | (type == TY_ITYP_VER_A53 ? "A53" : | |
79119a4d AW |
375 | (type == TY_ITYP_VER_A57 ? "A57" : |
376 | (type == TY_ITYP_VER_A72 ? "A72" : " "))), | |
2f78eae5 YS |
377 | strmhz(buf, sysinfo.freq_processor[core])); |
378 | } | |
904110c7 | 379 | /* Display platform clock as Bus frequency. */ |
2f78eae5 | 380 | printf("\n Bus: %-4s MHz ", |
904110c7 | 381 | strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV)); |
d4c711f0 | 382 | printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); |
e8297341 SX |
383 | #ifdef CONFIG_SYS_DPAA_FMAN |
384 | printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); | |
385 | #endif | |
44937214 | 386 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
3c1d218a YS |
387 | if (soc_has_dp_ddr()) { |
388 | printf(" DP-DDR: %-4s MT/s", | |
389 | strmhz(buf, sysinfo.freq_ddrbus2)); | |
390 | } | |
9f3183d2 | 391 | #endif |
2f78eae5 YS |
392 | puts("\n"); |
393 | ||
9f3183d2 MH |
394 | /* |
395 | * Display the RCW, so that no one gets confused as to what RCW | |
d27bf906 BS |
396 | * we're actually using for this boot. |
397 | */ | |
398 | puts("Reset Configuration Word (RCW):"); | |
399 | for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { | |
9f3183d2 | 400 | rcw = gur_in32(&gur->rcwsr[i]); |
d27bf906 | 401 | if ((i % 4) == 0) |
9f3183d2 | 402 | printf("\n %08x:", i * 4); |
d27bf906 BS |
403 | printf(" %08x", rcw); |
404 | } | |
405 | puts("\n"); | |
406 | ||
2f78eae5 YS |
407 | return 0; |
408 | } | |
409 | #endif | |
b940ca64 | 410 | |
8b06460e YL |
411 | #ifdef CONFIG_FSL_ESDHC |
412 | int cpu_mmc_init(bd_t *bis) | |
413 | { | |
414 | return fsl_esdhc_mmc_init(bis); | |
415 | } | |
416 | #endif | |
417 | ||
b940ca64 GR |
418 | int cpu_eth_init(bd_t *bis) |
419 | { | |
420 | int error = 0; | |
421 | ||
422 | #ifdef CONFIG_FSL_MC_ENET | |
a2a55e51 | 423 | error = fsl_mc_ldpaa_init(bis); |
e8297341 SX |
424 | #endif |
425 | #ifdef CONFIG_FMAN_ENET | |
426 | fm_standard_init(bis); | |
b940ca64 GR |
427 | #endif |
428 | return error; | |
429 | } | |
40f8dec5 | 430 | |
40f8dec5 YS |
431 | int arch_early_init_r(void) |
432 | { | |
9f3183d2 MH |
433 | #ifdef CONFIG_MP |
434 | int rv = 1; | |
032d5bb4 | 435 | u32 psci_ver = 0xffffffff; |
b4017364 PK |
436 | #endif |
437 | ||
438 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 | |
eea1cb77 PJ |
439 | u32 svr_dev_id; |
440 | /* | |
441 | * erratum A009635 is valid only for LS2080A SoC and | |
442 | * its personalitiesi | |
443 | */ | |
444 | svr_dev_id = get_svr() >> 16; | |
445 | if (svr_dev_id == SVR_DEV_LS2080A) | |
446 | erratum_a009635(); | |
b4017364 | 447 | #endif |
02fb2761 SL |
448 | #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) |
449 | erratum_a009942_check_cpo(); | |
450 | #endif | |
b4017364 | 451 | #ifdef CONFIG_MP |
2d16a1a6 | 452 | #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ |
daa92644 | 453 | defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) |
032d5bb4 HZ |
454 | /* Check the psci version to determine if the psci is supported */ |
455 | psci_ver = sec_firmware_support_psci_version(); | |
456 | #endif | |
457 | if (psci_ver == 0xffffffff) { | |
458 | rv = fsl_layerscape_wake_seconday_cores(); | |
459 | if (rv) | |
460 | printf("Did not wake secondary cores\n"); | |
461 | } | |
9f3183d2 | 462 | #endif |
40f8dec5 | 463 | |
31d34c6c ML |
464 | #ifdef CONFIG_SYS_HAS_SERDES |
465 | fsl_serdes_init(); | |
e8297341 SX |
466 | #endif |
467 | #ifdef CONFIG_FMAN_ENET | |
468 | fman_enet_init(); | |
31d34c6c | 469 | #endif |
40f8dec5 YS |
470 | return 0; |
471 | } | |
207774b2 YS |
472 | |
473 | int timer_init(void) | |
474 | { | |
475 | u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; | |
9f3183d2 | 476 | #ifdef CONFIG_FSL_LSCH3 |
207774b2 | 477 | u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; |
9f3183d2 | 478 | #endif |
a758177f YC |
479 | #ifdef CONFIG_LS2080A |
480 | u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; | |
f6b96ff6 | 481 | u32 svr_dev_id; |
a758177f | 482 | #endif |
207774b2 YS |
483 | #ifdef COUNTER_FREQUENCY_REAL |
484 | unsigned long cntfrq = COUNTER_FREQUENCY_REAL; | |
485 | ||
486 | /* Update with accurate clock frequency */ | |
487 | asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); | |
488 | #endif | |
489 | ||
9f3183d2 | 490 | #ifdef CONFIG_FSL_LSCH3 |
207774b2 YS |
491 | /* Enable timebase for all clusters. |
492 | * It is safe to do so even some clusters are not enabled. | |
493 | */ | |
494 | out_le32(cltbenr, 0xf); | |
9f3183d2 | 495 | #endif |
207774b2 | 496 | |
a758177f YC |
497 | #ifdef CONFIG_LS2080A |
498 | /* | |
499 | * In certain Layerscape SoCs, the clock for each core's | |
500 | * has an enable bit in the PMU Physical Core Time Base Enable | |
501 | * Register (PCTBENR), which allows the watchdog to operate. | |
502 | */ | |
503 | setbits_le32(pctbenr, 0xff); | |
f6b96ff6 PJ |
504 | /* |
505 | * For LS2080A SoC and its personalities, timer controller | |
506 | * offset is different | |
507 | */ | |
508 | svr_dev_id = get_svr() >> 16; | |
509 | if (svr_dev_id == SVR_DEV_LS2080A) | |
510 | cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR; | |
511 | ||
a758177f YC |
512 | #endif |
513 | ||
207774b2 YS |
514 | /* Enable clock for timer |
515 | * This is a global setting. | |
516 | */ | |
517 | out_le32(cntcr, 0x1); | |
518 | ||
519 | return 0; | |
520 | } | |
05d2e21b | 521 | |
78d57842 AG |
522 | __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; |
523 | ||
524 | void __efi_runtime reset_cpu(ulong addr) | |
05d2e21b | 525 | { |
05d2e21b | 526 | u32 val; |
527 | ||
528 | /* Raise RESET_REQ_B */ | |
9f3183d2 | 529 | val = scfg_in32(rstcr); |
05d2e21b | 530 | val |= 0x02; |
9f3183d2 | 531 | scfg_out32(rstcr, val); |
05d2e21b | 532 | } |
c0492141 | 533 | |
78d57842 AG |
534 | #ifdef CONFIG_EFI_LOADER |
535 | ||
536 | void __efi_runtime EFIAPI efi_reset_system( | |
537 | enum efi_reset_type reset_type, | |
538 | efi_status_t reset_status, | |
539 | unsigned long data_size, void *reset_data) | |
540 | { | |
541 | switch (reset_type) { | |
542 | case EFI_RESET_COLD: | |
543 | case EFI_RESET_WARM: | |
544 | reset_cpu(0); | |
545 | break; | |
546 | case EFI_RESET_SHUTDOWN: | |
547 | /* Nothing we can do */ | |
548 | break; | |
549 | } | |
550 | ||
551 | while (1) { } | |
552 | } | |
553 | ||
554 | void efi_reset_system_init(void) | |
555 | { | |
556 | efi_add_runtime_mmio(&rstcr, sizeof(*rstcr)); | |
557 | } | |
558 | ||
559 | #endif | |
560 | ||
c0492141 YS |
561 | phys_size_t board_reserve_ram_top(phys_size_t ram_size) |
562 | { | |
563 | phys_size_t ram_top = ram_size; | |
564 | ||
c0492141 | 565 | #ifdef CONFIG_FSL_MC_ENET |
36cc0de0 | 566 | /* The start address of MC reserved memory needs to be aligned. */ |
c0492141 YS |
567 | ram_top -= mc_get_dram_block_size(); |
568 | ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); | |
569 | #endif | |
570 | ||
36cc0de0 YS |
571 | return ram_size - ram_top; |
572 | } | |
573 | ||
574 | phys_size_t get_effective_memsize(void) | |
575 | { | |
576 | phys_size_t ea_size, rem = 0; | |
577 | ||
578 | /* | |
579 | * For ARMv8 SoCs, DDR memory is split into two or three regions. The | |
580 | * first region is 2GB space at 0x8000_0000. If the memory extends to | |
581 | * the second region (or the third region if applicable), the secure | |
582 | * memory and Management Complex (MC) memory should be put into the | |
583 | * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED | |
584 | * is set to the size of first region so U-Boot doesn't relocate itself | |
585 | * into higher address. Should DDR be configured to skip the first | |
586 | * region, this function needs to be adjusted. | |
587 | */ | |
588 | if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { | |
589 | ea_size = CONFIG_MAX_MEM_MAPPED; | |
590 | rem = gd->ram_size - ea_size; | |
591 | } else { | |
592 | ea_size = gd->ram_size; | |
593 | } | |
594 | ||
595 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE | |
596 | /* Check if we have enough space for secure memory */ | |
597 | if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) { | |
598 | rem -= CONFIG_SYS_MEM_RESERVE_SECURE; | |
599 | } else { | |
600 | if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) { | |
601 | ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; | |
602 | rem = 0; /* Presume MC requires more memory */ | |
603 | } else { | |
604 | printf("Error: No enough space for secure memory.\n"); | |
605 | } | |
606 | } | |
607 | #endif | |
608 | /* Check if we have enough memory for MC */ | |
609 | if (rem < board_reserve_ram_top(rem)) { | |
610 | /* Not enough memory in high region to reserve */ | |
611 | if (ea_size > board_reserve_ram_top(rem)) | |
612 | ea_size -= board_reserve_ram_top(rem); | |
613 | else | |
614 | printf("Error: No enough space for reserved memory.\n"); | |
615 | } | |
616 | ||
617 | return ea_size; | |
618 | } | |
619 | ||
620 | void dram_init_banksize(void) | |
621 | { | |
622 | #ifdef CONFIG_SYS_DP_DDR_BASE_PHY | |
623 | phys_size_t dp_ddr_size; | |
624 | #endif | |
625 | ||
626 | /* | |
627 | * gd->ram_size has the total size of DDR memory, less reserved secure | |
628 | * memory. The DDR extends from low region to high region(s) presuming | |
629 | * no hole is created with DDR configuration. gd->arch.secure_ram tracks | |
630 | * the location of secure memory. gd->arch.resv_ram tracks the location | |
631 | * of reserved memory for Management Complex (MC). | |
632 | */ | |
633 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
634 | if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { | |
635 | gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; | |
636 | gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; | |
637 | gd->bd->bi_dram[1].size = gd->ram_size - | |
638 | CONFIG_SYS_DDR_BLOCK1_SIZE; | |
639 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
640 | if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { | |
641 | gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; | |
642 | gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - | |
643 | CONFIG_SYS_DDR_BLOCK2_SIZE; | |
644 | gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; | |
645 | } | |
646 | #endif | |
647 | } else { | |
648 | gd->bd->bi_dram[0].size = gd->ram_size; | |
649 | } | |
650 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE | |
651 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
652 | if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { | |
653 | gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE; | |
654 | gd->arch.secure_ram = gd->bd->bi_dram[2].start + | |
655 | gd->bd->bi_dram[2].size; | |
656 | gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; | |
657 | gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; | |
658 | } else | |
659 | #endif | |
660 | { | |
661 | if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { | |
662 | gd->bd->bi_dram[1].size -= | |
663 | CONFIG_SYS_MEM_RESERVE_SECURE; | |
664 | gd->arch.secure_ram = gd->bd->bi_dram[1].start + | |
665 | gd->bd->bi_dram[1].size; | |
666 | gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; | |
667 | gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; | |
668 | } else if (gd->bd->bi_dram[0].size > | |
669 | CONFIG_SYS_MEM_RESERVE_SECURE) { | |
670 | gd->bd->bi_dram[0].size -= | |
671 | CONFIG_SYS_MEM_RESERVE_SECURE; | |
672 | gd->arch.secure_ram = gd->bd->bi_dram[0].start + | |
673 | gd->bd->bi_dram[0].size; | |
674 | gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; | |
675 | gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; | |
676 | } | |
677 | } | |
678 | #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ | |
679 | ||
680 | #ifdef CONFIG_FSL_MC_ENET | |
681 | /* Assign memory for MC */ | |
682 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
683 | if (gd->bd->bi_dram[2].size >= | |
684 | board_reserve_ram_top(gd->bd->bi_dram[2].size)) { | |
685 | gd->arch.resv_ram = gd->bd->bi_dram[2].start + | |
686 | gd->bd->bi_dram[2].size - | |
687 | board_reserve_ram_top(gd->bd->bi_dram[2].size); | |
688 | } else | |
689 | #endif | |
690 | { | |
691 | if (gd->bd->bi_dram[1].size >= | |
692 | board_reserve_ram_top(gd->bd->bi_dram[1].size)) { | |
693 | gd->arch.resv_ram = gd->bd->bi_dram[1].start + | |
694 | gd->bd->bi_dram[1].size - | |
695 | board_reserve_ram_top(gd->bd->bi_dram[1].size); | |
696 | } else if (gd->bd->bi_dram[0].size > | |
697 | board_reserve_ram_top(gd->bd->bi_dram[0].size)) { | |
698 | gd->arch.resv_ram = gd->bd->bi_dram[0].start + | |
699 | gd->bd->bi_dram[0].size - | |
700 | board_reserve_ram_top(gd->bd->bi_dram[0].size); | |
701 | } | |
702 | } | |
703 | #endif /* CONFIG_FSL_MC_ENET */ | |
704 | ||
705 | #ifdef CONFIG_SYS_DP_DDR_BASE_PHY | |
706 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
707 | #error "This SoC shouldn't have DP DDR" | |
708 | #endif | |
709 | if (soc_has_dp_ddr()) { | |
710 | /* initialize DP-DDR here */ | |
711 | puts("DP-DDR: "); | |
712 | /* | |
713 | * DDR controller use 0 as the base address for binding. | |
714 | * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. | |
715 | */ | |
716 | dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, | |
717 | CONFIG_DP_DDR_CTRL, | |
718 | CONFIG_DP_DDR_NUM_CTRLS, | |
719 | CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, | |
720 | NULL, NULL, NULL); | |
721 | if (dp_ddr_size) { | |
722 | gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; | |
723 | gd->bd->bi_dram[2].size = dp_ddr_size; | |
724 | } else { | |
725 | puts("Not detected"); | |
726 | } | |
727 | } | |
728 | #endif | |
729 | } | |
730 | ||
731 | #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) | |
732 | void efi_add_known_memory(void) | |
733 | { | |
734 | int i; | |
735 | phys_addr_t ram_start, start; | |
736 | phys_size_t ram_size; | |
737 | u64 pages; | |
738 | ||
739 | /* Add RAM */ | |
740 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
741 | #ifdef CONFIG_SYS_DP_DDR_BASE_PHY | |
742 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
743 | #error "This SoC shouldn't have DP DDR" | |
744 | #endif | |
745 | if (i == 2) | |
746 | continue; /* skip DP-DDR */ | |
747 | #endif | |
748 | ram_start = gd->bd->bi_dram[i].start; | |
749 | ram_size = gd->bd->bi_dram[i].size; | |
750 | #ifdef CONFIG_RESV_RAM | |
751 | if (gd->arch.resv_ram >= ram_start && | |
752 | gd->arch.resv_ram < ram_start + ram_size) | |
753 | ram_size = gd->arch.resv_ram - ram_start; | |
754 | #endif | |
755 | start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; | |
756 | pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; | |
757 | ||
758 | efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, | |
759 | false); | |
760 | } | |
c0492141 | 761 | } |
36cc0de0 | 762 | #endif |
4961eafc YS |
763 | |
764 | /* | |
765 | * Before DDR size is known, early MMU table have DDR mapped as device memory | |
766 | * to avoid speculative access. To relocate U-Boot to DDR, "normal memory" | |
767 | * needs to be set for these mappings. | |
768 | * If a special case configures DDR with holes in the mapping, the holes need | |
769 | * to be marked as invalid. This is not implemented in this function. | |
770 | */ | |
771 | void update_early_mmu_table(void) | |
772 | { | |
773 | if (!gd->arch.tlb_addr) | |
774 | return; | |
775 | ||
776 | if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { | |
777 | mmu_change_region_attr( | |
778 | CONFIG_SYS_SDRAM_BASE, | |
779 | gd->ram_size, | |
780 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
781 | PTE_BLOCK_OUTER_SHARE | | |
782 | PTE_BLOCK_NS | | |
783 | PTE_TYPE_VALID); | |
784 | } else { | |
785 | mmu_change_region_attr( | |
786 | CONFIG_SYS_SDRAM_BASE, | |
787 | CONFIG_SYS_DDR_BLOCK1_SIZE, | |
788 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
789 | PTE_BLOCK_OUTER_SHARE | | |
790 | PTE_BLOCK_NS | | |
791 | PTE_TYPE_VALID); | |
792 | #ifdef CONFIG_SYS_DDR_BLOCK3_BASE | |
793 | #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE | |
794 | #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" | |
795 | #endif | |
796 | if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > | |
797 | CONFIG_SYS_DDR_BLOCK2_SIZE) { | |
798 | mmu_change_region_attr( | |
799 | CONFIG_SYS_DDR_BLOCK2_BASE, | |
800 | CONFIG_SYS_DDR_BLOCK2_SIZE, | |
801 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
802 | PTE_BLOCK_OUTER_SHARE | | |
803 | PTE_BLOCK_NS | | |
804 | PTE_TYPE_VALID); | |
805 | mmu_change_region_attr( | |
806 | CONFIG_SYS_DDR_BLOCK3_BASE, | |
807 | gd->ram_size - | |
808 | CONFIG_SYS_DDR_BLOCK1_SIZE - | |
809 | CONFIG_SYS_DDR_BLOCK2_SIZE, | |
810 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
811 | PTE_BLOCK_OUTER_SHARE | | |
812 | PTE_BLOCK_NS | | |
813 | PTE_TYPE_VALID); | |
814 | } else | |
815 | #endif | |
816 | { | |
817 | mmu_change_region_attr( | |
818 | CONFIG_SYS_DDR_BLOCK2_BASE, | |
819 | gd->ram_size - | |
820 | CONFIG_SYS_DDR_BLOCK1_SIZE, | |
821 | PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
822 | PTE_BLOCK_OUTER_SHARE | | |
823 | PTE_BLOCK_NS | | |
824 | PTE_TYPE_VALID); | |
825 | } | |
826 | } | |
827 | } | |
828 | ||
829 | __weak int dram_init(void) | |
830 | { | |
831 | gd->ram_size = initdram(0); | |
832 | #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) | |
833 | /* This will break-before-make MMU for DDR */ | |
834 | update_early_mmu_table(); | |
835 | #endif | |
836 | ||
837 | return 0; | |
838 | } |