[people/ms/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / cpu.c

/*
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/arch/cpu.h>
#include <asm/arch/speed.h>
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
#include <efi_loader.h>
#include <fm_eth.h>
#include <fsl-mc/fsl_mc.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

struct mm_region *mem_map = early_map;

void cpu_name(char *name)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	unsigned int i, svr, ver;

	svr = gur_in32(&gur->svr);
	ver = SVR_SOC_VER(svr);

	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
		if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
			strcpy(name, cpu_type_list[i].name);

			if (IS_E_PROCESSOR(svr))
				strcat(name, "E");

			sprintf(name + strlen(name), " Rev%d.%d",
				SVR_MAJ(svr), SVR_MIN(svr));
			break;
		}

	if (i == ARRAY_SIZE(cpu_type_list))
		strcpy(name, "unknown");
}

#ifndef CONFIG_SYS_DCACHE_OFF
/*
 * To start MMU before DDR is available, we create MMU table in SRAM.
 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 * levels of translation tables here to cover 40-bit address space.
 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 * Note, the debug print in cache_v8.c is not usable for debugging
 * these early MMU tables because UART is not yet available.
 */
static inline void early_mmu_setup(void)
{
	unsigned int el = current_el();

	/* global data is already setup, no allocation yet */
	gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
	gd->arch.tlb_fillptr = gd->arch.tlb_addr;
	gd->arch.tlb_size = EARLY_PGTABLE_SIZE;

	/* Create early page tables */
	setup_pgtables();

	/* point TTBR to the new table */
	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
			  get_tcr(el, NULL, NULL) &
			  ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
			  MEMORY_ATTRIBUTES);

	set_sctlr(get_sctlr() | CR_M);
}

/*
 * The final tables look similar to early tables, but different in detail.
 * These tables are in DRAM. Sub tables are added to enable cache for
 * QBMan and OCRAM.
 *
 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 */
static inline void final_mmu_setup(void)
{
	u64 tlb_addr_save = gd->arch.tlb_addr;
	unsigned int el = current_el();
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
	int index;
#endif

	mem_map = final_map;

#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
		if (el == 3) {
			/*
			 * Only use gd->arch.secure_ram if the address is
			 * recalculated. Align to 4KB for MMU table.
			 */
			/* put page tables in secure ram */
			index = ARRAY_SIZE(final_map) - 2;
			gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
			final_map[index].virt = gd->arch.secure_ram & ~0x3;
			final_map[index].phys = final_map[index].virt;
			final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
			final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
			gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
			tlb_addr_save = gd->arch.tlb_addr;
		} else {
			/* Use allocated (board_f.c) memory for TLB */
			tlb_addr_save = gd->arch.tlb_allocated;
			gd->arch.tlb_addr = tlb_addr_save;
		}
	}
#endif

	/* Reset the fill ptr */
	gd->arch.tlb_fillptr = tlb_addr_save;

	/* Create normal system page tables */
	setup_pgtables();

	/* Create emergency page tables */
	gd->arch.tlb_addr = gd->arch.tlb_fillptr;
	gd->arch.tlb_emerg = gd->arch.tlb_addr;
	setup_pgtables();
	gd->arch.tlb_addr = tlb_addr_save;

	/* flush new MMU table */
	flush_dcache_range(gd->arch.tlb_addr,
			   gd->arch.tlb_addr + gd->arch.tlb_size);

	/* point TTBR to the new table */
	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
			  MEMORY_ATTRIBUTES);
	/*
	 * EL3 MMU is already enabled, just need to invalidate TLB to load the
	 * new table. The new table is compatible with the current table, if
	 * MMU somehow walks through the new table before invalidation TLB,
	 * it still works. So we don't need to turn off MMU here.
	 * When EL2 MMU table is created by calling this function, MMU needs
	 * to be enabled.
	 */
	set_sctlr(get_sctlr() | CR_M);
}

u64 get_page_table_size(void)
{
	return 0x10000;
}

int arch_cpu_init(void)
{
	icache_enable();
	__asm_invalidate_dcache_all();
	__asm_invalidate_tlb_all();
	early_mmu_setup();
	set_sctlr(get_sctlr() | CR_C);
	return 0;
}

void mmu_setup(void)
{
	final_mmu_setup();
}

/*
 * This function is called from common/board_r.c.
 * It recreates MMU table in main memory.
 */
void enable_caches(void)
{
	mmu_setup();
	__asm_invalidate_tlb_all();
	icache_enable();
	dcache_enable();
}
#endif

static inline u32 initiator_type(u32 cluster, int init_id)
{
	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
	u32 type = 0;

	type = gur_in32(&gur->tp_ityp[idx]);
	if (type & TP_ITYP_AV)
		return type;

	return 0;
}

u32 cpu_pos_mask(void)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	int i = 0;
	u32 cluster, type, mask = 0;

	do {
		int j;

		cluster = gur_in32(&gur->tp_cluster[i].lower);
		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
			type = initiator_type(cluster, j);
			if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
				mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
		}
		i++;
	} while ((cluster & TP_CLUSTER_EOC) == 0x0);

	return mask;
}

u32 cpu_mask(void)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	int i = 0, count = 0;
	u32 cluster, type, mask = 0;

	do {
		int j;

		cluster = gur_in32(&gur->tp_cluster[i].lower);
		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
			type = initiator_type(cluster, j);
			if (type) {
				if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
					mask |= 1 << count;
				count++;
			}
		}
		i++;
	} while ((cluster & TP_CLUSTER_EOC) == 0x0);

	return mask;
}

/*
 * Return the number of cores on this SOC.
 */
int cpu_numcores(void)
{
	return hweight32(cpu_mask());
}

int fsl_qoriq_core_to_cluster(unsigned int core)
{
	struct ccsr_gur __iomem *gur =
		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
	int i = 0, count = 0;
	u32 cluster;

	do {
		int j;

		cluster = gur_in32(&gur->tp_cluster[i].lower);
		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
			if (initiator_type(cluster, j)) {
				if (count == core)
					return i;
				count++;
			}
		}
		i++;
	} while ((cluster & TP_CLUSTER_EOC) == 0x0);

	return -1;      /* cannot identify the cluster */
}

u32 fsl_qoriq_core_to_type(unsigned int core)
{
	struct ccsr_gur __iomem *gur =
		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
	int i = 0, count = 0;
	u32 cluster, type;

	do {
		int j;

		cluster = gur_in32(&gur->tp_cluster[i].lower);
		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
			type = initiator_type(cluster, j);
			if (type) {
				if (count == core)
					return type;
				count++;
			}
		}
		i++;
	} while ((cluster & TP_CLUSTER_EOC) == 0x0);

	return -1;      /* cannot identify the cluster */
}

#ifndef CONFIG_FSL_LSCH3
uint get_svr(void)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);

	return gur_in32(&gur->svr);
}
#endif

#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	struct sys_info sysinfo;
	char buf[32];
	unsigned int i, core;
	u32 type, rcw, svr = gur_in32(&gur->svr);

	puts("SoC: ");

	cpu_name(buf);
	printf(" %s (0x%x)\n", buf, svr);
	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
	get_sys_info(&sysinfo);
	puts("Clock Configuration:");
	for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
		if (!(i % 3))
			puts("\n       ");
		type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
		printf("CPU%d(%s):%-4s MHz  ", core,
		       type == TY_ITYP_VER_A7 ? "A7 " :
		       (type == TY_ITYP_VER_A53 ? "A53" :
		       (type == TY_ITYP_VER_A57 ? "A57" :
		       (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
		       strmhz(buf, sysinfo.freq_processor[core]));
	}
	printf("\n       Bus:      %-4s MHz  ",
	       strmhz(buf, sysinfo.freq_systembus));
	printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
#ifdef CONFIG_SYS_DPAA_FMAN
	printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
#endif
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (soc_has_dp_ddr()) {
		printf("     DP-DDR:   %-4s MT/s",
		       strmhz(buf, sysinfo.freq_ddrbus2));
	}
#endif
	puts("\n");

	/*
	 * Display the RCW, so that no one gets confused as to what RCW
	 * we're actually using for this boot.
	 */
	puts("Reset Configuration Word (RCW):");
	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
		rcw = gur_in32(&gur->rcwsr[i]);
		if ((i % 4) == 0)
			printf("\n       %08x:", i * 4);
		printf(" %08x", rcw);
	}
	puts("\n");

	return 0;
}
#endif

#ifdef CONFIG_FSL_ESDHC
int cpu_mmc_init(bd_t *bis)
{
	return fsl_esdhc_mmc_init(bis);
}
#endif

int cpu_eth_init(bd_t *bis)
{
	int error = 0;

#ifdef CONFIG_FSL_MC_ENET
	error = fsl_mc_ldpaa_init(bis);
#endif
#ifdef CONFIG_FMAN_ENET
	fm_standard_init(bis);
#endif
	return error;
}

int arch_early_init_r(void)
{
#ifdef CONFIG_MP
	int rv = 1;
	u32 psci_ver = 0xffffffff;
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
	erratum_a009635();
#endif

#ifdef CONFIG_MP
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
	/* Check the psci version to determine if the psci is supported */
	psci_ver = sec_firmware_support_psci_version();
#endif
	if (psci_ver == 0xffffffff) {
		rv = fsl_layerscape_wake_seconday_cores();
		if (rv)
			printf("Did not wake secondary cores\n");
	}
#endif

#ifdef CONFIG_SYS_HAS_SERDES
	fsl_serdes_init();
#endif
#ifdef CONFIG_FMAN_ENET
	fman_enet_init();
#endif
	return 0;
}

int timer_init(void)
{
	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_FSL_LSCH3
	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
#ifdef CONFIG_LS2080A
	u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
	u32 svr_dev_id;
#endif
#ifdef COUNTER_FREQUENCY_REAL
	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;

	/* Update with accurate clock frequency */
	asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
#endif

#ifdef CONFIG_FSL_LSCH3
	/* Enable timebase for all clusters.
	 * It is safe to do so even some clusters are not enabled.
	 */
	out_le32(cltbenr, 0xf);
#endif

#ifdef CONFIG_LS2080A
	/*
	 * In certain Layerscape SoCs, the clock for each core's
	 * has an enable bit in the PMU Physical Core Time Base Enable
	 * Register (PCTBENR), which allows the watchdog to operate.
	 */
	setbits_le32(pctbenr, 0xff);
	/*
	 * For LS2080A SoC and its personalities, timer controller
	 * offset is different
	 */
	svr_dev_id = get_svr() >> 16;
	if (svr_dev_id == SVR_DEV_LS2080A)
		cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;

#endif

	/* Enable clock for timer
	 * This is a global setting.
	 */
	out_le32(cntcr, 0x1);

	return 0;
}

__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;

void __efi_runtime reset_cpu(ulong addr)
{
	u32 val;

	/* Raise RESET_REQ_B */
	val = scfg_in32(rstcr);
	val |= 0x02;
	scfg_out32(rstcr, val);
}

#ifdef CONFIG_EFI_LOADER

void __efi_runtime EFIAPI efi_reset_system(
		       enum efi_reset_type reset_type,
		       efi_status_t reset_status,
		       unsigned long data_size, void *reset_data)
{
	switch (reset_type) {
	case EFI_RESET_COLD:
	case EFI_RESET_WARM:
		reset_cpu(0);
		break;
	case EFI_RESET_SHUTDOWN:
		/* Nothing we can do */
		break;
	}

	while (1) { }
}

void efi_reset_system_init(void)
{
       efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
}

#endif

phys_size_t board_reserve_ram_top(phys_size_t ram_size)
{
	phys_size_t ram_top = ram_size;

#ifdef CONFIG_SYS_MEM_TOP_HIDE
#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
#endif

/* Carve the MC private DRAM block from the end of DRAM */
#ifdef CONFIG_FSL_MC_ENET
	ram_top -= mc_get_dram_block_size();
	ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
#endif

	return ram_top;
}
Commit	Line	Data
2f78eae5	1	/*
9f3183d2	2	* Copyright 2014-2015 Freescale Semiconductor, Inc.
2f78eae5 YS	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
1221ce45	9	#include <linux/errno.h>
2f78eae5 YS	10	#include <asm/system.h>
	11	#include <asm/armv8/mmu.h>
	12	#include <asm/io.h>
9f3183d2 MH	13	#include <asm/arch/fsl_serdes.h>
	14	#include <asm/arch/soc.h>
	15	#include <asm/arch/cpu.h>
	16	#include <asm/arch/speed.h>
	17	#ifdef CONFIG_MP
	18	#include <asm/arch/mp.h>
	19	#endif
78d57842	20	#include <efi_loader.h>
9f3183d2	21	#include <fm_eth.h>
7b3bd9a7	22	#include <fsl-mc/fsl_mc.h>
8b06460e YL	23	#ifdef CONFIG_FSL_ESDHC
	24	#include <fsl_esdhc.h>
	25	#endif
032d5bb4 HZ	26	#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
	27	#include <asm/armv8/sec_firmware.h>
	28	#endif
2f78eae5 YS	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
5ad5823d	32	struct mm_region *mem_map = early_map;
7985cdf7	33
22629665 PK	34	void cpu_name(char *name)
	35	{
	36	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	37	unsigned int i, svr, ver;
	38
9f3183d2	39	svr = gur_in32(&gur->svr);
22629665 PK	40	ver = SVR_SOC_VER(svr);
	41
	42	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
	43	if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
	44	strcpy(name, cpu_type_list[i].name);
	45
	46	if (IS_E_PROCESSOR(svr))
	47	strcat(name, "E");
5d1a7a9d WS	48
	49	sprintf(name + strlen(name), " Rev%d.%d",
	50	SVR_MAJ(svr), SVR_MIN(svr));
22629665 PK	51	break;
	52	}
	53
	54	if (i == ARRAY_SIZE(cpu_type_list))
	55	strcpy(name, "unknown");
	56	}
	57
2f78eae5	58	#ifndef CONFIG_SYS_DCACHE_OFF
99799220 AW	59	/*
	60	* To start MMU before DDR is available, we create MMU table in SRAM.
	61	* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
	62	* levels of translation tables here to cover 40-bit address space.
	63	* We use 4KB granule size, with 40 bits physical address, T0SZ=24
5ad5823d YS	64	* Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
	65	* Note, the debug print in cache_v8.c is not usable for debugging
	66	* these early MMU tables because UART is not yet available.
99799220 AW	67	*/
	68	static inline void early_mmu_setup(void)
	69	{
5ad5823d	70	unsigned int el = current_el();
99799220	71
5ad5823d YS	72	/* global data is already setup, no allocation yet */
	73	gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
	74	gd->arch.tlb_fillptr = gd->arch.tlb_addr;
	75	gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
99799220	76
5ad5823d YS	77	/* Create early page tables */
5ad5823d YS	78	setup_pgtables();
9f3183d2	79
5ad5823d YS	80	/* point TTBR to the new table */
	81	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
	82	get_tcr(el, NULL, NULL) &
	83	~(TCR_ORGN_MASK \| TCR_IRGN_MASK),
9f3183d2	84	MEMORY_ATTRIBUTES);
c107c0c0	85
5ad5823d	86	set_sctlr(get_sctlr() \| CR_M);
c107c0c0	87	}
c107c0c0	88
2f78eae5	89	/*
99799220 AW	90	* The final tables look similar to early tables, but different in detail.
	91	* These tables are in DRAM. Sub tables are added to enable cache for
	92	* QBMan and OCRAM.
	93	*
e61a7534 YS	94	* Put the MMU table in secure memory if gd->arch.secure_ram is valid.
e61a7534 YS	95	* OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
2f78eae5 YS	96	*/
	97	static inline void final_mmu_setup(void)
	98	{
5ad5823d	99	u64 tlb_addr_save = gd->arch.tlb_addr;
c107c0c0	100	unsigned int el = current_el();
c107c0c0	101	#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
5ad5823d	102	int index;
c107c0c0	103	#endif
2f78eae5	104
5ad5823d	105	mem_map = final_map;
2f78eae5	106
c107c0c0	107	#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
5ad5823d YS	108	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
	109	if (el == 3) {
	110	/*
	111	* Only use gd->arch.secure_ram if the address is
	112	* recalculated. Align to 4KB for MMU table.
	113	*/
	114	/* put page tables in secure ram */
	115	index = ARRAY_SIZE(final_map) - 2;
	116	gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
	117	final_map[index].virt = gd->arch.secure_ram & ~0x3;
	118	final_map[index].phys = final_map[index].virt;
	119	final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
	120	final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
e61a7534	121	gd->arch.secure_ram \|= MEM_RESERVE_SECURE_SECURED;
5ad5823d	122	tlb_addr_save = gd->arch.tlb_addr;
c107c0c0	123	} else {
5ad5823d YS	124	/* Use allocated (board_f.c) memory for TLB */
	125	tlb_addr_save = gd->arch.tlb_allocated;
	126	gd->arch.tlb_addr = tlb_addr_save;
c107c0c0 YS	127	}
	128	}
	129	#endif
2f78eae5	130
5ad5823d YS	131	/* Reset the fill ptr */
	132	gd->arch.tlb_fillptr = tlb_addr_save;
	133
	134	/* Create normal system page tables */
	135	setup_pgtables();
	136
	137	/* Create emergency page tables */
	138	gd->arch.tlb_addr = gd->arch.tlb_fillptr;
	139	gd->arch.tlb_emerg = gd->arch.tlb_addr;
	140	setup_pgtables();
	141	gd->arch.tlb_addr = tlb_addr_save;
	142
2f78eae5	143	/* flush new MMU table */
5ad5823d YS	144	flush_dcache_range(gd->arch.tlb_addr,
5ad5823d YS	145	gd->arch.tlb_addr + gd->arch.tlb_size);
2f78eae5 YS	146
2f78eae5 YS	147	/* point TTBR to the new table */
5ad5823d	148	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
db14f11d	149	MEMORY_ATTRIBUTES);
2f78eae5	150	/*
ed7a3943	151	* EL3 MMU is already enabled, just need to invalidate TLB to load the
2f78eae5 YS	152	* new table. The new table is compatible with the current table, if
	153	* MMU somehow walks through the new table before invalidation TLB,
	154	* it still works. So we don't need to turn off MMU here.
ed7a3943 YS	155	* When EL2 MMU table is created by calling this function, MMU needs
ed7a3943 YS	156	* to be enabled.
2f78eae5	157	*/
ed7a3943	158	set_sctlr(get_sctlr() \| CR_M);
2f78eae5 YS	159	}
2f78eae5 YS	160
c05016ab AG	161	u64 get_page_table_size(void)
	162	{
	163	return 0x10000;
	164	}
	165
2f78eae5 YS	166	int arch_cpu_init(void)
	167	{
	168	icache_enable();
	169	__asm_invalidate_dcache_all();
	170	__asm_invalidate_tlb_all();
	171	early_mmu_setup();
	172	set_sctlr(get_sctlr() \| CR_C);
	173	return 0;
	174	}
	175
85cdf38e HZ	176	void mmu_setup(void)
	177	{
	178	final_mmu_setup();
	179	}
	180
2f78eae5	181	/*
85cdf38e HZ	182	* This function is called from common/board_r.c.
85cdf38e HZ	183	* It recreates MMU table in main memory.
2f78eae5 YS	184	*/
	185	void enable_caches(void)
	186	{
85cdf38e	187	mmu_setup();
2f78eae5	188	__asm_invalidate_tlb_all();
85cdf38e HZ	189	icache_enable();
85cdf38e HZ	190	dcache_enable();
2f78eae5 YS	191	}
	192	#endif
	193
	194	static inline u32 initiator_type(u32 cluster, int init_id)
	195	{
	196	struct ccsr_gur gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	197	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
9f3183d2	198	u32 type = 0;
2f78eae5	199
9f3183d2	200	type = gur_in32(&gur->tp_ityp[idx]);
2f78eae5 YS	201	if (type & TP_ITYP_AV)
	202	return type;
	203
	204	return 0;
	205	}
	206
ef9a5fd8 YS	207	u32 cpu_pos_mask(void)
	208	{
	209	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	210	int i = 0;
	211	u32 cluster, type, mask = 0;
	212
	213	do {
	214	int j;
	215
	216	cluster = gur_in32(&gur->tp_cluster[i].lower);
	217	for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
	218	type = initiator_type(cluster, j);
	219	if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
	220	mask \|= 1 << (i * TP_INIT_PER_CLUSTER + j);
	221	}
	222	i++;
	223	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
	224
	225	return mask;
	226	}
	227
2f78eae5 YS	228	u32 cpu_mask(void)
	229	{
	230	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	231	int i = 0, count = 0;
	232	u32 cluster, type, mask = 0;
	233
	234	do {
	235	int j;
9f3183d2 MH	236
9f3183d2 MH	237	cluster = gur_in32(&gur->tp_cluster[i].lower);
2f78eae5 YS	238	for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
	239	type = initiator_type(cluster, j);
	240	if (type) {
	241	if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
	242	mask \|= 1 << count;
	243	count++;
	244	}
	245	}
	246	i++;
9f3183d2	247	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
2f78eae5 YS	248
	249	return mask;
	250	}
	251
	252	/*
	253	* Return the number of cores on this SOC.
	254	*/
	255	int cpu_numcores(void)
	256	{
	257	return hweight32(cpu_mask());
	258	}
	259
	260	int fsl_qoriq_core_to_cluster(unsigned int core)
	261	{
	262	struct ccsr_gur __iomem *gur =
	263	(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
	264	int i = 0, count = 0;
	265	u32 cluster;
	266
	267	do {
	268	int j;
9f3183d2 MH	269
9f3183d2 MH	270	cluster = gur_in32(&gur->tp_cluster[i].lower);
2f78eae5 YS	271	for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
	272	if (initiator_type(cluster, j)) {
	273	if (count == core)
	274	return i;
	275	count++;
	276	}
	277	}
	278	i++;
9f3183d2	279	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
2f78eae5 YS	280
	281	return -1; /* cannot identify the cluster */
	282	}
	283
	284	u32 fsl_qoriq_core_to_type(unsigned int core)
	285	{
	286	struct ccsr_gur __iomem *gur =
	287	(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
	288	int i = 0, count = 0;
	289	u32 cluster, type;
	290
	291	do {
	292	int j;
9f3183d2 MH	293
9f3183d2 MH	294	cluster = gur_in32(&gur->tp_cluster[i].lower);
2f78eae5 YS	295	for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
	296	type = initiator_type(cluster, j);
	297	if (type) {
	298	if (count == core)
	299	return type;
	300	count++;
	301	}
	302	}
	303	i++;
9f3183d2	304	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
2f78eae5 YS	305
	306	return -1; /* cannot identify the cluster */
	307	}
	308
f6a70b3a	309	#ifndef CONFIG_FSL_LSCH3
6fb522dc SD	310	uint get_svr(void)
	311	{
	312	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	313
	314	return gur_in32(&gur->svr);
	315	}
f6a70b3a	316	#endif
6fb522dc	317
2f78eae5 YS	318	#ifdef CONFIG_DISPLAY_CPUINFO
	319	int print_cpuinfo(void)
	320	{
d27bf906	321	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
2f78eae5 YS	322	struct sys_info sysinfo;
	323	char buf[32];
	324	unsigned int i, core;
3c1d218a	325	u32 type, rcw, svr = gur_in32(&gur->svr);
2f78eae5	326
22629665 PK	327	puts("SoC: ");
	328
	329	cpu_name(buf);
3c1d218a	330	printf(" %s (0x%x)\n", buf, svr);
22629665	331	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
2f78eae5 YS	332	get_sys_info(&sysinfo);
	333	puts("Clock Configuration:");
	334	for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
	335	if (!(i % 3))
	336	puts("\n ");
	337	type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
	338	printf("CPU%d(%s):%-4s MHz ", core,
	339	type == TY_ITYP_VER_A7 ? "A7 " :
	340	(type == TY_ITYP_VER_A53 ? "A53" :
79119a4d AW	341	(type == TY_ITYP_VER_A57 ? "A57" :
79119a4d AW	342	(type == TY_ITYP_VER_A72 ? "A72" : " "))),
2f78eae5 YS	343	strmhz(buf, sysinfo.freq_processor[core]));
	344	}
	345	printf("\n Bus: %-4s MHz ",
	346	strmhz(buf, sysinfo.freq_systembus));
d4c711f0	347	printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
e8297341 SX	348	#ifdef CONFIG_SYS_DPAA_FMAN
	349	printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
	350	#endif
44937214	351	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
3c1d218a YS	352	if (soc_has_dp_ddr()) {
	353	printf(" DP-DDR: %-4s MT/s",
	354	strmhz(buf, sysinfo.freq_ddrbus2));
	355	}
9f3183d2	356	#endif
2f78eae5 YS	357	puts("\n");
2f78eae5 YS	358
9f3183d2 MH	359	/*
9f3183d2 MH	360	* Display the RCW, so that no one gets confused as to what RCW
d27bf906 BS	361	* we're actually using for this boot.
	362	*/
	363	puts("Reset Configuration Word (RCW):");
	364	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
9f3183d2	365	rcw = gur_in32(&gur->rcwsr[i]);
d27bf906	366	if ((i % 4) == 0)
9f3183d2	367	printf("\n %08x:", i * 4);
d27bf906 BS	368	printf(" %08x", rcw);
	369	}
	370	puts("\n");
	371
2f78eae5 YS	372	return 0;
	373	}
	374	#endif
b940ca64	375
8b06460e YL	376	#ifdef CONFIG_FSL_ESDHC
	377	int cpu_mmc_init(bd_t *bis)
	378	{
	379	return fsl_esdhc_mmc_init(bis);
	380	}
	381	#endif
	382
b940ca64 GR	383	int cpu_eth_init(bd_t *bis)
	384	{
	385	int error = 0;
	386
	387	#ifdef CONFIG_FSL_MC_ENET
a2a55e51	388	error = fsl_mc_ldpaa_init(bis);
e8297341 SX	389	#endif
	390	#ifdef CONFIG_FMAN_ENET
	391	fm_standard_init(bis);
b940ca64 GR	392	#endif
	393	return error;
	394	}
40f8dec5	395
40f8dec5 YS	396	int arch_early_init_r(void)
40f8dec5 YS	397	{
9f3183d2 MH	398	#ifdef CONFIG_MP
9f3183d2 MH	399	int rv = 1;
032d5bb4	400	u32 psci_ver = 0xffffffff;
b4017364 PK	401	#endif
	402
	403	#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
	404	erratum_a009635();
	405	#endif
40f8dec5	406
b4017364	407	#ifdef CONFIG_MP
032d5bb4 HZ	408	#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
	409	/* Check the psci version to determine if the psci is supported */
	410	psci_ver = sec_firmware_support_psci_version();
	411	#endif
	412	if (psci_ver == 0xffffffff) {
	413	rv = fsl_layerscape_wake_seconday_cores();
	414	if (rv)
	415	printf("Did not wake secondary cores\n");
	416	}
9f3183d2	417	#endif
40f8dec5	418
31d34c6c ML	419	#ifdef CONFIG_SYS_HAS_SERDES
31d34c6c ML	420	fsl_serdes_init();
e8297341 SX	421	#endif
	422	#ifdef CONFIG_FMAN_ENET
	423	fman_enet_init();
31d34c6c	424	#endif
40f8dec5 YS	425	return 0;
40f8dec5 YS	426	}
207774b2 YS	427
	428	int timer_init(void)
	429	{
	430	u32 __iomem cntcr = (u32 )CONFIG_SYS_FSL_TIMER_ADDR;
9f3183d2	431	#ifdef CONFIG_FSL_LSCH3
207774b2	432	u32 __iomem cltbenr = (u32 )CONFIG_SYS_FSL_PMU_CLTBENR;
9f3183d2	433	#endif
a758177f YC	434	#ifdef CONFIG_LS2080A
a758177f YC	435	u32 __iomem pctbenr = (u32 )FSL_PMU_PCTBENR_OFFSET;
f6b96ff6	436	u32 svr_dev_id;
a758177f	437	#endif
207774b2 YS	438	#ifdef COUNTER_FREQUENCY_REAL
	439	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
	440
	441	/* Update with accurate clock frequency */
	442	asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
	443	#endif
	444
9f3183d2	445	#ifdef CONFIG_FSL_LSCH3
207774b2 YS	446	/* Enable timebase for all clusters.
	447	* It is safe to do so even some clusters are not enabled.
	448	*/
	449	out_le32(cltbenr, 0xf);
9f3183d2	450	#endif
207774b2	451
a758177f YC	452	#ifdef CONFIG_LS2080A
	453	/*
	454	* In certain Layerscape SoCs, the clock for each core's
	455	* has an enable bit in the PMU Physical Core Time Base Enable
	456	* Register (PCTBENR), which allows the watchdog to operate.
	457	*/
	458	setbits_le32(pctbenr, 0xff);
f6b96ff6 PJ	459	/*
	460	* For LS2080A SoC and its personalities, timer controller
	461	* offset is different
	462	*/
	463	svr_dev_id = get_svr() >> 16;
	464	if (svr_dev_id == SVR_DEV_LS2080A)
	465	cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
	466
a758177f YC	467	#endif
a758177f YC	468
207774b2 YS	469	/* Enable clock for timer
	470	* This is a global setting.
	471	*/
	472	out_le32(cntcr, 0x1);
	473
	474	return 0;
	475	}
05d2e21b	476
78d57842 AG	477	__efi_runtime_data u32 __iomem rstcr = (u32 )CONFIG_SYS_FSL_RST_ADDR;
	478
	479	void __efi_runtime reset_cpu(ulong addr)
05d2e21b	480	{
05d2e21b	481	u32 val;
	482
	483	/* Raise RESET_REQ_B */
9f3183d2	484	val = scfg_in32(rstcr);
05d2e21b	485	val \|= 0x02;
9f3183d2	486	scfg_out32(rstcr, val);
05d2e21b	487	}
c0492141	488
78d57842 AG	489	#ifdef CONFIG_EFI_LOADER
	490
	491	void __efi_runtime EFIAPI efi_reset_system(
	492	enum efi_reset_type reset_type,
	493	efi_status_t reset_status,
	494	unsigned long data_size, void *reset_data)
	495	{
	496	switch (reset_type) {
	497	case EFI_RESET_COLD:
	498	case EFI_RESET_WARM:
	499	reset_cpu(0);
	500	break;
	501	case EFI_RESET_SHUTDOWN:
	502	/* Nothing we can do */
	503	break;
	504	}
	505
	506	while (1) { }
	507	}
	508
	509	void efi_reset_system_init(void)
	510	{
	511	efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
	512	}
	513
	514	#endif
	515
c0492141 YS	516	phys_size_t board_reserve_ram_top(phys_size_t ram_size)
	517	{
	518	phys_size_t ram_top = ram_size;
	519
	520	#ifdef CONFIG_SYS_MEM_TOP_HIDE
	521	#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
	522	#endif
c0492141 YS	523
	524	/* Carve the MC private DRAM block from the end of DRAM */
	525	#ifdef CONFIG_FSL_MC_ENET
	526	ram_top -= mc_get_dram_block_size();
	527	ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
	528	#endif
	529
	530	return ram_top;
	531	}