[thirdparty/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / fdt.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 * Copyright 2020 NXP
 */

#include <common.h>
#include <clock_legacy.h>
#include <efi_loader.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <phy.h>
#ifdef CONFIG_FSL_LSCH3
#include <asm/arch/fdt.h>
#endif
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#include <fsl_fman.h>
#endif
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
#include <fsl_sec.h>
#include <asm/arch-fsl-layerscape/soc.h>
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif
#include <asm/arch/speed.h>
#include <fsl_qbman.h>

int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
	const char *conn;

	/* Do NOT apply fixup for backplane modes specified in DT */
	if (phyc == PHY_INTERFACE_MODE_XGMII) {
		conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
		if (is_backplane_mode(conn))
			return 0;
	}
	return fdt_setprop_string(blob, offset, "phy-connection-type",
					 phy_string_for_interface(phyc));
}

#ifdef CONFIG_MP
void ft_fixup_cpu(void *blob)
{
	int off;
	__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
	fdt32_t *reg;
	int addr_cells;
	u64 val, core_id;
	size_t *boot_code_size = &(__secondary_boot_code_size);
	u32 mask = cpu_pos_mask();
	int off_prev = -1;

	off = fdt_path_offset(blob, "/cpus");
	if (off < 0) {
		puts("couldn't find /cpus node\n");
		return;
	}

	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);

	off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
					    "cpu", 4);
	while (off != -FDT_ERR_NOTFOUND) {
		reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
		if (reg) {
			core_id = fdt_read_number(reg, addr_cells);
			if (!test_bit(id_to_core(core_id), &mask)) {
				fdt_del_node(blob, off);
				off = off_prev;
			}
		}
		off_prev = off;
		off = fdt_node_offset_by_prop_value(blob, off_prev,
						    "device_type", "cpu", 4);
	}

#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
	defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
	int node;
	u32 psci_ver;

	/* Check the psci version to determine if the psci is supported */
	psci_ver = sec_firmware_support_psci_version();
	if (psci_ver == 0xffffffff) {
		/* remove psci DT node */
		node = fdt_path_offset(blob, "/psci");
		if (node >= 0)
			goto remove_psci_node;

		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci");
		if (node >= 0)
			goto remove_psci_node;

		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-0.2");
		if (node >= 0)
			goto remove_psci_node;

		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-1.0");
		if (node >= 0)
			goto remove_psci_node;

remove_psci_node:
		if (node >= 0)
			fdt_del_node(blob, node);
	} else {
		return;
	}
#endif
	off = fdt_path_offset(blob, "/cpus");
	if (off < 0) {
		puts("couldn't find /cpus node\n");
		return;
	}
	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);

	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
	while (off != -FDT_ERR_NOTFOUND) {
		reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
		if (reg) {
			core_id = fdt_read_number(reg, addr_cells);
			if (core_id  == 0 || (is_core_online(core_id))) {
				val = spin_tbl_addr;
				val += id_to_core(core_id) *
				       SPIN_TABLE_ELEM_SIZE;
				val = cpu_to_fdt64(val);
				fdt_setprop_string(blob, off, "enable-method",
						   "spin-table");
				fdt_setprop(blob, off, "cpu-release-addr",
					    &val, sizeof(val));
			} else {
				debug("skipping offline core\n");
			}
		} else {
			puts("Warning: found cpu node without reg property\n");
		}
		off = fdt_node_offset_by_prop_value(blob, off, "device_type",
						    "cpu", 4);
	}

	fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
			*boot_code_size);
#if CONFIG_IS_ENABLED(EFI_LOADER)
	efi_add_memory_map((uintptr_t)&secondary_boot_code, *boot_code_size,
			   EFI_RESERVED_MEMORY_TYPE);
#endif
}
#endif

void fsl_fdt_disable_usb(void *blob)
{
	int off;
	/*
	 * SYSCLK is used as a reference clock for USB. When the USB
	 * controller is used, SYSCLK must meet the additional requirement
	 * of 100 MHz.
	 */
	if (CONFIG_SYS_CLK_FREQ != 100000000) {
		off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
		while (off != -FDT_ERR_NOTFOUND) {
			fdt_status_disabled(blob, off);
			off = fdt_node_offset_by_compatible(blob, off,
							    "snps,dwc3");
		}
	}
}

#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
static void fdt_fixup_gic(void *blob)
{
	int offset, err;
	u64 reg[8];
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	unsigned int val;
	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
	int align_64k = 0;

	val = gur_in32(&gur->svr);

	if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
		align_64k = 1;
	} else if (SVR_REV(val) != REV1_0) {
		val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
		if (!val)
			align_64k = 1;
	}

	offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000");
	if (offset < 0) {
		printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
		       "interrupt-controller@1400000", fdt_strerror(offset));
		return;
	}

	/* Fixup gic node align with 64K */
	if (align_64k) {
		reg[0] = cpu_to_fdt64(GICD_BASE_64K);
		reg[1] = cpu_to_fdt64(GICD_SIZE_64K);
		reg[2] = cpu_to_fdt64(GICC_BASE_64K);
		reg[3] = cpu_to_fdt64(GICC_SIZE_64K);
		reg[4] = cpu_to_fdt64(GICH_BASE_64K);
		reg[5] = cpu_to_fdt64(GICH_SIZE_64K);
		reg[6] = cpu_to_fdt64(GICV_BASE_64K);
		reg[7] = cpu_to_fdt64(GICV_SIZE_64K);
	} else {
	/* Fixup gic node align with default */
		reg[0] = cpu_to_fdt64(GICD_BASE);
		reg[1] = cpu_to_fdt64(GICD_SIZE);
		reg[2] = cpu_to_fdt64(GICC_BASE);
		reg[3] = cpu_to_fdt64(GICC_SIZE);
		reg[4] = cpu_to_fdt64(GICH_BASE);
		reg[5] = cpu_to_fdt64(GICH_SIZE);
		reg[6] = cpu_to_fdt64(GICV_BASE);
		reg[7] = cpu_to_fdt64(GICV_SIZE);
	}

	err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
	if (err < 0) {
		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
		       "reg", "interrupt-controller@1400000",
		       fdt_strerror(err));
		return;
	}

	return;
}
#endif

#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
static int _fdt_fixup_msi_node(void *blob, const char *name,
				  int irq_0, int irq_1, int rev)
{
	int err, offset, len;
	u32 tmp[4][3];
	void *p;

	offset = fdt_path_offset(blob, name);
	if (offset < 0) {
		printf("WARNING: fdt_path_offset can't find path %s: %s\n",
		       name, fdt_strerror(offset));
		return 0;
	}

	/*fixup the property of interrupts*/

	tmp[0][0] = cpu_to_fdt32(0x0);
	tmp[0][1] = cpu_to_fdt32(irq_0);
	tmp[0][2] = cpu_to_fdt32(0x4);

	if (rev > REV1_0) {
		tmp[1][0] = cpu_to_fdt32(0x0);
		tmp[1][1] = cpu_to_fdt32(irq_1);
		tmp[1][2] = cpu_to_fdt32(0x4);
		tmp[2][0] = cpu_to_fdt32(0x0);
		tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
		tmp[2][2] = cpu_to_fdt32(0x4);
		tmp[3][0] = cpu_to_fdt32(0x0);
		tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
		tmp[3][2] = cpu_to_fdt32(0x4);
		len = sizeof(tmp);
	} else {
		len = sizeof(tmp[0]);
	}

	err = fdt_setprop(blob, offset, "interrupts", tmp, len);
	if (err < 0) {
		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
		       "interrupts", name, fdt_strerror(err));
		return 0;
	}

	/*fixup the property of reg*/
	p = (char *)fdt_getprop(blob, offset, "reg", &len);
	if (!p) {
		printf("WARNING: fdt_getprop can't get %s from node %s\n",
		       "reg", name);
		return 0;
	}

	memcpy((char *)tmp, p, len);

	if (rev > REV1_0)
		*((u32 *)tmp + 3) = cpu_to_fdt32(0x1000);
	else
		*((u32 *)tmp + 3) = cpu_to_fdt32(0x8);

	err = fdt_setprop(blob, offset, "reg", tmp, len);
	if (err < 0) {
		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
		       "reg", name, fdt_strerror(err));
		return 0;
	}

	/*fixup the property of compatible*/
	if (rev > REV1_0)
		err = fdt_setprop_string(blob, offset, "compatible",
					 "fsl,ls1043a-v1.1-msi");
	else
		err = fdt_setprop_string(blob, offset, "compatible",
					 "fsl,ls1043a-msi");
	if (err < 0) {
		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
		       "compatible", name, fdt_strerror(err));
		return 0;
	}

	return 1;
}

static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
{
	int offset, len, err;
	void *p;
	int val;
	u32 tmp[4][8];

	offset = fdt_path_offset(blob, name);
	if (offset < 0) {
		printf("WARNING: fdt_path_offset can't find path %s: %s\n",
		       name, fdt_strerror(offset));
		return 0;
	}

	p = (char *)fdt_getprop(blob, offset, "interrupt-map", &len);
	if (!p || len != sizeof(tmp)) {
		printf("WARNING: fdt_getprop can't get %s from node %s\n",
		       "interrupt-map", name);
		return 0;
	}

	memcpy((char *)tmp, p, len);

	val = fdt32_to_cpu(tmp[0][6]);
	if (rev == REV1_0) {
		tmp[1][6] = cpu_to_fdt32(val + 1);
		tmp[2][6] = cpu_to_fdt32(val + 2);
		tmp[3][6] = cpu_to_fdt32(val + 3);
	} else {
		tmp[1][6] = cpu_to_fdt32(val);
		tmp[2][6] = cpu_to_fdt32(val);
		tmp[3][6] = cpu_to_fdt32(val);
	}

	err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
	if (err < 0) {
		printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
		       "interrupt-map", name, fdt_strerror(err));
		return 0;
	}
	return 1;
}

/* Fixup msi node for ls1043a rev1.1*/

static void fdt_fixup_msi(void *blob)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	unsigned int rev;

	rev = gur_in32(&gur->svr);

	if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
		return;

	rev = SVR_REV(rev);

	_fdt_fixup_msi_node(blob, "/soc/msi-controller1@1571000",
			    116, 111, rev);
	_fdt_fixup_msi_node(blob, "/soc/msi-controller2@1572000",
			    126, 121, rev);
	_fdt_fixup_msi_node(blob, "/soc/msi-controller3@1573000",
			    160, 155, rev);

	_fdt_fixup_pci_msi(blob, "/soc/pcie@3400000", rev);
	_fdt_fixup_pci_msi(blob, "/soc/pcie@3500000", rev);
	_fdt_fixup_pci_msi(blob, "/soc/pcie@3600000", rev);
}
#endif

#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/* Remove JR node used by SEC firmware */
void fdt_fixup_remove_jr(void *blob)
{
	int jr_node, addr_cells, len;
	int crypto_node = fdt_path_offset(blob, "crypto");
	u64 jr_offset, used_jr;
	fdt32_t *reg;

	used_jr = sec_firmware_used_jobring_offset();
	fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);

	jr_node = fdt_node_offset_by_compatible(blob, crypto_node,
						"fsl,sec-v4.0-job-ring");

	while (jr_node != -FDT_ERR_NOTFOUND) {
		reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
		jr_offset = fdt_read_number(reg, addr_cells);
		if (jr_offset == used_jr) {
			fdt_del_node(blob, jr_node);
			break;
		}
		jr_node = fdt_node_offset_by_compatible(blob, jr_node,
							"fsl,sec-v4.0-job-ring");
	}
}
#endif

#ifdef CONFIG_ARCH_LS1028A
static void fdt_disable_multimedia(void *blob, unsigned int svr)
{
	int off;

	if (IS_MULTIMEDIA_EN(svr))
		return;

	/* Disable eDP/LCD node */
	off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500");
	if (off != -FDT_ERR_NOTFOUND)
		fdt_status_disabled(blob, off);

	/* Disable GPU node */
	off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
	if (off != -FDT_ERR_NOTFOUND)
		fdt_status_disabled(blob, off);
}
#endif

#ifdef CONFIG_PCIE_ECAM_GENERIC
__weak void fdt_fixup_ecam(void *blob)
{
}
#endif

void ft_cpu_setup(void *blob, bd_t *bd)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	unsigned int svr = gur_in32(&gur->svr);

	/* delete crypto node if not on an E-processor */
	if (!IS_E_PROCESSOR(svr))
		fdt_fixup_crypto_node(blob, 0);
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
	else {
		ccsr_sec_t __iomem *sec;

#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
		fdt_fixup_remove_jr(blob);
		fdt_fixup_kaslr(blob);
#endif

		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
	}
#endif

#ifdef CONFIG_MP
	ft_fixup_cpu(blob);
#endif

#ifdef CONFIG_SYS_NS16550
	do_fixup_by_compat_u32(blob, "fsl,ns16550",
			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif

	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
			     CONFIG_SYS_CLK_FREQ, 1);

#ifdef CONFIG_GIC_V3_ITS
	ls_gic_rd_tables_init(blob);
#endif

#if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
	ft_pci_setup(blob, bd);
#endif

#ifdef CONFIG_FSL_ESDHC
	fdt_fixup_esdhc(blob, bd);
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	fdt_fixup_bportals(blob);
	fdt_fixup_qportals(blob);
	do_fixup_by_compat_u32(blob, "fsl,qman",
			       "clock-frequency", get_qman_freq(), 1);
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	fdt_fixup_fman_firmware(blob);
#endif
#ifndef CONFIG_ARCH_LS1012A
	fsl_fdt_disable_usb(blob);
#endif
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
	fdt_fixup_gic(blob);
#endif
#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
	fdt_fixup_msi(blob);
#endif
#ifdef CONFIG_ARCH_LS1028A
	fdt_disable_multimedia(blob, svr);
#endif
#ifdef CONFIG_PCIE_ECAM_GENERIC
	fdt_fixup_ecam(blob);
#endif
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
40f8dec5	2	/*
9f3183d2	3	* Copyright 2014-2015 Freescale Semiconductor, Inc.
5d3bcdb1	4	* Copyright 2020 NXP
40f8dec5 YS	5	*/
	6
	7	#include <common.h>
d96c2604	8	#include <clock_legacy.h>
5a37a2f0	9	#include <efi_loader.h>
b08c8c48	10	#include <linux/libfdt.h>
40f8dec5	11	#include <fdt_support.h>
9f3183d2 MH	12	#include <phy.h>
	13	#ifdef CONFIG_FSL_LSCH3
	14	#include <asm/arch/fdt.h>
	15	#endif
8b06460e YL	16	#ifdef CONFIG_FSL_ESDHC
	17	#include <fsl_esdhc.h>
	18	#endif
0e52b6fe QG	19	#ifdef CONFIG_SYS_DPAA_FMAN
	20	#include <fsl_fman.h>
	21	#endif
9f3183d2 MH	22	#ifdef CONFIG_MP
	23	#include <asm/arch/mp.h>
	24	#endif
f13c99c2 AP	25	#include <fsl_sec.h>
f13c99c2 AP	26	#include <asm/arch-fsl-layerscape/soc.h>
032d5bb4 HZ	27	#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
	28	#include <asm/armv8/sec_firmware.h>
	29	#endif
44262327 AM	30	#include <asm/arch/speed.h>
44262327 AM	31	#include <fsl_qbman.h>
40f8dec5	32
e8297341 SX	33	int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
e8297341 SX	34	{
5d3bcdb1 FI	35	const char *conn;
	36
	37	/* Do NOT apply fixup for backplane modes specified in DT */
	38	if (phyc == PHY_INTERFACE_MODE_XGMII) {
	39	conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
	40	if (is_backplane_mode(conn))
	41	return 0;
	42	}
e8297341 SX	43	return fdt_setprop_string(blob, offset, "phy-connection-type",
	44	phy_string_for_interface(phyc));
	45	}
	46
40f8dec5 YS	47	#ifdef CONFIG_MP
	48	void ft_fixup_cpu(void *blob)
	49	{
	50	int off;
	51	__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
	52	fdt32_t *reg;
	53	int addr_cells;
60385d94	54	u64 val, core_id;
40f8dec5	55	size_t *boot_code_size = &(__secondary_boot_code_size);
20c73051 W	56	u32 mask = cpu_pos_mask();
	57	int off_prev = -1;
	58
	59	off = fdt_path_offset(blob, "/cpus");
	60	if (off < 0) {
	61	puts("couldn't find /cpus node\n");
	62	return;
	63	}
	64
	65	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);
	66
	67	off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
	68	"cpu", 4);
	69	while (off != -FDT_ERR_NOTFOUND) {
	70	reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
	71	if (reg) {
	72	core_id = fdt_read_number(reg, addr_cells);
	73	if (!test_bit(id_to_core(core_id), &mask)) {
	74	fdt_del_node(blob, off);
	75	off = off_prev;
	76	}
	77	}
	78	off_prev = off;
	79	off = fdt_node_offset_by_prop_value(blob, off_prev,
	80	"device_type", "cpu", 4);
	81	}
	82
2d16a1a6	83	#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
daa92644	84	defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
032d5bb4 HZ	85	int node;
	86	u32 psci_ver;
	87
	88	/* Check the psci version to determine if the psci is supported */
	89	psci_ver = sec_firmware_support_psci_version();
	90	if (psci_ver == 0xffffffff) {
	91	/* remove psci DT node */
	92	node = fdt_path_offset(blob, "/psci");
	93	if (node >= 0)
	94	goto remove_psci_node;
	95
	96	node = fdt_node_offset_by_compatible(blob, -1, "arm,psci");
	97	if (node >= 0)
	98	goto remove_psci_node;
	99
	100	node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-0.2");
	101	if (node >= 0)
	102	goto remove_psci_node;
40f8dec5	103
032d5bb4 HZ	104	node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-1.0");
	105	if (node >= 0)
	106	goto remove_psci_node;
	107
	108	remove_psci_node:
	109	if (node >= 0)
	110	fdt_del_node(blob, node);
	111	} else {
	112	return;
	113	}
	114	#endif
40f8dec5 YS	115	off = fdt_path_offset(blob, "/cpus");
	116	if (off < 0) {
	117	puts("couldn't find /cpus node\n");
	118	return;
	119	}
eed36609	120	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);
40f8dec5 YS	121
	122	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
	123	while (off != -FDT_ERR_NOTFOUND) {
	124	reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
	125	if (reg) {
eed36609	126	core_id = fdt_read_number(reg, addr_cells);
60385d94 AB	127	if (core_id == 0 \|\| (is_core_online(core_id))) {
	128	val = spin_tbl_addr;
	129	val += id_to_core(core_id) *
	130	SPIN_TABLE_ELEM_SIZE;
	131	val = cpu_to_fdt64(val);
	132	fdt_setprop_string(blob, off, "enable-method",
	133	"spin-table");
	134	fdt_setprop(blob, off, "cpu-release-addr",
	135	&val, sizeof(val));
	136	} else {
	137	debug("skipping offline core\n");
	138	}
40f8dec5 YS	139	} else {
	140	puts("Warning: found cpu node without reg property\n");
	141	}
	142	off = fdt_node_offset_by_prop_value(blob, off, "device_type",
	143	"cpu", 4);
	144	}
	145
	146	fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
	147	*boot_code_size);
9b5e6396	148	#if CONFIG_IS_ENABLED(EFI_LOADER)
714497e3 MW	149	efi_add_memory_map((uintptr_t)&secondary_boot_code, *boot_code_size,
714497e3 MW	150	EFI_RESERVED_MEMORY_TYPE);
5a37a2f0	151	#endif
40f8dec5 YS	152	}
	153	#endif
	154
c93db4f7 SD	155	void fsl_fdt_disable_usb(void *blob)
	156	{
	157	int off;
	158	/*
	159	* SYSCLK is used as a reference clock for USB. When the USB
	160	* controller is used, SYSCLK must meet the additional requirement
	161	* of 100 MHz.
	162	*/
	163	if (CONFIG_SYS_CLK_FREQ != 100000000) {
	164	off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
	165	while (off != -FDT_ERR_NOTFOUND) {
	166	fdt_status_disabled(blob, off);
	167	off = fdt_node_offset_by_compatible(blob, off,
	168	"snps,dwc3");
	169	}
	170	}
	171	}
	172
fa18ed76 WS	173	#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
	174	static void fdt_fixup_gic(void *blob)
	175	{
	176	int offset, err;
	177	u64 reg[8];
	178	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	179	unsigned int val;
	180	struct ccsr_scfg __iomem scfg = (void )CONFIG_SYS_FSL_SCFG_ADDR;
	181	int align_64k = 0;
	182
	183	val = gur_in32(&gur->svr);
	184
a8f33034	185	if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
fa18ed76 WS	186	align_64k = 1;
	187	} else if (SVR_REV(val) != REV1_0) {
	188	val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
	189	if (!val)
	190	align_64k = 1;
	191	}
	192
	193	offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000");
	194	if (offset < 0) {
	195	printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
	196	"interrupt-controller@1400000", fdt_strerror(offset));
	197	return;
	198	}
	199
	200	/* Fixup gic node align with 64K */
	201	if (align_64k) {
	202	reg[0] = cpu_to_fdt64(GICD_BASE_64K);
	203	reg[1] = cpu_to_fdt64(GICD_SIZE_64K);
	204	reg[2] = cpu_to_fdt64(GICC_BASE_64K);
	205	reg[3] = cpu_to_fdt64(GICC_SIZE_64K);
	206	reg[4] = cpu_to_fdt64(GICH_BASE_64K);
	207	reg[5] = cpu_to_fdt64(GICH_SIZE_64K);
	208	reg[6] = cpu_to_fdt64(GICV_BASE_64K);
	209	reg[7] = cpu_to_fdt64(GICV_SIZE_64K);
	210	} else {
	211	/* Fixup gic node align with default */
	212	reg[0] = cpu_to_fdt64(GICD_BASE);
	213	reg[1] = cpu_to_fdt64(GICD_SIZE);
	214	reg[2] = cpu_to_fdt64(GICC_BASE);
	215	reg[3] = cpu_to_fdt64(GICC_SIZE);
	216	reg[4] = cpu_to_fdt64(GICH_BASE);
	217	reg[5] = cpu_to_fdt64(GICH_SIZE);
	218	reg[6] = cpu_to_fdt64(GICV_BASE);
	219	reg[7] = cpu_to_fdt64(GICV_SIZE);
	220	}
	221
	222	err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
	223	if (err < 0) {
	224	printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
	225	"reg", "interrupt-controller@1400000",
	226	fdt_strerror(err));
	227	return;
	228	}
	229
	230	return;
	231	}
	232	#endif
	233
2ca84bf7 WS	234	#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
	235	static int _fdt_fixup_msi_node(void blob, const char name,
	236	int irq_0, int irq_1, int rev)
	237	{
	238	int err, offset, len;
	239	u32 tmp[4][3];
	240	void *p;
	241
	242	offset = fdt_path_offset(blob, name);
	243	if (offset < 0) {
	244	printf("WARNING: fdt_path_offset can't find path %s: %s\n",
	245	name, fdt_strerror(offset));
	246	return 0;
	247	}
	248
	249	/fixup the property of interrupts/
	250
	251	tmp[0][0] = cpu_to_fdt32(0x0);
	252	tmp[0][1] = cpu_to_fdt32(irq_0);
	253	tmp[0][2] = cpu_to_fdt32(0x4);
	254
	255	if (rev > REV1_0) {
	256	tmp[1][0] = cpu_to_fdt32(0x0);
	257	tmp[1][1] = cpu_to_fdt32(irq_1);
	258	tmp[1][2] = cpu_to_fdt32(0x4);
	259	tmp[2][0] = cpu_to_fdt32(0x0);
	260	tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
	261	tmp[2][2] = cpu_to_fdt32(0x4);
	262	tmp[3][0] = cpu_to_fdt32(0x0);
	263	tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
	264	tmp[3][2] = cpu_to_fdt32(0x4);
	265	len = sizeof(tmp);
	266	} else {
	267	len = sizeof(tmp[0]);
	268	}
	269
	270	err = fdt_setprop(blob, offset, "interrupts", tmp, len);
	271	if (err < 0) {
	272	printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
	273	"interrupts", name, fdt_strerror(err));
	274	return 0;
	275	}
	276
	277	/fixup the property of reg/
	278	p = (char *)fdt_getprop(blob, offset, "reg", &len);
	279	if (!p) {
	280	printf("WARNING: fdt_getprop can't get %s from node %s\n",
	281	"reg", name);
	282	return 0;
	283	}
	284
	285	memcpy((char *)tmp, p, len);
	286
	287	if (rev > REV1_0)
	288	((u32 )tmp + 3) = cpu_to_fdt32(0x1000);
	289	else
	290	((u32 )tmp + 3) = cpu_to_fdt32(0x8);
	291
	292	err = fdt_setprop(blob, offset, "reg", tmp, len);
	293	if (err < 0) {
	294	printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
	295	"reg", name, fdt_strerror(err));
	296	return 0;
	297	}
298
299	/fixup the property of compatible/
300	if (rev > REV1_0)
301	err = fdt_setprop_string(blob, offset, "compatible",
302	"fsl,ls1043a-v1.1-msi");
303	else
304	err = fdt_setprop_string(blob, offset, "compatible",
305	"fsl,ls1043a-msi");
306	if (err < 0) {
307	printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
308	"compatible", name, fdt_strerror(err));
309	return 0;
310	}
311
312	return 1;
313	}
314
315	static int _fdt_fixup_pci_msi(void blob, const char name, int rev)
316	{
317	int offset, len, err;
318	void *p;
319	int val;
320	u32 tmp[4][8];
321
322	offset = fdt_path_offset(blob, name);
323	if (offset < 0) {
324	printf("WARNING: fdt_path_offset can't find path %s: %s\n",
325	name, fdt_strerror(offset));
326	return 0;
327	}
328
329	p = (char *)fdt_getprop(blob, offset, "interrupt-map", &len);
330	if (!p \|\| len != sizeof(tmp)) {
331	printf("WARNING: fdt_getprop can't get %s from node %s\n",
332	"interrupt-map", name);
333	return 0;
334	}
335
336	memcpy((char *)tmp, p, len);
337
338	val = fdt32_to_cpu(tmp[0][6]);
5b994e85	339	if (rev == REV1_0) {
2ca84bf7 WS	340	tmp[1][6] = cpu_to_fdt32(val + 1);
	341	tmp[2][6] = cpu_to_fdt32(val + 2);
	342	tmp[3][6] = cpu_to_fdt32(val + 3);
	343	} else {
	344	tmp[1][6] = cpu_to_fdt32(val);
	345	tmp[2][6] = cpu_to_fdt32(val);
	346	tmp[3][6] = cpu_to_fdt32(val);
	347	}
	348
	349	err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
	350	if (err < 0) {
	351	printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
	352	"interrupt-map", name, fdt_strerror(err));
	353	return 0;
	354	}
	355	return 1;
	356	}
	357
	358	/* Fixup msi node for ls1043a rev1.1*/
	359
	360	static void fdt_fixup_msi(void *blob)
	361	{
	362	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	363	unsigned int rev;
	364
	365	rev = gur_in32(&gur->svr);
	366
a8f33034	367	if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
2ca84bf7 WS	368	return;
	369
	370	rev = SVR_REV(rev);
	371
	372	_fdt_fixup_msi_node(blob, "/soc/msi-controller1@1571000",
	373	116, 111, rev);
	374	_fdt_fixup_msi_node(blob, "/soc/msi-controller2@1572000",
	375	126, 121, rev);
	376	_fdt_fixup_msi_node(blob, "/soc/msi-controller3@1573000",
	377	160, 155, rev);
	378
	379	_fdt_fixup_pci_msi(blob, "/soc/pcie@3400000", rev);
	380	_fdt_fixup_pci_msi(blob, "/soc/pcie@3500000", rev);
	381	_fdt_fixup_pci_msi(blob, "/soc/pcie@3600000", rev);
	382	}
	383	#endif
	384
a797f274 RG	385	#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
	386	/* Remove JR node used by SEC firmware */
	387	void fdt_fixup_remove_jr(void *blob)
	388	{
	389	int jr_node, addr_cells, len;
	390	int crypto_node = fdt_path_offset(blob, "crypto");
	391	u64 jr_offset, used_jr;
	392	fdt32_t *reg;
	393
	394	used_jr = sec_firmware_used_jobring_offset();
	395	fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
	396
	397	jr_node = fdt_node_offset_by_compatible(blob, crypto_node,
	398	"fsl,sec-v4.0-job-ring");
	399
	400	while (jr_node != -FDT_ERR_NOTFOUND) {
	401	reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
	402	jr_offset = fdt_read_number(reg, addr_cells);
	403	if (jr_offset == used_jr) {
	404	fdt_del_node(blob, jr_node);
	405	break;
	406	}
	407	jr_node = fdt_node_offset_by_compatible(blob, jr_node,
	408	"fsl,sec-v4.0-job-ring");
	409	}
	410	}
	411	#endif
	412
54d5c06c YT	413	#ifdef CONFIG_ARCH_LS1028A
	414	static void fdt_disable_multimedia(void *blob, unsigned int svr)
	415	{
	416	int off;
	417
	418	if (IS_MULTIMEDIA_EN(svr))
	419	return;
	420
	421	/* Disable eDP/LCD node */
	422	off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500");
	423	if (off != -FDT_ERR_NOTFOUND)
	424	fdt_status_disabled(blob, off);
	425
	426	/* Disable GPU node */
	427	off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
	428	if (off != -FDT_ERR_NOTFOUND)
	429	fdt_status_disabled(blob, off);
	430	}
	431	#endif
	432
3499dd03 AM	433	#ifdef CONFIG_PCIE_ECAM_GENERIC
	434	__weak void fdt_fixup_ecam(void *blob)
	435	{
	436	}
	437	#endif
	438
40f8dec5 YS	439	void ft_cpu_setup(void blob, bd_t bd)
40f8dec5 YS	440	{
f13c99c2	441	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
a797f274	442	unsigned int svr = gur_in32(&gur->svr);
f13c99c2 AP	443
	444	/* delete crypto node if not on an E-processor */
	445	if (!IS_E_PROCESSOR(svr))
	446	fdt_fixup_crypto_node(blob, 0);
	447	#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
	448	else {
	449	ccsr_sec_t __iomem *sec;
	450
a797f274	451	#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
b6bb93de RG	452	fdt_fixup_remove_jr(blob);
b6bb93de RG	453	fdt_fixup_kaslr(blob);
a797f274 RG	454	#endif
a797f274 RG	455
f13c99c2 AP	456	sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
	457	fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
	458	}
	459	#endif
f13c99c2	460
40f8dec5 YS	461	#ifdef CONFIG_MP
	462	ft_fixup_cpu(blob);
	463	#endif
912cc40f BS	464
912cc40f BS	465	#ifdef CONFIG_SYS_NS16550
1e52835a	466	do_fixup_by_compat_u32(blob, "fsl,ns16550",
912cc40f BS	467	"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
912cc40f BS	468	#endif
8b06460e	469
3d91f46c YL	470	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
3d91f46c YL	471	CONFIG_SYS_CLK_FREQ, 1);
6f14e257	472
f40b120e HZ	473	#ifdef CONFIG_GIC_V3_ITS
	474	ls_gic_rd_tables_init(blob);
	475	#endif
	476
c9ba88ba	477	#if defined(CONFIG_PCIE_LAYERSCAPE) \|\| defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
5be3b44c PK	478	ft_pci_setup(blob, bd);
	479	#endif
	480
9f3183d2	481	#ifdef CONFIG_FSL_ESDHC
8b06460e YL	482	fdt_fixup_esdhc(blob, bd);
8b06460e YL	483	#endif
70e52d21	484
44262327 AM	485	#ifdef CONFIG_SYS_DPAA_QBMAN
	486	fdt_fixup_bportals(blob);
	487	fdt_fixup_qportals(blob);
	488	do_fixup_by_compat_u32(blob, "fsl,qman",
	489	"clock-frequency", get_qman_freq(), 1);
	490	#endif
	491
0e52b6fe QG	492	#ifdef CONFIG_SYS_DPAA_FMAN
	493	fdt_fixup_fman_firmware(blob);
	494	#endif
5436c6a3	495	#ifndef CONFIG_ARCH_LS1012A
c93db4f7	496	fsl_fdt_disable_usb(blob);
132a1468	497	#endif
fa18ed76 WS	498	#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
	499	fdt_fixup_gic(blob);
	500	#endif
2ca84bf7 WS	501	#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
	502	fdt_fixup_msi(blob);
	503	#endif
54d5c06c YT	504	#ifdef CONFIG_ARCH_LS1028A
	505	fdt_disable_multimedia(blob, svr);
	506	#endif
3499dd03 AM	507	#ifdef CONFIG_PCIE_ECAM_GENERIC
	508	fdt_fixup_ecam(blob);
	509	#endif
40f8dec5	510	}