[thirdparty/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / fdt.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 * Copyright 2020 NXP
 */

#include <common.h>
#include <clock_legacy.h>
#include <efi_loader.h>
#include <asm/cache.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <phy.h>
#ifdef CONFIG_FSL_LSCH3
#include <asm/arch/fdt.h>
#endif
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#include <fsl_fman.h>
#endif
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
#include <fsl_sec.h>
#include <asm/arch-fsl-layerscape/soc.h>
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif
#include <asm/arch/speed.h>
#include <fsl_qbman.h>

int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
	const char *conn;

	/* Do NOT apply fixup for backplane modes specified in DT */
	if (phyc == PHY_INTERFACE_MODE_XGMII) {
		conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
		if (is_backplane_mode(conn))
			return 0;
	}
	return fdt_setprop_string(blob, offset, "phy-connection-type",
					 phy_string_for_interface(phyc));
}

#ifdef CONFIG_MP
void ft_fixup_cpu(void *blob)
{
	int off;
	__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
	fdt32_t *reg;
	int addr_cells;
	u64 val, core_id;
	size_t *boot_code_size = &(__secondary_boot_code_size);
	u32 mask = cpu_pos_mask();
	int off_prev = -1;

	off = fdt_path_offset(blob, "/cpus");
	if (off < 0) {
		puts("couldn't find /cpus node\n");
		return;
	}

	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);

	off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
					    "cpu", 4);
	while (off != -FDT_ERR_NOTFOUND) {
		reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
		if (reg) {
			core_id = fdt_read_number(reg, addr_cells);
			if (!test_bit(id_to_core(core_id), &mask)) {
				fdt_del_node(blob, off);
				off = off_prev;
			}
		}
		off_prev = off;
		off = fdt_node_offset_by_prop_value(blob, off_prev,
						    "device_type", "cpu", 4);
	}

#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
	defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
	int node;
	u32 psci_ver;

	/* Check the psci version to determine if the psci is supported */
	psci_ver = sec_firmware_support_psci_version();
	if (psci_ver == 0xffffffff) {
		/* remove psci DT node */
		node = fdt_path_offset(blob, "/psci");
		if (node >= 0)
			goto remove_psci_node;

		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci");
		if (node >= 0)
			goto remove_psci_node;

		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-0.2");
		if (node >= 0)
			goto remove_psci_node;

		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-1.0");
		if (node >= 0)
			goto remove_psci_node;

remove_psci_node:
		if (node >= 0)
			fdt_del_node(blob, node);
	} else {
		return;
	}
#endif
	off = fdt_path_offset(blob, "/cpus");
	if (off < 0) {
		puts("couldn't find /cpus node\n");
		return;
	}
	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);

	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
	while (off != -FDT_ERR_NOTFOUND) {
		reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
		if (reg) {
			core_id = fdt_read_number(reg, addr_cells);
			if (core_id  == 0 || (is_core_online(core_id))) {
				val = spin_tbl_addr;
				val += id_to_core(core_id) *
				       SPIN_TABLE_ELEM_SIZE;
				val = cpu_to_fdt64(val);
				fdt_setprop_string(blob, off, "enable-method",
						   "spin-table");
				fdt_setprop(blob, off, "cpu-release-addr",
					    &val, sizeof(val));
			} else {
				debug("skipping offline core\n");
			}
		} else {
			puts("Warning: found cpu node without reg property\n");
		}
		off = fdt_node_offset_by_prop_value(blob, off, "device_type",
						    "cpu", 4);
	}

	fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
			*boot_code_size);
#if CONFIG_IS_ENABLED(EFI_LOADER)
	efi_add_memory_map((uintptr_t)&secondary_boot_code, *boot_code_size,
			   EFI_RESERVED_MEMORY_TYPE);
#endif
}
#endif

void fsl_fdt_disable_usb(void *blob)
{
	int off;
	/*
	 * SYSCLK is used as a reference clock for USB. When the USB
	 * controller is used, SYSCLK must meet the additional requirement
	 * of 100 MHz.
	 */
	if (CONFIG_SYS_CLK_FREQ != 100000000) {
		off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
		while (off != -FDT_ERR_NOTFOUND) {
			fdt_status_disabled(blob, off);
			off = fdt_node_offset_by_compatible(blob, off,
							    "snps,dwc3");
		}
	}
}

#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
static void fdt_fixup_gic(void *blob)
{
	int offset, err;
	u64 reg[8];
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	unsigned int val;
	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
	int align_64k = 0;

	val = gur_in32(&gur->svr);

	if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
		align_64k = 1;
	} else if (SVR_REV(val) != REV1_0) {
		val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
		if (!val)
			align_64k = 1;
	}

	offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000");
	if (offset < 0) {
		printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
		       "interrupt-controller@1400000", fdt_strerror(offset));
		return;
	}

	/* Fixup gic node align with 64K */
	if (align_64k) {
		reg[0] = cpu_to_fdt64(GICD_BASE_64K);
		reg[1] = cpu_to_fdt64(GICD_SIZE_64K);
		reg[2] = cpu_to_fdt64(GICC_BASE_64K);
		reg[3] = cpu_to_fdt64(GICC_SIZE_64K);
		reg[4] = cpu_to_fdt64(GICH_BASE_64K);
		reg[5] = cpu_to_fdt64(GICH_SIZE_64K);
		reg[6] = cpu_to_fdt64(GICV_BASE_64K);
		reg[7] = cpu_to_fdt64(GICV_SIZE_64K);
	} else {
	/* Fixup gic node align with default */
		reg[0] = cpu_to_fdt64(GICD_BASE);
		reg[1] = cpu_to_fdt64(GICD_SIZE);
		reg[2] = cpu_to_fdt64(GICC_BASE);
		reg[3] = cpu_to_fdt64(GICC_SIZE);
		reg[4] = cpu_to_fdt64(GICH_BASE);
		reg[5] = cpu_to_fdt64(GICH_SIZE);
		reg[6] = cpu_to_fdt64(GICV_BASE);
		reg[7] = cpu_to_fdt64(GICV_SIZE);
	}

	err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
	if (err < 0) {
		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
		       "reg", "interrupt-controller@1400000",
		       fdt_strerror(err));
		return;
	}

	return;
}
#endif

#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
static int _fdt_fixup_msi_node(void *blob, const char *name,
				  int irq_0, int irq_1, int rev)
{
	int err, offset, len;
	u32 tmp[4][3];
	void *p;

	offset = fdt_path_offset(blob, name);
	if (offset < 0) {
		printf("WARNING: fdt_path_offset can't find path %s: %s\n",
		       name, fdt_strerror(offset));
		return 0;
	}

	/*fixup the property of interrupts*/

	tmp[0][0] = cpu_to_fdt32(0x0);
	tmp[0][1] = cpu_to_fdt32(irq_0);
	tmp[0][2] = cpu_to_fdt32(0x4);

	if (rev > REV1_0) {
		tmp[1][0] = cpu_to_fdt32(0x0);
		tmp[1][1] = cpu_to_fdt32(irq_1);
		tmp[1][2] = cpu_to_fdt32(0x4);
		tmp[2][0] = cpu_to_fdt32(0x0);
		tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
		tmp[2][2] = cpu_to_fdt32(0x4);
		tmp[3][0] = cpu_to_fdt32(0x0);
		tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
		tmp[3][2] = cpu_to_fdt32(0x4);
		len = sizeof(tmp);
	} else {
		len = sizeof(tmp[0]);
	}

	err = fdt_setprop(blob, offset, "interrupts", tmp, len);
	if (err < 0) {
		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
		       "interrupts", name, fdt_strerror(err));
		return 0;
	}

	/*fixup the property of reg*/
	p = (char *)fdt_getprop(blob, offset, "reg", &len);
	if (!p) {
		printf("WARNING: fdt_getprop can't get %s from node %s\n",
		       "reg", name);
		return 0;
	}

	memcpy((char *)tmp, p, len);

	if (rev > REV1_0)
		*((u32 *)tmp + 3) = cpu_to_fdt32(0x1000);
	else
		*((u32 *)tmp + 3) = cpu_to_fdt32(0x8);

	err = fdt_setprop(blob, offset, "reg", tmp, len);
	if (err < 0) {
		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
		       "reg", name, fdt_strerror(err));
		return 0;
	}

	/*fixup the property of compatible*/
	if (rev > REV1_0)
		err = fdt_setprop_string(blob, offset, "compatible",
					 "fsl,ls1043a-v1.1-msi");
	else
		err = fdt_setprop_string(blob, offset, "compatible",
					 "fsl,ls1043a-msi");
	if (err < 0) {
		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
		       "compatible", name, fdt_strerror(err));
		return 0;
	}

	return 1;
}

static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
{
	int offset, len, err;
	void *p;
	int val;
	u32 tmp[4][8];

	offset = fdt_path_offset(blob, name);
	if (offset < 0) {
		printf("WARNING: fdt_path_offset can't find path %s: %s\n",
		       name, fdt_strerror(offset));
		return 0;
	}

	p = (char *)fdt_getprop(blob, offset, "interrupt-map", &len);
	if (!p || len != sizeof(tmp)) {
		printf("WARNING: fdt_getprop can't get %s from node %s\n",
		       "interrupt-map", name);
		return 0;
	}

	memcpy((char *)tmp, p, len);

	val = fdt32_to_cpu(tmp[0][6]);
	if (rev == REV1_0) {
		tmp[1][6] = cpu_to_fdt32(val + 1);
		tmp[2][6] = cpu_to_fdt32(val + 2);
		tmp[3][6] = cpu_to_fdt32(val + 3);
	} else {
		tmp[1][6] = cpu_to_fdt32(val);
		tmp[2][6] = cpu_to_fdt32(val);
		tmp[3][6] = cpu_to_fdt32(val);
	}

	err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
	if (err < 0) {
		printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
		       "interrupt-map", name, fdt_strerror(err));
		return 0;
	}
	return 1;
}

/* Fixup msi node for ls1043a rev1.1*/

static void fdt_fixup_msi(void *blob)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	unsigned int rev;

	rev = gur_in32(&gur->svr);

	if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
		return;

	rev = SVR_REV(rev);

	_fdt_fixup_msi_node(blob, "/soc/msi-controller1@1571000",
			    116, 111, rev);
	_fdt_fixup_msi_node(blob, "/soc/msi-controller2@1572000",
			    126, 121, rev);
	_fdt_fixup_msi_node(blob, "/soc/msi-controller3@1573000",
			    160, 155, rev);

	_fdt_fixup_pci_msi(blob, "/soc/pcie@3400000", rev);
	_fdt_fixup_pci_msi(blob, "/soc/pcie@3500000", rev);
	_fdt_fixup_pci_msi(blob, "/soc/pcie@3600000", rev);
}
#endif

#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/* Remove JR node used by SEC firmware */
void fdt_fixup_remove_jr(void *blob)
{
	int jr_node, addr_cells, len;
	int crypto_node = fdt_path_offset(blob, "crypto");
	u64 jr_offset, used_jr;
	fdt32_t *reg;

	used_jr = sec_firmware_used_jobring_offset();
	fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);

	jr_node = fdt_node_offset_by_compatible(blob, crypto_node,
						"fsl,sec-v4.0-job-ring");

	while (jr_node != -FDT_ERR_NOTFOUND) {
		reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
		jr_offset = fdt_read_number(reg, addr_cells);
		if (jr_offset == used_jr) {
			fdt_del_node(blob, jr_node);
			break;
		}
		jr_node = fdt_node_offset_by_compatible(blob, jr_node,
							"fsl,sec-v4.0-job-ring");
	}
}
#endif

#ifdef CONFIG_ARCH_LS1028A
static void fdt_disable_multimedia(void *blob, unsigned int svr)
{
	int off;

	if (IS_MULTIMEDIA_EN(svr))
		return;

	/* Disable eDP/LCD node */
	off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500");
	if (off != -FDT_ERR_NOTFOUND)
		fdt_status_disabled(blob, off);

	/* Disable GPU node */
	off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
	if (off != -FDT_ERR_NOTFOUND)
		fdt_status_disabled(blob, off);
}
#endif

#ifdef CONFIG_PCIE_ECAM_GENERIC
__weak void fdt_fixup_ecam(void *blob)
{
}
#endif

void ft_cpu_setup(void *blob, bd_t *bd)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	unsigned int svr = gur_in32(&gur->svr);

	/* delete crypto node if not on an E-processor */
	if (!IS_E_PROCESSOR(svr))
		fdt_fixup_crypto_node(blob, 0);
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
	else {
		ccsr_sec_t __iomem *sec;

#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
		fdt_fixup_remove_jr(blob);
		fdt_fixup_kaslr(blob);
#endif

		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
	}
#endif

#ifdef CONFIG_MP
	ft_fixup_cpu(blob);
#endif

#ifdef CONFIG_SYS_NS16550
	do_fixup_by_compat_u32(blob, "fsl,ns16550",
			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif

	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
			     CONFIG_SYS_CLK_FREQ, 1);

#ifdef CONFIG_GIC_V3_ITS
	ls_gic_rd_tables_init(blob);
#endif

#if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
	ft_pci_setup(blob, bd);
#endif

#ifdef CONFIG_FSL_ESDHC
	fdt_fixup_esdhc(blob, bd);
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	fdt_fixup_bportals(blob);
	fdt_fixup_qportals(blob);
	do_fixup_by_compat_u32(blob, "fsl,qman",
			       "clock-frequency", get_qman_freq(), 1);
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	fdt_fixup_fman_firmware(blob);
#endif
#ifndef CONFIG_ARCH_LS1012A
	fsl_fdt_disable_usb(blob);
#endif
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
	fdt_fixup_gic(blob);
#endif
#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
	fdt_fixup_msi(blob);
#endif
#ifdef CONFIG_ARCH_LS1028A
	fdt_disable_multimedia(blob, svr);
#endif
#ifdef CONFIG_PCIE_ECAM_GENERIC
	fdt_fixup_ecam(blob);
#endif
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
40f8dec5	2	/*
9f3183d2	3	* Copyright 2014-2015 Freescale Semiconductor, Inc.
5d3bcdb1	4	* Copyright 2020 NXP
40f8dec5 YS	5	*/
	6
	7	#include <common.h>
d96c2604	8	#include <clock_legacy.h>
5a37a2f0	9	#include <efi_loader.h>
90526e9f	10	#include <asm/cache.h>
b08c8c48	11	#include <linux/libfdt.h>
40f8dec5	12	#include <fdt_support.h>
9f3183d2 MH	13	#include <phy.h>
	14	#ifdef CONFIG_FSL_LSCH3
	15	#include <asm/arch/fdt.h>
	16	#endif
8b06460e YL	17	#ifdef CONFIG_FSL_ESDHC
	18	#include <fsl_esdhc.h>
	19	#endif
0e52b6fe QG	20	#ifdef CONFIG_SYS_DPAA_FMAN
	21	#include <fsl_fman.h>
	22	#endif
9f3183d2 MH	23	#ifdef CONFIG_MP
	24	#include <asm/arch/mp.h>
	25	#endif
f13c99c2 AP	26	#include <fsl_sec.h>
f13c99c2 AP	27	#include <asm/arch-fsl-layerscape/soc.h>
032d5bb4 HZ	28	#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
	29	#include <asm/armv8/sec_firmware.h>
	30	#endif
44262327 AM	31	#include <asm/arch/speed.h>
44262327 AM	32	#include <fsl_qbman.h>
40f8dec5	33
e8297341 SX	34	int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
e8297341 SX	35	{
5d3bcdb1 FI	36	const char *conn;
	37
	38	/* Do NOT apply fixup for backplane modes specified in DT */
	39	if (phyc == PHY_INTERFACE_MODE_XGMII) {
	40	conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
	41	if (is_backplane_mode(conn))
	42	return 0;
	43	}
e8297341 SX	44	return fdt_setprop_string(blob, offset, "phy-connection-type",
	45	phy_string_for_interface(phyc));
	46	}
	47
40f8dec5 YS	48	#ifdef CONFIG_MP
	49	void ft_fixup_cpu(void *blob)
	50	{
	51	int off;
	52	__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
	53	fdt32_t *reg;
	54	int addr_cells;
60385d94	55	u64 val, core_id;
40f8dec5	56	size_t *boot_code_size = &(__secondary_boot_code_size);
20c73051 W	57	u32 mask = cpu_pos_mask();
	58	int off_prev = -1;
	59
	60	off = fdt_path_offset(blob, "/cpus");
	61	if (off < 0) {
	62	puts("couldn't find /cpus node\n");
	63	return;
	64	}
	65
	66	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);
	67
	68	off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
	69	"cpu", 4);
	70	while (off != -FDT_ERR_NOTFOUND) {
	71	reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
	72	if (reg) {
	73	core_id = fdt_read_number(reg, addr_cells);
	74	if (!test_bit(id_to_core(core_id), &mask)) {
	75	fdt_del_node(blob, off);
	76	off = off_prev;
	77	}
	78	}
	79	off_prev = off;
	80	off = fdt_node_offset_by_prop_value(blob, off_prev,
	81	"device_type", "cpu", 4);
	82	}
	83
2d16a1a6	84	#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
daa92644	85	defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
032d5bb4 HZ	86	int node;
	87	u32 psci_ver;
	88
	89	/* Check the psci version to determine if the psci is supported */
	90	psci_ver = sec_firmware_support_psci_version();
	91	if (psci_ver == 0xffffffff) {
	92	/* remove psci DT node */
	93	node = fdt_path_offset(blob, "/psci");
	94	if (node >= 0)
	95	goto remove_psci_node;
	96
	97	node = fdt_node_offset_by_compatible(blob, -1, "arm,psci");
	98	if (node >= 0)
	99	goto remove_psci_node;
	100
	101	node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-0.2");
	102	if (node >= 0)
	103	goto remove_psci_node;
40f8dec5	104
032d5bb4 HZ	105	node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-1.0");
	106	if (node >= 0)
	107	goto remove_psci_node;
	108
	109	remove_psci_node:
	110	if (node >= 0)
	111	fdt_del_node(blob, node);
	112	} else {
	113	return;
	114	}
	115	#endif
40f8dec5 YS	116	off = fdt_path_offset(blob, "/cpus");
	117	if (off < 0) {
	118	puts("couldn't find /cpus node\n");
	119	return;
	120	}
eed36609	121	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);
40f8dec5 YS	122
	123	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
	124	while (off != -FDT_ERR_NOTFOUND) {
	125	reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
	126	if (reg) {
eed36609	127	core_id = fdt_read_number(reg, addr_cells);
60385d94 AB	128	if (core_id == 0 \|\| (is_core_online(core_id))) {
	129	val = spin_tbl_addr;
	130	val += id_to_core(core_id) *
	131	SPIN_TABLE_ELEM_SIZE;
	132	val = cpu_to_fdt64(val);
	133	fdt_setprop_string(blob, off, "enable-method",
	134	"spin-table");
	135	fdt_setprop(blob, off, "cpu-release-addr",
	136	&val, sizeof(val));
	137	} else {
	138	debug("skipping offline core\n");
	139	}
40f8dec5 YS	140	} else {
	141	puts("Warning: found cpu node without reg property\n");
	142	}
	143	off = fdt_node_offset_by_prop_value(blob, off, "device_type",
	144	"cpu", 4);
	145	}
	146
	147	fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
	148	*boot_code_size);
9b5e6396	149	#if CONFIG_IS_ENABLED(EFI_LOADER)
714497e3 MW	150	efi_add_memory_map((uintptr_t)&secondary_boot_code, *boot_code_size,
714497e3 MW	151	EFI_RESERVED_MEMORY_TYPE);
5a37a2f0	152	#endif
40f8dec5 YS	153	}
	154	#endif
	155
c93db4f7 SD	156	void fsl_fdt_disable_usb(void *blob)
	157	{
	158	int off;
	159	/*
	160	* SYSCLK is used as a reference clock for USB. When the USB
	161	* controller is used, SYSCLK must meet the additional requirement
	162	* of 100 MHz.
	163	*/
	164	if (CONFIG_SYS_CLK_FREQ != 100000000) {
	165	off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
	166	while (off != -FDT_ERR_NOTFOUND) {
	167	fdt_status_disabled(blob, off);
	168	off = fdt_node_offset_by_compatible(blob, off,
	169	"snps,dwc3");
	170	}
	171	}
	172	}
	173
fa18ed76 WS	174	#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
	175	static void fdt_fixup_gic(void *blob)
	176	{
	177	int offset, err;
	178	u64 reg[8];
	179	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	180	unsigned int val;
	181	struct ccsr_scfg __iomem scfg = (void )CONFIG_SYS_FSL_SCFG_ADDR;
	182	int align_64k = 0;
	183
	184	val = gur_in32(&gur->svr);
	185
a8f33034	186	if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
fa18ed76 WS	187	align_64k = 1;
	188	} else if (SVR_REV(val) != REV1_0) {
	189	val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
	190	if (!val)
	191	align_64k = 1;
	192	}
	193
	194	offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000");
	195	if (offset < 0) {
	196	printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
	197	"interrupt-controller@1400000", fdt_strerror(offset));
	198	return;
	199	}
	200
	201	/* Fixup gic node align with 64K */
	202	if (align_64k) {
	203	reg[0] = cpu_to_fdt64(GICD_BASE_64K);
	204	reg[1] = cpu_to_fdt64(GICD_SIZE_64K);
	205	reg[2] = cpu_to_fdt64(GICC_BASE_64K);
	206	reg[3] = cpu_to_fdt64(GICC_SIZE_64K);
	207	reg[4] = cpu_to_fdt64(GICH_BASE_64K);
	208	reg[5] = cpu_to_fdt64(GICH_SIZE_64K);
	209	reg[6] = cpu_to_fdt64(GICV_BASE_64K);
	210	reg[7] = cpu_to_fdt64(GICV_SIZE_64K);
	211	} else {
	212	/* Fixup gic node align with default */
	213	reg[0] = cpu_to_fdt64(GICD_BASE);
	214	reg[1] = cpu_to_fdt64(GICD_SIZE);
	215	reg[2] = cpu_to_fdt64(GICC_BASE);
	216	reg[3] = cpu_to_fdt64(GICC_SIZE);
	217	reg[4] = cpu_to_fdt64(GICH_BASE);
	218	reg[5] = cpu_to_fdt64(GICH_SIZE);
	219	reg[6] = cpu_to_fdt64(GICV_BASE);
	220	reg[7] = cpu_to_fdt64(GICV_SIZE);
	221	}
	222
	223	err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
	224	if (err < 0) {
	225	printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
	226	"reg", "interrupt-controller@1400000",
	227	fdt_strerror(err));
	228	return;
	229	}
	230
	231	return;
	232	}
	233	#endif
	234
2ca84bf7 WS	235	#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
	236	static int _fdt_fixup_msi_node(void blob, const char name,
	237	int irq_0, int irq_1, int rev)
	238	{
	239	int err, offset, len;
	240	u32 tmp[4][3];
	241	void *p;
	242
	243	offset = fdt_path_offset(blob, name);
	244	if (offset < 0) {
	245	printf("WARNING: fdt_path_offset can't find path %s: %s\n",
	246	name, fdt_strerror(offset));
	247	return 0;
	248	}
	249
	250	/fixup the property of interrupts/
	251
	252	tmp[0][0] = cpu_to_fdt32(0x0);
	253	tmp[0][1] = cpu_to_fdt32(irq_0);
	254	tmp[0][2] = cpu_to_fdt32(0x4);
	255
	256	if (rev > REV1_0) {
	257	tmp[1][0] = cpu_to_fdt32(0x0);
	258	tmp[1][1] = cpu_to_fdt32(irq_1);
	259	tmp[1][2] = cpu_to_fdt32(0x4);
	260	tmp[2][0] = cpu_to_fdt32(0x0);
	261	tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
	262	tmp[2][2] = cpu_to_fdt32(0x4);
	263	tmp[3][0] = cpu_to_fdt32(0x0);
	264	tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
	265	tmp[3][2] = cpu_to_fdt32(0x4);
	266	len = sizeof(tmp);
	267	} else {
	268	len = sizeof(tmp[0]);
	269	}
	270
	271	err = fdt_setprop(blob, offset, "interrupts", tmp, len);
	272	if (err < 0) {
	273	printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
	274	"interrupts", name, fdt_strerror(err));
	275	return 0;
	276	}
	277
	278	/fixup the property of reg/
	279	p = (char *)fdt_getprop(blob, offset, "reg", &len);
	280	if (!p) {
	281	printf("WARNING: fdt_getprop can't get %s from node %s\n",
	282	"reg", name);
	283	return 0;
	284	}
	285
	286	memcpy((char *)tmp, p, len);
	287
	288	if (rev > REV1_0)
	289	((u32 )tmp + 3) = cpu_to_fdt32(0x1000);
	290	else
	291	((u32 )tmp + 3) = cpu_to_fdt32(0x8);
	292
	293	err = fdt_setprop(blob, offset, "reg", tmp, len);
	294	if (err < 0) {
	295	printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
	296	"reg", name, fdt_strerror(err));
	297	return 0;
	298	}
299
300	/fixup the property of compatible/
301	if (rev > REV1_0)
302	err = fdt_setprop_string(blob, offset, "compatible",
303	"fsl,ls1043a-v1.1-msi");
304	else
305	err = fdt_setprop_string(blob, offset, "compatible",
306	"fsl,ls1043a-msi");
307	if (err < 0) {
308	printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
309	"compatible", name, fdt_strerror(err));
310	return 0;
311	}
312
313	return 1;
314	}
315
316	static int _fdt_fixup_pci_msi(void blob, const char name, int rev)
317	{
318	int offset, len, err;
319	void *p;
320	int val;
321	u32 tmp[4][8];
322
323	offset = fdt_path_offset(blob, name);
324	if (offset < 0) {
325	printf("WARNING: fdt_path_offset can't find path %s: %s\n",
326	name, fdt_strerror(offset));
327	return 0;
328	}
329
330	p = (char *)fdt_getprop(blob, offset, "interrupt-map", &len);
331	if (!p \|\| len != sizeof(tmp)) {
332	printf("WARNING: fdt_getprop can't get %s from node %s\n",
333	"interrupt-map", name);
334	return 0;
335	}
336
337	memcpy((char *)tmp, p, len);
338
339	val = fdt32_to_cpu(tmp[0][6]);
5b994e85	340	if (rev == REV1_0) {
2ca84bf7 WS	341	tmp[1][6] = cpu_to_fdt32(val + 1);
	342	tmp[2][6] = cpu_to_fdt32(val + 2);
	343	tmp[3][6] = cpu_to_fdt32(val + 3);
	344	} else {
	345	tmp[1][6] = cpu_to_fdt32(val);
	346	tmp[2][6] = cpu_to_fdt32(val);
	347	tmp[3][6] = cpu_to_fdt32(val);
	348	}
	349
	350	err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
	351	if (err < 0) {
	352	printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
	353	"interrupt-map", name, fdt_strerror(err));
	354	return 0;
	355	}
	356	return 1;
	357	}
	358
	359	/* Fixup msi node for ls1043a rev1.1*/
	360
	361	static void fdt_fixup_msi(void *blob)
	362	{
	363	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	364	unsigned int rev;
	365
	366	rev = gur_in32(&gur->svr);
	367
a8f33034	368	if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
2ca84bf7 WS	369	return;
	370
	371	rev = SVR_REV(rev);
	372
	373	_fdt_fixup_msi_node(blob, "/soc/msi-controller1@1571000",
	374	116, 111, rev);
	375	_fdt_fixup_msi_node(blob, "/soc/msi-controller2@1572000",
	376	126, 121, rev);
	377	_fdt_fixup_msi_node(blob, "/soc/msi-controller3@1573000",
	378	160, 155, rev);
	379
	380	_fdt_fixup_pci_msi(blob, "/soc/pcie@3400000", rev);
	381	_fdt_fixup_pci_msi(blob, "/soc/pcie@3500000", rev);
	382	_fdt_fixup_pci_msi(blob, "/soc/pcie@3600000", rev);
	383	}
	384	#endif
	385
a797f274 RG	386	#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
	387	/* Remove JR node used by SEC firmware */
	388	void fdt_fixup_remove_jr(void *blob)
	389	{
	390	int jr_node, addr_cells, len;
	391	int crypto_node = fdt_path_offset(blob, "crypto");
	392	u64 jr_offset, used_jr;
	393	fdt32_t *reg;
	394
	395	used_jr = sec_firmware_used_jobring_offset();
	396	fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
	397
	398	jr_node = fdt_node_offset_by_compatible(blob, crypto_node,
	399	"fsl,sec-v4.0-job-ring");
	400
	401	while (jr_node != -FDT_ERR_NOTFOUND) {
	402	reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
	403	jr_offset = fdt_read_number(reg, addr_cells);
	404	if (jr_offset == used_jr) {
	405	fdt_del_node(blob, jr_node);
	406	break;
	407	}
	408	jr_node = fdt_node_offset_by_compatible(blob, jr_node,
	409	"fsl,sec-v4.0-job-ring");
	410	}
	411	}
	412	#endif
	413
54d5c06c YT	414	#ifdef CONFIG_ARCH_LS1028A
	415	static void fdt_disable_multimedia(void *blob, unsigned int svr)
	416	{
	417	int off;
	418
	419	if (IS_MULTIMEDIA_EN(svr))
	420	return;
	421
	422	/* Disable eDP/LCD node */
	423	off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500");
	424	if (off != -FDT_ERR_NOTFOUND)
	425	fdt_status_disabled(blob, off);
	426
	427	/* Disable GPU node */
	428	off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
	429	if (off != -FDT_ERR_NOTFOUND)
	430	fdt_status_disabled(blob, off);
	431	}
	432	#endif
	433
3499dd03 AM	434	#ifdef CONFIG_PCIE_ECAM_GENERIC
	435	__weak void fdt_fixup_ecam(void *blob)
	436	{
	437	}
	438	#endif
	439
40f8dec5 YS	440	void ft_cpu_setup(void blob, bd_t bd)
40f8dec5 YS	441	{
f13c99c2	442	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
a797f274	443	unsigned int svr = gur_in32(&gur->svr);
f13c99c2 AP	444
	445	/* delete crypto node if not on an E-processor */
	446	if (!IS_E_PROCESSOR(svr))
	447	fdt_fixup_crypto_node(blob, 0);
	448	#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
	449	else {
	450	ccsr_sec_t __iomem *sec;
	451
a797f274	452	#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
b6bb93de RG	453	fdt_fixup_remove_jr(blob);
b6bb93de RG	454	fdt_fixup_kaslr(blob);
a797f274 RG	455	#endif
a797f274 RG	456
f13c99c2 AP	457	sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
	458	fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
	459	}
	460	#endif
f13c99c2	461
40f8dec5 YS	462	#ifdef CONFIG_MP
	463	ft_fixup_cpu(blob);
	464	#endif
912cc40f BS	465
912cc40f BS	466	#ifdef CONFIG_SYS_NS16550
1e52835a	467	do_fixup_by_compat_u32(blob, "fsl,ns16550",
912cc40f BS	468	"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
912cc40f BS	469	#endif
8b06460e	470
3d91f46c YL	471	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
3d91f46c YL	472	CONFIG_SYS_CLK_FREQ, 1);
6f14e257	473
f40b120e HZ	474	#ifdef CONFIG_GIC_V3_ITS
	475	ls_gic_rd_tables_init(blob);
	476	#endif
	477
c9ba88ba	478	#if defined(CONFIG_PCIE_LAYERSCAPE) \|\| defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
5be3b44c PK	479	ft_pci_setup(blob, bd);
	480	#endif
	481
9f3183d2	482	#ifdef CONFIG_FSL_ESDHC
8b06460e YL	483	fdt_fixup_esdhc(blob, bd);
8b06460e YL	484	#endif
70e52d21	485
44262327 AM	486	#ifdef CONFIG_SYS_DPAA_QBMAN
	487	fdt_fixup_bportals(blob);
	488	fdt_fixup_qportals(blob);
	489	do_fixup_by_compat_u32(blob, "fsl,qman",
	490	"clock-frequency", get_qman_freq(), 1);
	491	#endif
	492
0e52b6fe QG	493	#ifdef CONFIG_SYS_DPAA_FMAN
	494	fdt_fixup_fman_firmware(blob);
	495	#endif
5436c6a3	496	#ifndef CONFIG_ARCH_LS1012A
c93db4f7	497	fsl_fdt_disable_usb(blob);
132a1468	498	#endif
fa18ed76 WS	499	#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
	500	fdt_fixup_gic(blob);
	501	#endif
2ca84bf7 WS	502	#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
	503	fdt_fixup_msi(blob);
	504	#endif
54d5c06c YT	505	#ifdef CONFIG_ARCH_LS1028A
	506	fdt_disable_multimedia(blob, svr);
	507	#endif
3499dd03 AM	508	#ifdef CONFIG_PCIE_ECAM_GENERIC
	509	fdt_fixup_ecam(blob);
	510	#endif
40f8dec5	511	}