[people/ms/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / lowlevel.S

/*
 * (C) Copyright 2014-2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Extracted from armv8/start.S
 */

#include <config.h>
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif

ENTRY(lowlevel_init)
	mov	x29, lr			/* Save LR */

#ifdef CONFIG_FSL_LSCH3

	/* Set Wuo bit for RN-I 20 */
#ifdef CONFIG_LS2080A
	ldr	x0, =CCI_AUX_CONTROL_BASE(20)
	ldr	x1, =0x00000010
	bl	ccn504_set_aux
#endif

	/* Add fully-coherent masters to DVM domain */
	ldr	x0, =CCI_MN_BASE
	ldr	x1, =CCI_MN_RNF_NODEID_LIST
	ldr	x2, =CCI_MN_DVM_DOMAIN_CTL_SET
	bl	ccn504_add_masters_to_dvm

	/* Set all RN-I ports to QoS of 15 */
	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(0)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(0)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(0)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos

	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(2)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(2)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(2)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos

	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(6)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(6)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(6)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos

	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(12)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(12)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(12)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos

	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(16)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(16)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(16)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos

	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(20)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(20)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(20)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
#endif

#ifdef SMMU_BASE
	/* Set the SMMU page size in the sACR register */
	ldr	x1, =SMMU_BASE
	ldr	w0, [x1, #0x10]
	orr	w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
	str	w0, [x1, #0x10]
#endif

	/* Initialize GIC Secure Bank Status */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
	branch_if_slave x0, 1f
	ldr	x0, =GICD_BASE
	bl	gic_init_secure
1:
#ifdef CONFIG_GICV3
	ldr	x0, =GICR_BASE
	bl	gic_init_secure_percpu
#elif defined(CONFIG_GICV2)
	ldr	x0, =GICD_BASE
	ldr	x1, =GICC_BASE
	bl	gic_init_secure_percpu
#endif
#endif

	branch_if_master x0, x1, 2f

#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
	ldr	x0, =secondary_boot_func
	blr	x0
#endif

2:
#ifdef CONFIG_FSL_TZPC_BP147
	/* Set Non Secure access for all devices protected via TZPC */
	ldr	x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
	orr	w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
	str	w0, [x1]

	isb
	dsb	sy
#endif

#ifdef CONFIG_FSL_TZASC_400
	/* Set TZASC so that:
	 * a. We use only Region0 whose global secure write/read is EN
	 * b. We use only Region0 whose NSAID write/read is EN
	 *
	 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
	 * 	 placeholders.
	 */
	ldr	x1, =TZASC_GATE_KEEPER(0)
	ldr	x0, [x1]		/* Filter 0 Gate Keeper Register */
	orr	x0, x0, #1 << 0		/* Set open_request for Filter 0 */
	str	x0, [x1]

	ldr	x1, =TZASC_GATE_KEEPER(1)
	ldr	x0, [x1]		/* Filter 0 Gate Keeper Register */
	orr	x0, x0, #1 << 0		/* Set open_request for Filter 0 */
	str	x0, [x1]

	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(0)
	ldr	x0, [x1]		/* Region-0 Attributes Register */
	orr	x0, x0, #1 << 31	/* Set Sec global write en, Bit[31] */
	orr	x0, x0, #1 << 30	/* Set Sec global read en, Bit[30] */
	str	x0, [x1]

	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(1)
	ldr	x0, [x1]		/* Region-1 Attributes Register */
	orr	x0, x0, #1 << 31	/* Set Sec global write en, Bit[31] */
	orr	x0, x0, #1 << 30	/* Set Sec global read en, Bit[30] */
	str	x0, [x1]

	ldr	x1, =TZASC_REGION_ID_ACCESS_0(0)
	ldr	w0, [x1]		/* Region-0 Access Register */
	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
	str	w0, [x1]

	ldr	x1, =TZASC_REGION_ID_ACCESS_0(1)
	ldr	w0, [x1]		/* Region-1 Attributes Register */
	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
	str	w0, [x1]

	isb
	dsb	sy
#endif
	mov	lr, x29			/* Restore LR */
	ret
ENDPROC(lowlevel_init)

#ifdef CONFIG_FSL_LSCH3
hnf_pstate_poll:
	/* x0 has the desired status, return 0 for success, 1 for timeout
	 * clobber x1, x2, x3, x4, x6, x7
	 */
	mov	x1, x0
	mov	x7, #0			/* flag for timeout */
	mrs	x3, cntpct_el0		/* read timer */
	add	x3, x3, #1200		/* timeout after 100 microseconds */
	mov	x0, #0x18
	movk	x0, #0x420, lsl #16	/* HNF0_PSTATE_STATUS */
	mov	w6, #8			/* HN-F node count */
1:
	ldr	x2, [x0]
	cmp	x2, x1			/* check status */
	b.eq	2f
	mrs	x4, cntpct_el0
	cmp	x4, x3
	b.ls	1b
	mov	x7, #1			/* timeout */
	b	3f
2:
	add	x0, x0, #0x10000	/* move to next node */
	subs	w6, w6, #1
	cbnz	w6, 1b
3:
	mov	x0, x7
	ret

hnf_set_pstate:
	/* x0 has the desired state, clobber x1, x2, x6 */
	mov	x1, x0
	/* power state to SFONLY */
	mov	w6, #8			/* HN-F node count */
	mov	x0, #0x10
	movk	x0, #0x420, lsl #16	/* HNF0_PSTATE_REQ */
1:	/* set pstate to sfonly */
	ldr	x2, [x0]
	and	x2, x2, #0xfffffffffffffffc	/* & HNFPSTAT_MASK */
	orr	x2, x2, x1
	str	x2, [x0]
	add	x0, x0, #0x10000	/* move to next node */
	subs	w6, w6, #1
	cbnz	w6, 1b

	ret

ENTRY(__asm_flush_l3_cache)
	/*
	 * Return status in x0
	 *    success 0
	 *    tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
	 */
	mov	x29, lr
	mov	x8, #0

	dsb	sy
	mov	x0, #0x1		/* HNFPSTAT_SFONLY */
	bl	hnf_set_pstate

	mov	x0, #0x4		/* SFONLY status */
	bl	hnf_pstate_poll
	cbz	x0, 1f
	mov	x8, #1			/* timeout */
1:
	dsb	sy
	mov	x0, #0x3		/* HNFPSTAT_FAM */
	bl	hnf_set_pstate

	mov	x0, #0xc		/* FAM status */
	bl	hnf_pstate_poll
	cbz	x0, 1f
	add	x8, x8, #0x2
1:
	mov	x0, x8
	mov	lr, x29
	ret
ENDPROC(__asm_flush_l3_cache)
#endif

#ifdef CONFIG_MP
	/* Keep literals not used by the secondary boot code outside it */
	.ltorg

	/* Using 64 bit alignment since the spin table is accessed as data */
	.align 4
	.global secondary_boot_code
	/* Secondary Boot Code starts here */
secondary_boot_code:
	.global __spin_table
__spin_table:
	.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE

	.align 2
ENTRY(secondary_boot_func)
	/*
	 * MPIDR_EL1 Fields:
	 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
	 * MPIDR[7:2] = AFF0_RES
	 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
	 * MPIDR[23:16] = AFF2_CLUSTERID
	 * MPIDR[24] = MT
	 * MPIDR[29:25] = RES0
	 * MPIDR[30] = U
	 * MPIDR[31] = ME
	 * MPIDR[39:32] = AFF3
	 *
	 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
	 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
	 * until AFF2_CLUSTERID and AFF3 have non-zero values)
	 *
	 * LPID = MPIDR[15:8] | MPIDR[1:0]
	 */
	mrs	x0, mpidr_el1
	ubfm	x1, x0, #8, #15
	ubfm	x2, x0, #0, #1
	orr	x10, x2, x1, lsl #2	/* x10 has LPID */
	ubfm    x9, x0, #0, #15         /* x9 contains MPIDR[15:0] */
	/*
	 * offset of the spin table element for this core from start of spin
	 * table (each elem is padded to 64 bytes)
	 */
	lsl	x1, x10, #6
	ldr	x0, =__spin_table
	/* physical address of this cpus spin table element */
	add	x11, x1, x0

	ldr	x0, =__real_cntfrq
	ldr	x0, [x0]
	msr	cntfrq_el0, x0	/* set with real frequency */
	str	x9, [x11, #16]	/* LPID */
	mov	x4, #1
	str	x4, [x11, #8]	/* STATUS */
	dsb	sy
#if defined(CONFIG_GICV3)
	gic_wait_for_interrupt_m x0
#elif defined(CONFIG_GICV2)
        ldr     x0, =GICC_BASE
        gic_wait_for_interrupt_m x0, w1
#endif

	bl secondary_switch_to_el2
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
	bl secondary_switch_to_el1
#endif

slave_cpu:
	wfe
	ldr	x0, [x11]
	cbz	x0, slave_cpu
#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
	mrs     x1, sctlr_el2
#else
	mrs     x1, sctlr_el1
#endif
	tbz     x1, #25, cpu_is_le
	rev     x0, x0                  /* BE to LE conversion */
cpu_is_le:
	br	x0			/* branch to the given address */
ENDPROC(secondary_boot_func)

ENTRY(secondary_switch_to_el2)
	switch_el x0, 1f, 0f, 0f
0:	ret
1:	armv8_switch_to_el2_m x0
ENDPROC(secondary_switch_to_el2)

ENTRY(secondary_switch_to_el1)
	switch_el x0, 0f, 1f, 0f
0:	ret
1:	armv8_switch_to_el1_m x0, x1
ENDPROC(secondary_switch_to_el1)

	/* Ensure that the literals used by the secondary boot code are
	 * assembled within it (this is required so that we can protect
	 * this area with a single memreserve region
	 */
	.ltorg

	/* 64 bit alignment for elements accessed as data */
	.align 4
	.global __real_cntfrq
__real_cntfrq:
	.quad COUNTER_FREQUENCY
	.globl __secondary_boot_code_size
	.type __secondary_boot_code_size, %object
	/* Secondary Boot Code ends here */
__secondary_boot_code_size:
	.quad .-secondary_boot_code
#endif
Commit	Line	Data
2f78eae5	1	/*
9f3183d2	2	* (C) Copyright 2014-2015 Freescale Semiconductor
2f78eae5 YS	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*
	6	* Extracted from armv8/start.S
	7	*/
	8
	9	#include <config.h>
	10	#include <linux/linkage.h>
40f8dec5	11	#include <asm/gic.h>
2f78eae5	12	#include <asm/macro.h>
9f3183d2 MH	13	#ifdef CONFIG_MP
	14	#include <asm/arch/mp.h>
	15	#endif
2f78eae5 YS	16
	17	ENTRY(lowlevel_init)
	18	mov x29, lr /* Save LR */
	19
9f3183d2	20	#ifdef CONFIG_FSL_LSCH3
2b690b98 PK	21
2b690b98 PK	22	/* Set Wuo bit for RN-I 20 */
3c1d218a	23	#ifdef CONFIG_LS2080A
2b690b98 PK	24	ldr x0, =CCI_AUX_CONTROL_BASE(20)
	25	ldr x1, =0x00000010
	26	bl ccn504_set_aux
	27	#endif
	28
07c66000	29	/* Add fully-coherent masters to DVM domain */
3ffa95c2 BS	30	ldr x0, =CCI_MN_BASE
	31	ldr x1, =CCI_MN_RNF_NODEID_LIST
	32	ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
	33	bl ccn504_add_masters_to_dvm
	34
	35	/* Set all RN-I ports to QoS of 15 */
	36	ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
	37	ldr x1, =0x00FF000C
	38	bl ccn504_set_qos
	39	ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
	40	ldr x1, =0x00FF000C
	41	bl ccn504_set_qos
	42	ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
	43	ldr x1, =0x00FF000C
	44	bl ccn504_set_qos
	45
	46	ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
	47	ldr x1, =0x00FF000C
	48	bl ccn504_set_qos
	49	ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
	50	ldr x1, =0x00FF000C
	51	bl ccn504_set_qos
	52	ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
	53	ldr x1, =0x00FF000C
	54	bl ccn504_set_qos
	55
	56	ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
	57	ldr x1, =0x00FF000C
	58	bl ccn504_set_qos
	59	ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
	60	ldr x1, =0x00FF000C
	61	bl ccn504_set_qos
	62	ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
	63	ldr x1, =0x00FF000C
	64	bl ccn504_set_qos
	65
	66	ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
	67	ldr x1, =0x00FF000C
	68	bl ccn504_set_qos
	69	ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
	70	ldr x1, =0x00FF000C
	71	bl ccn504_set_qos
	72	ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
	73	ldr x1, =0x00FF000C
	74	bl ccn504_set_qos
	75
	76	ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
	77	ldr x1, =0x00FF000C
	78	bl ccn504_set_qos
	79	ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
	80	ldr x1, =0x00FF000C
	81	bl ccn504_set_qos
	82	ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
	83	ldr x1, =0x00FF000C
	84	bl ccn504_set_qos
	85
	86	ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
	87	ldr x1, =0x00FF000C
	88	bl ccn504_set_qos
	89	ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
	90	ldr x1, =0x00FF000C
	91	bl ccn504_set_qos
	92	ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
	93	ldr x1, =0x00FF000C
94	bl ccn504_set_qos
9f3183d2	95	#endif
07c66000	96
1e49a231	97	#ifdef SMMU_BASE
2f78eae5 YS	98	/* Set the SMMU page size in the sACR register */
	99	ldr x1, =SMMU_BASE
	100	ldr w0, [x1, #0x10]
	101	orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
	102	str w0, [x1, #0x10]
1e49a231	103	#endif
2f78eae5 YS	104
	105	/* Initialize GIC Secure Bank Status */
	106	#if defined(CONFIG_GICV2) \|\| defined(CONFIG_GICV3)
	107	branch_if_slave x0, 1f
	108	ldr x0, =GICD_BASE
	109	bl gic_init_secure
	110	1:
	111	#ifdef CONFIG_GICV3
	112	ldr x0, =GICR_BASE
	113	bl gic_init_secure_percpu
	114	#elif defined(CONFIG_GICV2)
	115	ldr x0, =GICD_BASE
	116	ldr x1, =GICC_BASE
	117	bl gic_init_secure_percpu
	118	#endif
	119	#endif
	120
40f8dec5	121	branch_if_master x0, x1, 2f
2f78eae5	122
9f3183d2	123	#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
40f8dec5 YS	124	ldr x0, =secondary_boot_func
40f8dec5 YS	125	blr x0
9f3183d2	126	#endif
9c66ce66	127
9f3183d2	128	2:
9c66ce66 BS	129	#ifdef CONFIG_FSL_TZPC_BP147
	130	/* Set Non Secure access for all devices protected via TZPC */
	131	ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
	132	orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
	133	str w0, [x1]
	134
	135	isb
	136	dsb sy
	137	#endif
	138
	139	#ifdef CONFIG_FSL_TZASC_400
	140	/* Set TZASC so that:
	141	* a. We use only Region0 whose global secure write/read is EN
	142	* b. We use only Region0 whose NSAID write/read is EN
	143	*
	144	* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
	145	* placeholders.
	146	*/
	147	ldr x1, =TZASC_GATE_KEEPER(0)
	148	ldr x0, [x1] /* Filter 0 Gate Keeper Register */
	149	orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
	150	str x0, [x1]
	151
	152	ldr x1, =TZASC_GATE_KEEPER(1)
	153	ldr x0, [x1] /* Filter 0 Gate Keeper Register */
	154	orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
	155	str x0, [x1]
	156
	157	ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
	158	ldr x0, [x1] /* Region-0 Attributes Register */
	159	orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
	160	orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
	161	str x0, [x1]
	162
	163	ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
	164	ldr x0, [x1] /* Region-1 Attributes Register */
	165	orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
	166	orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
	167	str x0, [x1]
	168
	169	ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
	170	ldr w0, [x1] /* Region-0 Access Register */
	171	mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
	172	str w0, [x1]
	173
	174	ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
	175	ldr w0, [x1] /* Region-1 Attributes Register */
	176	mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
	177	str w0, [x1]
	178
	179	isb
	180	dsb sy
	181	#endif
40f8dec5 YS	182	mov lr, x29 /* Restore LR */
	183	ret
	184	ENDPROC(lowlevel_init)
	185
b7f2bbff	186	#ifdef CONFIG_FSL_LSCH3
dcd468b8 YS	187	hnf_pstate_poll:
	188	/* x0 has the desired status, return 0 for success, 1 for timeout
	189	* clobber x1, x2, x3, x4, x6, x7
	190	*/
	191	mov x1, x0
	192	mov x7, #0 /* flag for timeout */
	193	mrs x3, cntpct_el0 /* read timer */
	194	add x3, x3, #1200 /* timeout after 100 microseconds */
	195	mov x0, #0x18
	196	movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
	197	mov w6, #8 /* HN-F node count */
	198	1:
	199	ldr x2, [x0]
	200	cmp x2, x1 /* check status */
	201	b.eq 2f
	202	mrs x4, cntpct_el0
	203	cmp x4, x3
	204	b.ls 1b
	205	mov x7, #1 /* timeout */
	206	b 3f
	207	2:
	208	add x0, x0, #0x10000 /* move to next node */
	209	subs w6, w6, #1
	210	cbnz w6, 1b
	211	3:
	212	mov x0, x7
	213	ret
	214
	215	hnf_set_pstate:
	216	/* x0 has the desired state, clobber x1, x2, x6 */
	217	mov x1, x0
	218	/* power state to SFONLY */
	219	mov w6, #8 /* HN-F node count */
	220	mov x0, #0x10
	221	movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
	222	1: /* set pstate to sfonly */
	223	ldr x2, [x0]
	224	and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
	225	orr x2, x2, x1
	226	str x2, [x0]
	227	add x0, x0, #0x10000 /* move to next node */
	228	subs w6, w6, #1
	229	cbnz w6, 1b
	230
	231	ret
	232
	233	ENTRY(__asm_flush_l3_cache)
	234	/*
	235	* Return status in x0
	236	* success 0
	237	* tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
	238	*/
	239	mov x29, lr
	240	mov x8, #0
	241
	242	dsb sy
	243	mov x0, #0x1 /* HNFPSTAT_SFONLY */
	244	bl hnf_set_pstate
	245
	246	mov x0, #0x4 /* SFONLY status */
	247	bl hnf_pstate_poll
	248	cbz x0, 1f
	249	mov x8, #1 /* timeout */
	250	1:
251	dsb sy
252	mov x0, #0x3 /* HNFPSTAT_FAM */
253	bl hnf_set_pstate
254
255	mov x0, #0xc /* FAM status */
256	bl hnf_pstate_poll
257	cbz x0, 1f
258	add x8, x8, #0x2
259	1:
260	mov x0, x8
261	mov lr, x29
262	ret
263	ENDPROC(__asm_flush_l3_cache)
b7f2bbff	264	#endif
dcd468b8	265
9f3183d2	266	#ifdef CONFIG_MP
40f8dec5 YS	267	/* Keep literals not used by the secondary boot code outside it */
	268	.ltorg
	269
	270	/* Using 64 bit alignment since the spin table is accessed as data */
	271	.align 4
	272	.global secondary_boot_code
	273	/* Secondary Boot Code starts here */
	274	secondary_boot_code:
	275	.global __spin_table
	276	__spin_table:
	277	.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
	278
	279	.align 2
	280	ENTRY(secondary_boot_func)
2f78eae5	281	/*
40f8dec5 YS	282	* MPIDR_EL1 Fields:
	283	* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
	284	* MPIDR[7:2] = AFF0_RES
	285	* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
	286	* MPIDR[23:16] = AFF2_CLUSTERID
	287	* MPIDR[24] = MT
	288	* MPIDR[29:25] = RES0
	289	* MPIDR[30] = U
	290	* MPIDR[31] = ME
	291	* MPIDR[39:32] = AFF3
	292	*
	293	* Linear Processor ID (LPID) calculation from MPIDR_EL1:
	294	* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
	295	* until AFF2_CLUSTERID and AFF3 have non-zero values)
	296	*
	297	* LPID = MPIDR[15:8] \| MPIDR[1:0]
2f78eae5	298	*/
40f8dec5 YS	299	mrs x0, mpidr_el1
	300	ubfm x1, x0, #8, #15
	301	ubfm x2, x0, #0, #1
	302	orr x10, x2, x1, lsl #2 /* x10 has LPID */
	303	ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
2f78eae5	304	/*
40f8dec5 YS	305	* offset of the spin table element for this core from start of spin
40f8dec5 YS	306	* table (each elem is padded to 64 bytes)
2f78eae5	307	*/
40f8dec5 YS	308	lsl x1, x10, #6
	309	ldr x0, =__spin_table
	310	/* physical address of this cpus spin table element */
	311	add x11, x1, x0
	312
207774b2 YS	313	ldr x0, =__real_cntfrq
	314	ldr x0, [x0]
	315	msr cntfrq_el0, x0 /* set with real frequency */
40f8dec5 YS	316	str x9, [x11, #16] /* LPID */
	317	mov x4, #1
	318	str x4, [x11, #8] /* STATUS */
	319	dsb sy
	320	#if defined(CONFIG_GICV3)
	321	gic_wait_for_interrupt_m x0
	322	#elif defined(CONFIG_GICV2)
	323	ldr x0, =GICC_BASE
	324	gic_wait_for_interrupt_m x0, w1
	325	#endif
	326
	327	bl secondary_switch_to_el2
2f78eae5	328	#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
40f8dec5	329	bl secondary_switch_to_el1
2f78eae5	330	#endif
2f78eae5	331
40f8dec5 YS	332	slave_cpu:
	333	wfe
	334	ldr x0, [x11]
	335	cbz x0, slave_cpu
	336	#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
	337	mrs x1, sctlr_el2
	338	#else
	339	mrs x1, sctlr_el1
	340	#endif
	341	tbz x1, #25, cpu_is_le
	342	rev x0, x0 /* BE to LE conversion */
	343	cpu_is_le:
	344	br x0 /* branch to the given address */
	345	ENDPROC(secondary_boot_func)
	346
	347	ENTRY(secondary_switch_to_el2)
	348	switch_el x0, 1f, 0f, 0f
	349	0: ret
	350	1: armv8_switch_to_el2_m x0
	351	ENDPROC(secondary_switch_to_el2)
	352
	353	ENTRY(secondary_switch_to_el1)
	354	switch_el x0, 0f, 1f, 0f
	355	0: ret
	356	1: armv8_switch_to_el1_m x0, x1
	357	ENDPROC(secondary_switch_to_el1)
	358
	359	/* Ensure that the literals used by the secondary boot code are
	360	* assembled within it (this is required so that we can protect
	361	* this area with a single memreserve region
	362	*/
	363	.ltorg
	364
	365	/* 64 bit alignment for elements accessed as data */
	366	.align 4
207774b2 YS	367	.global __real_cntfrq
	368	__real_cntfrq:
	369	.quad COUNTER_FREQUENCY
40f8dec5 YS	370	.globl __secondary_boot_code_size
	371	.type __secondary_boot_code_size, %object
	372	/* Secondary Boot Code ends here */
	373	__secondary_boot_code_size:
	374	.quad .-secondary_boot_code
9f3183d2	375	#endif