[people/ms/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / lowlevel.S

/*
 * (C) Copyright 2014-2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Extracted from armv8/start.S
 */

#include <config.h>
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
#ifdef CONFIG_FSL_LSCH3
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#include <asm/arch-fsl-layerscape/soc.h>
#endif
#include <asm/u-boot.h>

ENTRY(lowlevel_init)
	mov	x29, lr			/* Save LR */

#ifdef CONFIG_FSL_LSCH3

	/* Set Wuo bit for RN-I 20 */
#ifdef CONFIG_LS2080A
	ldr	x0, =CCI_AUX_CONTROL_BASE(20)
	ldr	x1, =0x00000010
	bl	ccn504_set_aux
#endif

	/* Add fully-coherent masters to DVM domain */
	ldr	x0, =CCI_MN_BASE
	ldr	x1, =CCI_MN_RNF_NODEID_LIST
	ldr	x2, =CCI_MN_DVM_DOMAIN_CTL_SET
	bl	ccn504_add_masters_to_dvm

	/* Set all RN-I ports to QoS of 15 */
	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(0)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(0)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(0)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos

	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(2)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(2)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(2)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos

	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(6)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(6)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(6)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos

	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(12)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(12)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(12)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos

	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(16)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(16)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(16)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos

	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(20)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(20)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(20)
	ldr	x1, =0x00FF000C
	bl	ccn504_set_qos
#endif

#ifdef SMMU_BASE
	/* Set the SMMU page size in the sACR register */
	ldr	x1, =SMMU_BASE
	ldr	w0, [x1, #0x10]
	orr	w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
	str	w0, [x1, #0x10]
#endif

	/* Initialize GIC Secure Bank Status */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
	branch_if_slave x0, 1f
	ldr	x0, =GICD_BASE
	bl	gic_init_secure
1:
#ifdef CONFIG_GICV3
	ldr	x0, =GICR_BASE
	bl	gic_init_secure_percpu
#elif defined(CONFIG_GICV2)
	ldr	x0, =GICD_BASE
	ldr	x1, =GICC_BASE
	bl	gic_init_secure_percpu
#endif
#endif

	branch_if_master x0, x1, 2f

#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
	ldr	x0, =secondary_boot_func
	blr	x0
#endif

2:
#ifdef CONFIG_FSL_TZPC_BP147
	/* Set Non Secure access for all devices protected via TZPC */
	ldr	x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
	orr	w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
	str	w0, [x1]

	isb
	dsb	sy
#endif

#ifdef CONFIG_FSL_TZASC_400
	/*
	 * LS2080 and its personalities does not support TZASC
	 * So skip TZASC related operations
	 */
	bl	get_svr
	lsr	w0, w0, #16
	ldr	w1, =SVR_DEV_LS2080A
	cmp	w0, w1
	b.eq	1f

	/* Set TZASC so that:
	 * a. We use only Region0 whose global secure write/read is EN
	 * b. We use only Region0 whose NSAID write/read is EN
	 *
	 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
	 * 	 placeholders.
	 */
	ldr	x1, =TZASC_GATE_KEEPER(0)
	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
	str	w0, [x1]

	ldr	x1, =TZASC_GATE_KEEPER(1)
	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
	str	w0, [x1]

	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(0)
	ldr	w0, [x1]		/* Region-0 Attributes Register */
	orr	w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
	orr	w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
	str	w0, [x1]

	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(1)
	ldr	w0, [x1]		/* Region-1 Attributes Register */
	orr	w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
	orr	w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
	str	w0, [x1]

	ldr	x1, =TZASC_REGION_ID_ACCESS_0(0)
	ldr	w0, [x1]		/* Region-0 Access Register */
	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
	str	w0, [x1]

	ldr	x1, =TZASC_REGION_ID_ACCESS_0(1)
	ldr	w0, [x1]		/* Region-1 Attributes Register */
	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
	str	w0, [x1]

	isb
	dsb	sy
#endif
1:
#ifdef CONFIG_ARCH_LS1046A
	/* Initialize the L2 RAM latency */
	mrs   x1, S3_1_c11_c0_2
	mov   x0, #0x1C7
	/* Clear L2 Tag RAM latency and L2 Data RAM latency */
	bic   x1, x1, x0
	/* Set L2 data ram latency bits [2:0] */
	orr   x1, x1, #0x2
	/* set L2 tag ram latency bits [8:6] */
	orr   x1,  x1, #0x80
	msr   S3_1_c11_c0_2, x1
	isb
#endif

	mov	lr, x29			/* Restore LR */
	ret
ENDPROC(lowlevel_init)

#ifdef CONFIG_FSL_LSCH3
	.globl get_svr
get_svr:
	ldr	x1, =FSL_LSCH3_SVR
	ldr	w0, [x1]
	ret

hnf_pstate_poll:
	/* x0 has the desired status, return 0 for success, 1 for timeout
	 * clobber x1, x2, x3, x4, x6, x7
	 */
	mov	x1, x0
	mov	x7, #0			/* flag for timeout */
	mrs	x3, cntpct_el0		/* read timer */
	add	x3, x3, #1200		/* timeout after 100 microseconds */
	mov	x0, #0x18
	movk	x0, #0x420, lsl #16	/* HNF0_PSTATE_STATUS */
	mov	w6, #8			/* HN-F node count */
1:
	ldr	x2, [x0]
	cmp	x2, x1			/* check status */
	b.eq	2f
	mrs	x4, cntpct_el0
	cmp	x4, x3
	b.ls	1b
	mov	x7, #1			/* timeout */
	b	3f
2:
	add	x0, x0, #0x10000	/* move to next node */
	subs	w6, w6, #1
	cbnz	w6, 1b
3:
	mov	x0, x7
	ret

hnf_set_pstate:
	/* x0 has the desired state, clobber x1, x2, x6 */
	mov	x1, x0
	/* power state to SFONLY */
	mov	w6, #8			/* HN-F node count */
	mov	x0, #0x10
	movk	x0, #0x420, lsl #16	/* HNF0_PSTATE_REQ */
1:	/* set pstate to sfonly */
	ldr	x2, [x0]
	and	x2, x2, #0xfffffffffffffffc	/* & HNFPSTAT_MASK */
	orr	x2, x2, x1
	str	x2, [x0]
	add	x0, x0, #0x10000	/* move to next node */
	subs	w6, w6, #1
	cbnz	w6, 1b

	ret

ENTRY(__asm_flush_l3_dcache)
	/*
	 * Return status in x0
	 *    success 0
	 *    tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
	 */
	mov	x29, lr
	mov	x8, #0

	dsb	sy
	mov	x0, #0x1		/* HNFPSTAT_SFONLY */
	bl	hnf_set_pstate

	mov	x0, #0x4		/* SFONLY status */
	bl	hnf_pstate_poll
	cbz	x0, 1f
	mov	x8, #1			/* timeout */
1:
	dsb	sy
	mov	x0, #0x3		/* HNFPSTAT_FAM */
	bl	hnf_set_pstate

	mov	x0, #0xc		/* FAM status */
	bl	hnf_pstate_poll
	cbz	x0, 1f
	add	x8, x8, #0x2
1:
	mov	x0, x8
	mov	lr, x29
	ret
ENDPROC(__asm_flush_l3_dcache)
#endif

#ifdef CONFIG_MP
	/* Keep literals not used by the secondary boot code outside it */
	.ltorg

	/* Using 64 bit alignment since the spin table is accessed as data */
	.align 4
	.global secondary_boot_code
	/* Secondary Boot Code starts here */
secondary_boot_code:
	.global __spin_table
__spin_table:
	.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE

	.align 2
ENTRY(secondary_boot_func)
	/*
	 * MPIDR_EL1 Fields:
	 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
	 * MPIDR[7:2] = AFF0_RES
	 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
	 * MPIDR[23:16] = AFF2_CLUSTERID
	 * MPIDR[24] = MT
	 * MPIDR[29:25] = RES0
	 * MPIDR[30] = U
	 * MPIDR[31] = ME
	 * MPIDR[39:32] = AFF3
	 *
	 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
	 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
	 * until AFF2_CLUSTERID and AFF3 have non-zero values)
	 *
	 * LPID = MPIDR[15:8] | MPIDR[1:0]
	 */
	mrs	x0, mpidr_el1
	ubfm	x1, x0, #8, #15
	ubfm	x2, x0, #0, #1
	orr	x10, x2, x1, lsl #2	/* x10 has LPID */
	ubfm    x9, x0, #0, #15         /* x9 contains MPIDR[15:0] */
	/*
	 * offset of the spin table element for this core from start of spin
	 * table (each elem is padded to 64 bytes)
	 */
	lsl	x1, x10, #6
	ldr	x0, =__spin_table
	/* physical address of this cpus spin table element */
	add	x11, x1, x0

	ldr	x0, =__real_cntfrq
	ldr	x0, [x0]
	msr	cntfrq_el0, x0	/* set with real frequency */
	str	x9, [x11, #16]	/* LPID */
	mov	x4, #1
	str	x4, [x11, #8]	/* STATUS */
	dsb	sy
#if defined(CONFIG_GICV3)
	gic_wait_for_interrupt_m x0
#elif defined(CONFIG_GICV2)
        ldr     x0, =GICC_BASE
        gic_wait_for_interrupt_m x0, w1
#endif

slave_cpu:
	wfe
	ldr	x0, [x11]
	cbz	x0, slave_cpu
#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
	mrs     x1, sctlr_el2
#else
	mrs     x1, sctlr_el1
#endif
	tbz     x1, #25, cpu_is_le
	rev     x0, x0                  /* BE to LE conversion */
cpu_is_le:
	ldr	x5, [x11, #24]
	ldr	x6, =IH_ARCH_DEFAULT
	cmp	x6, x5
	b.eq	1f

#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
	adr	x3, secondary_switch_to_el1
	ldr	x4, =ES_TO_AARCH64
#else
	ldr	x3, [x11]
	ldr	x4, =ES_TO_AARCH32
#endif
	bl	secondary_switch_to_el2

1:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
	adr	x3, secondary_switch_to_el1
#else
	ldr	x3, [x11]
#endif
	ldr	x4, =ES_TO_AARCH64
	bl	secondary_switch_to_el2

ENDPROC(secondary_boot_func)

ENTRY(secondary_switch_to_el2)
	switch_el x5, 1f, 0f, 0f
0:	ret
1:	armv8_switch_to_el2_m x3, x4, x5
ENDPROC(secondary_switch_to_el2)

ENTRY(secondary_switch_to_el1)
	mrs	x0, mpidr_el1
	ubfm	x1, x0, #8, #15
	ubfm	x2, x0, #0, #1
	orr	x10, x2, x1, lsl #2	/* x10 has LPID */

	lsl	x1, x10, #6
	ldr	x0, =__spin_table
	/* physical address of this cpus spin table element */
	add	x11, x1, x0

	ldr	x3, [x11]

	ldr	x5, [x11, #24]
	ldr	x6, =IH_ARCH_DEFAULT
	cmp	x6, x5
	b.eq	2f

	ldr	x4, =ES_TO_AARCH32
	bl	switch_to_el1

2:	ldr	x4, =ES_TO_AARCH64

switch_to_el1:
	switch_el x5, 0f, 1f, 0f
0:	ret
1:	armv8_switch_to_el1_m x3, x4, x5
ENDPROC(secondary_switch_to_el1)

	/* Ensure that the literals used by the secondary boot code are
	 * assembled within it (this is required so that we can protect
	 * this area with a single memreserve region
	 */
	.ltorg

	/* 64 bit alignment for elements accessed as data */
	.align 4
	.global __real_cntfrq
__real_cntfrq:
	.quad COUNTER_FREQUENCY
	.globl __secondary_boot_code_size
	.type __secondary_boot_code_size, %object
	/* Secondary Boot Code ends here */
__secondary_boot_code_size:
	.quad .-secondary_boot_code
#endif
Commit	Line	Data
2f78eae5	1	/*
9f3183d2	2	* (C) Copyright 2014-2015 Freescale Semiconductor
2f78eae5 YS	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*
	6	* Extracted from armv8/start.S
	7	*/
	8
	9	#include <config.h>
	10	#include <linux/linkage.h>
40f8dec5	11	#include <asm/gic.h>
2f78eae5	12	#include <asm/macro.h>
9f3183d2 MH	13	#ifdef CONFIG_MP
	14	#include <asm/arch/mp.h>
	15	#endif
f6a70b3a PJ	16	#ifdef CONFIG_FSL_LSCH3
f6a70b3a PJ	17	#include <asm/arch-fsl-layerscape/immap_lsch3.h>
d5df606d	18	#include <asm/arch-fsl-layerscape/soc.h>
f6a70b3a	19	#endif
ec6617c3	20	#include <asm/u-boot.h>
2f78eae5 YS	21
	22	ENTRY(lowlevel_init)
	23	mov x29, lr /* Save LR */
	24
9f3183d2	25	#ifdef CONFIG_FSL_LSCH3
2b690b98 PK	26
2b690b98 PK	27	/* Set Wuo bit for RN-I 20 */
3c1d218a	28	#ifdef CONFIG_LS2080A
2b690b98 PK	29	ldr x0, =CCI_AUX_CONTROL_BASE(20)
	30	ldr x1, =0x00000010
	31	bl ccn504_set_aux
	32	#endif
	33
07c66000	34	/* Add fully-coherent masters to DVM domain */
3ffa95c2 BS	35	ldr x0, =CCI_MN_BASE
	36	ldr x1, =CCI_MN_RNF_NODEID_LIST
	37	ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
	38	bl ccn504_add_masters_to_dvm
	39
	40	/* Set all RN-I ports to QoS of 15 */
	41	ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
	42	ldr x1, =0x00FF000C
	43	bl ccn504_set_qos
	44	ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
	45	ldr x1, =0x00FF000C
	46	bl ccn504_set_qos
	47	ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
	48	ldr x1, =0x00FF000C
	49	bl ccn504_set_qos
	50
	51	ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
	52	ldr x1, =0x00FF000C
	53	bl ccn504_set_qos
	54	ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
	55	ldr x1, =0x00FF000C
	56	bl ccn504_set_qos
	57	ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
	58	ldr x1, =0x00FF000C
	59	bl ccn504_set_qos
	60
	61	ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
	62	ldr x1, =0x00FF000C
	63	bl ccn504_set_qos
	64	ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
	65	ldr x1, =0x00FF000C
	66	bl ccn504_set_qos
	67	ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
	68	ldr x1, =0x00FF000C
	69	bl ccn504_set_qos
	70
	71	ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
	72	ldr x1, =0x00FF000C
	73	bl ccn504_set_qos
	74	ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
	75	ldr x1, =0x00FF000C
	76	bl ccn504_set_qos
	77	ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
	78	ldr x1, =0x00FF000C
	79	bl ccn504_set_qos
	80
	81	ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
	82	ldr x1, =0x00FF000C
	83	bl ccn504_set_qos
	84	ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
	85	ldr x1, =0x00FF000C
	86	bl ccn504_set_qos
	87	ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
	88	ldr x1, =0x00FF000C
	89	bl ccn504_set_qos
	90
	91	ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
	92	ldr x1, =0x00FF000C
	93	bl ccn504_set_qos
	94	ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
	95	ldr x1, =0x00FF000C
	96	bl ccn504_set_qos
	97	ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
	98	ldr x1, =0x00FF000C
99	bl ccn504_set_qos
9f3183d2	100	#endif
07c66000	101
1e49a231	102	#ifdef SMMU_BASE
2f78eae5 YS	103	/* Set the SMMU page size in the sACR register */
	104	ldr x1, =SMMU_BASE
	105	ldr w0, [x1, #0x10]
	106	orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
	107	str w0, [x1, #0x10]
1e49a231	108	#endif
2f78eae5 YS	109
	110	/* Initialize GIC Secure Bank Status */
	111	#if defined(CONFIG_GICV2) \|\| defined(CONFIG_GICV3)
	112	branch_if_slave x0, 1f
	113	ldr x0, =GICD_BASE
	114	bl gic_init_secure
	115	1:
	116	#ifdef CONFIG_GICV3
	117	ldr x0, =GICR_BASE
	118	bl gic_init_secure_percpu
	119	#elif defined(CONFIG_GICV2)
	120	ldr x0, =GICD_BASE
	121	ldr x1, =GICC_BASE
	122	bl gic_init_secure_percpu
	123	#endif
	124	#endif
	125
40f8dec5	126	branch_if_master x0, x1, 2f
2f78eae5	127
9f3183d2	128	#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
40f8dec5 YS	129	ldr x0, =secondary_boot_func
40f8dec5 YS	130	blr x0
9f3183d2	131	#endif
9c66ce66	132
9f3183d2	133	2:
9c66ce66 BS	134	#ifdef CONFIG_FSL_TZPC_BP147
	135	/* Set Non Secure access for all devices protected via TZPC */
	136	ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
	137	orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
	138	str w0, [x1]
	139
	140	isb
	141	dsb sy
	142	#endif
	143
	144	#ifdef CONFIG_FSL_TZASC_400
d5df606d PJ	145	/*
	146	* LS2080 and its personalities does not support TZASC
	147	* So skip TZASC related operations
	148	*/
	149	bl get_svr
	150	lsr w0, w0, #16
	151	ldr w1, =SVR_DEV_LS2080A
	152	cmp w0, w1
	153	b.eq 1f
	154
9c66ce66 BS	155	/* Set TZASC so that:
	156	* a. We use only Region0 whose global secure write/read is EN
	157	* b. We use only Region0 whose NSAID write/read is EN
	158	*
	159	* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
	160	* placeholders.
	161	*/
	162	ldr x1, =TZASC_GATE_KEEPER(0)
7cfbb4ab PJ	163	ldr w0, [x1] /* Filter 0 Gate Keeper Register */
	164	orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
	165	str w0, [x1]
9c66ce66 BS	166
9c66ce66 BS	167	ldr x1, =TZASC_GATE_KEEPER(1)
7cfbb4ab PJ	168	ldr w0, [x1] /* Filter 0 Gate Keeper Register */
	169	orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
	170	str w0, [x1]
9c66ce66 BS	171
9c66ce66 BS	172	ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
7cfbb4ab PJ	173	ldr w0, [x1] /* Region-0 Attributes Register */
	174	orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
	175	orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
	176	str w0, [x1]
9c66ce66 BS	177
9c66ce66 BS	178	ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
7cfbb4ab PJ	179	ldr w0, [x1] /* Region-1 Attributes Register */
	180	orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
	181	orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
	182	str w0, [x1]
9c66ce66 BS	183
	184	ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
	185	ldr w0, [x1] /* Region-0 Access Register */
	186	mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
	187	str w0, [x1]
	188
	189	ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
	190	ldr w0, [x1] /* Region-1 Attributes Register */
	191	mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
	192	str w0, [x1]
	193
	194	isb
	195	dsb sy
	196	#endif
d5df606d	197	1:
da28e58a	198	#ifdef CONFIG_ARCH_LS1046A
13f79880 MH	199	/* Initialize the L2 RAM latency */
	200	mrs x1, S3_1_c11_c0_2
	201	mov x0, #0x1C7
	202	/* Clear L2 Tag RAM latency and L2 Data RAM latency */
	203	bic x1, x1, x0
	204	/* Set L2 data ram latency bits [2:0] */
	205	orr x1, x1, #0x2
	206	/* set L2 tag ram latency bits [8:6] */
	207	orr x1, x1, #0x80
	208	msr S3_1_c11_c0_2, x1
	209	isb
	210	#endif
	211
40f8dec5 YS	212	mov lr, x29 /* Restore LR */
	213	ret
	214	ENDPROC(lowlevel_init)
	215
b7f2bbff	216	#ifdef CONFIG_FSL_LSCH3
f6a70b3a PJ	217	.globl get_svr
	218	get_svr:
	219	ldr x1, =FSL_LSCH3_SVR
	220	ldr w0, [x1]
	221	ret
	222
dcd468b8 YS	223	hnf_pstate_poll:
	224	/* x0 has the desired status, return 0 for success, 1 for timeout
	225	* clobber x1, x2, x3, x4, x6, x7
	226	*/
	227	mov x1, x0
	228	mov x7, #0 /* flag for timeout */
	229	mrs x3, cntpct_el0 /* read timer */
	230	add x3, x3, #1200 /* timeout after 100 microseconds */
	231	mov x0, #0x18
	232	movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
	233	mov w6, #8 /* HN-F node count */
	234	1:
	235	ldr x2, [x0]
	236	cmp x2, x1 /* check status */
	237	b.eq 2f
	238	mrs x4, cntpct_el0
	239	cmp x4, x3
	240	b.ls 1b
	241	mov x7, #1 /* timeout */
	242	b 3f
	243	2:
	244	add x0, x0, #0x10000 /* move to next node */
	245	subs w6, w6, #1
	246	cbnz w6, 1b
	247	3:
	248	mov x0, x7
	249	ret
	250
	251	hnf_set_pstate:
	252	/* x0 has the desired state, clobber x1, x2, x6 */
	253	mov x1, x0
	254	/* power state to SFONLY */
	255	mov w6, #8 /* HN-F node count */
	256	mov x0, #0x10
	257	movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
	258	1: /* set pstate to sfonly */
	259	ldr x2, [x0]
	260	and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
	261	orr x2, x2, x1
	262	str x2, [x0]
	263	add x0, x0, #0x10000 /* move to next node */
	264	subs w6, w6, #1
	265	cbnz w6, 1b
	266
	267	ret
	268
1ab557a0	269	ENTRY(__asm_flush_l3_dcache)
dcd468b8 YS	270	/*
	271	* Return status in x0
	272	* success 0
	273	* tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
	274	*/
	275	mov x29, lr
	276	mov x8, #0
	277
	278	dsb sy
	279	mov x0, #0x1 /* HNFPSTAT_SFONLY */
	280	bl hnf_set_pstate
	281
	282	mov x0, #0x4 /* SFONLY status */
	283	bl hnf_pstate_poll
	284	cbz x0, 1f
	285	mov x8, #1 /* timeout */
	286	1:
	287	dsb sy
	288	mov x0, #0x3 /* HNFPSTAT_FAM */
	289	bl hnf_set_pstate
	290
	291	mov x0, #0xc /* FAM status */
	292	bl hnf_pstate_poll
	293	cbz x0, 1f
	294	add x8, x8, #0x2
	295	1:
	296	mov x0, x8
	297	mov lr, x29
	298	ret
1ab557a0	299	ENDPROC(__asm_flush_l3_dcache)
b7f2bbff	300	#endif
dcd468b8	301
9f3183d2	302	#ifdef CONFIG_MP
40f8dec5 YS	303	/* Keep literals not used by the secondary boot code outside it */
	304	.ltorg
	305
	306	/* Using 64 bit alignment since the spin table is accessed as data */
	307	.align 4
	308	.global secondary_boot_code
	309	/* Secondary Boot Code starts here */
	310	secondary_boot_code:
	311	.global __spin_table
	312	__spin_table:
	313	.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
	314
	315	.align 2
	316	ENTRY(secondary_boot_func)
2f78eae5	317	/*
40f8dec5 YS	318	* MPIDR_EL1 Fields:
	319	* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
	320	* MPIDR[7:2] = AFF0_RES
	321	* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
	322	* MPIDR[23:16] = AFF2_CLUSTERID
	323	* MPIDR[24] = MT
	324	* MPIDR[29:25] = RES0
	325	* MPIDR[30] = U
	326	* MPIDR[31] = ME
	327	* MPIDR[39:32] = AFF3
	328	*
	329	* Linear Processor ID (LPID) calculation from MPIDR_EL1:
	330	* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
	331	* until AFF2_CLUSTERID and AFF3 have non-zero values)
	332	*
	333	* LPID = MPIDR[15:8] \| MPIDR[1:0]
2f78eae5	334	*/
40f8dec5 YS	335	mrs x0, mpidr_el1
	336	ubfm x1, x0, #8, #15
	337	ubfm x2, x0, #0, #1
	338	orr x10, x2, x1, lsl #2 /* x10 has LPID */
	339	ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
2f78eae5	340	/*
40f8dec5 YS	341	* offset of the spin table element for this core from start of spin
40f8dec5 YS	342	* table (each elem is padded to 64 bytes)
2f78eae5	343	*/
40f8dec5 YS	344	lsl x1, x10, #6
	345	ldr x0, =__spin_table
	346	/* physical address of this cpus spin table element */
	347	add x11, x1, x0
	348
207774b2 YS	349	ldr x0, =__real_cntfrq
	350	ldr x0, [x0]
	351	msr cntfrq_el0, x0 /* set with real frequency */
40f8dec5 YS	352	str x9, [x11, #16] /* LPID */
	353	mov x4, #1
	354	str x4, [x11, #8] /* STATUS */
	355	dsb sy
	356	#if defined(CONFIG_GICV3)
	357	gic_wait_for_interrupt_m x0
	358	#elif defined(CONFIG_GICV2)
	359	ldr x0, =GICC_BASE
	360	gic_wait_for_interrupt_m x0, w1
	361	#endif
	362
40f8dec5 YS	363	slave_cpu:
	364	wfe
	365	ldr x0, [x11]
	366	cbz x0, slave_cpu
	367	#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
	368	mrs x1, sctlr_el2
	369	#else
	370	mrs x1, sctlr_el1
	371	#endif
	372	tbz x1, #25, cpu_is_le
	373	rev x0, x0 /* BE to LE conversion */
	374	cpu_is_le:
ec6617c3 AW	375	ldr x5, [x11, #24]
	376	ldr x6, =IH_ARCH_DEFAULT
	377	cmp x6, x5
	378	b.eq 1f
	379
	380	#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
	381	adr x3, secondary_switch_to_el1
	382	ldr x4, =ES_TO_AARCH64
	383	#else
	384	ldr x3, [x11]
	385	ldr x4, =ES_TO_AARCH32
	386	#endif
	387	bl secondary_switch_to_el2
	388
	389	1:
	390	#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
	391	adr x3, secondary_switch_to_el1
	392	#else
	393	ldr x3, [x11]
	394	#endif
	395	ldr x4, =ES_TO_AARCH64
	396	bl secondary_switch_to_el2
	397
40f8dec5 YS	398	ENDPROC(secondary_boot_func)
	399
	400	ENTRY(secondary_switch_to_el2)
ec6617c3	401	switch_el x5, 1f, 0f, 0f
40f8dec5	402	0: ret
ec6617c3	403	1: armv8_switch_to_el2_m x3, x4, x5
40f8dec5 YS	404	ENDPROC(secondary_switch_to_el2)
	405
	406	ENTRY(secondary_switch_to_el1)
ec6617c3 AW	407	mrs x0, mpidr_el1
	408	ubfm x1, x0, #8, #15
	409	ubfm x2, x0, #0, #1
	410	orr x10, x2, x1, lsl #2 /* x10 has LPID */
	411
	412	lsl x1, x10, #6
	413	ldr x0, =__spin_table
	414	/* physical address of this cpus spin table element */
	415	add x11, x1, x0
	416
	417	ldr x3, [x11]
	418
	419	ldr x5, [x11, #24]
	420	ldr x6, =IH_ARCH_DEFAULT
	421	cmp x6, x5
	422	b.eq 2f
	423
	424	ldr x4, =ES_TO_AARCH32
	425	bl switch_to_el1
	426
	427	2: ldr x4, =ES_TO_AARCH64
	428
	429	switch_to_el1:
	430	switch_el x5, 0f, 1f, 0f
40f8dec5	431	0: ret
ec6617c3	432	1: armv8_switch_to_el1_m x3, x4, x5
40f8dec5 YS	433	ENDPROC(secondary_switch_to_el1)
	434
	435	/* Ensure that the literals used by the secondary boot code are
	436	* assembled within it (this is required so that we can protect
	437	* this area with a single memreserve region
	438	*/
	439	.ltorg
	440
	441	/* 64 bit alignment for elements accessed as data */
	442	.align 4
207774b2 YS	443	.global __real_cntfrq
	444	__real_cntfrq:
	445	.quad COUNTER_FREQUENCY
40f8dec5 YS	446	.globl __secondary_boot_code_size
	447	.type __secondary_boot_code_size, %object
	448	/* Secondary Boot Code ends here */
	449	__secondary_boot_code_size:
	450	.quad .-secondary_boot_code
9f3183d2	451	#endif