[people/ms/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / soc.c

/*
 * Copyright 2014-2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fsl_immap.h>
#include <fsl_ifc.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
#include <fsl_csu.h>
#endif
#ifdef CONFIG_SYS_FSL_DDR
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
#endif
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
#include <fsl_immap.h>

DECLARE_GLOBAL_DATA_PTR;

bool soc_has_dp_ddr(void)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	u32 svr = gur_in32(&gur->svr);

	/* LS2085A, LS2088A, LS2048A has DP_DDR */
	if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
	    (SVR_SOC_VER(svr) == SVR_LS2088A) ||
	    (SVR_SOC_VER(svr) == SVR_LS2048A))
		return true;

	return false;
}

bool soc_has_aiop(void)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	u32 svr = gur_in32(&gur->svr);

	/* LS2085A has AIOP */
	if (SVR_SOC_VER(svr) == SVR_LS2085A)
		return true;

	return false;
}

static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
{
	scfg_clrsetbits32(scfg + offset / 4,
			0xF << 6,
			SCFG_USB_TXVREFTUNE << 6);
}

static void erratum_a009008(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;

#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
#elif defined(CONFIG_ARCH_LS2080A)
	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}

static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
{
	scfg_clrbits32(scfg + offset / 4,
			SCFG_USB_SQRXTUNE_MASK << 23);
}

static void erratum_a009798(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;

#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
#elif defined(CONFIG_ARCH_LS2080A)
	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}

#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
{
	scfg_clrsetbits32(scfg + offset / 4,
			0x7F << 9,
			SCFG_USB_PCSTXSWINGFULL << 9);
}
#endif

static void erratum_a008997(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;

	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}

#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)

#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)	\
	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);	\
	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);	\
	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);	\
	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)

#elif defined(CONFIG_ARCH_LS2080A)

#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)	\
	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)

#endif

static void erratum_a009007(void)
{
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
	void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;

	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);

	usb_phy = (void __iomem *)SCFG_USB_PHY2;
	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);

	usb_phy = (void __iomem *)SCFG_USB_PHY3;
	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
#elif defined(CONFIG_ARCH_LS2080A)
	void __iomem *dcsr = (void __iomem *)DCSR_BASE;

	PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
	PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
}

#if defined(CONFIG_FSL_LSCH3)
/*
 * This erratum requires setting a value to eddrtqcr1 to
 * optimal the DDR performance.
 */
static void erratum_a008336(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
	u32 *eddrtqcr1;

#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
	if (fsl_ddr_get_version(0) == 0x50200)
		out_le32(eddrtqcr1, 0x63b30002);
#endif
#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
	if (fsl_ddr_get_version(0) == 0x50200)
		out_le32(eddrtqcr1, 0x63b30002);
#endif
#endif
}

/*
 * This erratum requires a register write before being Memory
 * controller 3 being enabled.
 */
static void erratum_a008514(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
	u32 *eddrtqcr1;

#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
	out_le32(eddrtqcr1, 0x63b20002);
#endif
#endif
}
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
#define PLATFORM_CYCLE_ENV_VAR	"a009635_interval_val"

static unsigned long get_internval_val_mhz(void)
{
	char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
	/*
	 *  interval is the number of platform cycles(MHz) between
	 *  wake up events generated by EPU.
	 */
	ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);

	if (interval)
		interval_mhz = simple_strtoul(interval, NULL, 10);

	return interval_mhz;
}

void erratum_a009635(void)
{
	u32 val;
	unsigned long interval_mhz = get_internval_val_mhz();

	if (!interval_mhz)
		return;

	val = in_le32(DCSR_CGACRE5);
	writel(val | 0x00000200, DCSR_CGACRE5);

	val = in_le32(EPU_EPCMPR5);
	writel(interval_mhz, EPU_EPCMPR5);
	val = in_le32(EPU_EPCCR5);
	writel(val | 0x82820000, EPU_EPCCR5);
	val = in_le32(EPU_EPSMCR5);
	writel(val | 0x002f0000, EPU_EPSMCR5);
	val = in_le32(EPU_EPECR5);
	writel(val | 0x20000000, EPU_EPECR5);
	val = in_le32(EPU_EPGCR);
	writel(val | 0x80000000, EPU_EPGCR);
}
#endif	/* CONFIG_SYS_FSL_ERRATUM_A009635 */

static void erratum_rcw_src(void)
{
#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
	u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
	u32 val;

	val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
	val &= ~DCFG_PORSR1_RCW_SRC;
	val |= DCFG_PORSR1_RCW_SRC_NOR;
	out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
#endif
}

#define I2C_DEBUG_REG 0x6
#define I2C_GLITCH_EN 0x8
/*
 * This erratum requires setting glitch_en bit to enable
 * digital glitch filter to improve clock stability.
 */
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
static void erratum_a009203(void)
{
	u8 __iomem *ptr;
#ifdef CONFIG_SYS_I2C
#ifdef I2C1_BASE_ADDR
	ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);

	writeb(I2C_GLITCH_EN, ptr);
#endif
#ifdef I2C2_BASE_ADDR
	ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);

	writeb(I2C_GLITCH_EN, ptr);
#endif
#ifdef I2C3_BASE_ADDR
	ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);

	writeb(I2C_GLITCH_EN, ptr);
#endif
#ifdef I2C4_BASE_ADDR
	ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);

	writeb(I2C_GLITCH_EN, ptr);
#endif
#endif
}
#endif

void bypass_smmu(void)
{
	u32 val;
	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
	out_le32(SMMU_SCR0, val);
	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
	out_le32(SMMU_NSCR0, val);
}
void fsl_lsch3_early_init_f(void)
{
	erratum_rcw_src();
#ifdef CONFIG_FSL_IFC
	init_early_memctl_regs();	/* tighten IFC timing */
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
	erratum_a009203();
#endif
	erratum_a008514();
	erratum_a008336();
	erratum_a009008();
	erratum_a009798();
	erratum_a008997();
	erratum_a009007();
#ifdef CONFIG_CHAIN_OF_TRUST
	/* In case of Secure Boot, the IBR configures the SMMU
	* to allow only Secure transactions.
	* SMMU must be reset in bypass mode.
	* Set the ClientPD bit and Clear the USFCFG Bit
	*/
	if (fsl_check_boot_mode_secure() == 1)
		bypass_smmu();
#endif
}

#ifdef CONFIG_SCSI_AHCI_PLAT
int sata_init(void)
{
	struct ccsr_ahci __iomem *ccsr_ahci;

#ifdef CONFIG_SYS_SATA2
	ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
#endif

#ifdef CONFIG_SYS_SATA1
	ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);

	ahci_init((void __iomem *)CONFIG_SYS_SATA1);
	scsi_scan(false);
#endif

	return 0;
}
#endif

#elif defined(CONFIG_FSL_LSCH2)
#ifdef CONFIG_SCSI_AHCI_PLAT
int sata_init(void)
{
	struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;

	/* Disable SATA ECC */
	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);

	ahci_init((void __iomem *)CONFIG_SYS_SATA);
	scsi_scan(false);

	return 0;
}
#endif

static void erratum_a009929(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
	struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
	u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
	u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);

	rstrqmr1 |= 0x00000400;
	gur_out32(&gur->rstrqmr1, rstrqmr1);
	writel(0x01000000, dcsr_cop_ccp);
#endif
}

/*
 * This erratum requires setting a value to eddrtqcr1 to optimal
 * the DDR performance. The eddrtqcr1 register is in SCFG space
 * of LS1043A and the offset is 0x157_020c.
 */
#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
	&& defined(CONFIG_SYS_FSL_ERRATUM_A008514)
#error A009660 and A008514 can not be both enabled.
#endif

static void erratum_a009660(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
	u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
	out_be32(eddrtqcr1, 0x63b20042);
#endif
}

static void erratum_a008850_early(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
	/* part 1 of 2 */
	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
						CONFIG_SYS_CCI400_OFFSET);
	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;

	/* Skip if running at lower exception level */
	if (current_el() < 3)
		return;

	/* disables propagation of barrier transactions to DDRC from CCI400 */
	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);

	/* disable the re-ordering in DDRC */
	ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
#endif
}

void erratum_a008850_post(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
	/* part 2 of 2 */
	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
						CONFIG_SYS_CCI400_OFFSET);
	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
	u32 tmp;

	/* Skip if running at lower exception level */
	if (current_el() < 3)
		return;

	/* enable propagation of barrier transactions to DDRC from CCI400 */
	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);

	/* enable the re-ordering in DDRC */
	tmp = ddr_in32(&ddr->eor);
	tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
	ddr_out32(&ddr->eor, tmp);
#endif
}

#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
void erratum_a010315(void)
{
	int i;

	for (i = PCIE1; i <= PCIE4; i++)
		if (!is_serdes_configured(i)) {
			debug("PCIe%d: disabled all R/W permission!\n", i);
			set_pcie_ns_access(i, 0);
		}
}
#endif

static void erratum_a010539(void)
{
#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	u32 porsr1;

	porsr1 = in_be32(&gur->porsr1);
	porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
	out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
		 porsr1);
#endif
}

/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	int vdd;
	u32 fusesr;
	u8 vid;

	fusesr = in_be32(&gur->dcfg_fusesr);
	debug("%s: fusesr = 0x%x\n", __func__, fusesr);
	vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
		FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
	if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
		vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
			FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
	}
	debug("%s: VID = 0x%x\n", __func__, vid);
	switch (vid) {
	case 0x00: /* VID isn't supported */
		vdd = -EINVAL;
		debug("%s: The VID feature is not supported\n", __func__);
		break;
	case 0x08: /* 0.9V silicon */
		vdd = 900;
		break;
	case 0x10: /* 1.0V silicon */
		vdd = 1000;
		break;
	default:  /* Other core voltage */
		vdd = -EINVAL;
		printf("%s: The VID(%x) isn't supported\n", __func__, vid);
		break;
	}
	debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);

	return vdd;
}

__weak int board_switch_core_volt(u32 vdd)
{
	return 0;
}

static int setup_core_volt(u32 vdd)
{
	return board_setup_core_volt(vdd);
}

#ifdef CONFIG_SYS_FSL_DDR
static void ddr_enable_0v9_volt(bool en)
{
	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
	u32 tmp;

	tmp = ddr_in32(&ddr->ddr_cdr1);

	if (en)
		tmp |= DDR_CDR1_V0PT9_EN;
	else
		tmp &= ~DDR_CDR1_V0PT9_EN;

	ddr_out32(&ddr->ddr_cdr1, tmp);
}
#endif

int setup_chip_volt(void)
{
	int vdd;

	vdd = get_core_volt_from_fuse();
	/* Nothing to do for silicons doesn't support VID */
	if (vdd < 0)
		return vdd;

	if (setup_core_volt(vdd))
		printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
#ifdef CONFIG_SYS_HAS_SERDES
	if (setup_serdes_volt(vdd))
		printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
#endif

#ifdef CONFIG_SYS_FSL_DDR
	if (vdd == 900)
		ddr_enable_0v9_volt(true);
#endif

	return 0;
}

void fsl_lsch2_early_init_f(void)
{
	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
					CONFIG_SYS_CCI400_OFFSET);
	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;

#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
	enable_layerscape_ns_access();
#endif

#ifdef CONFIG_FSL_IFC
	init_early_memctl_regs();	/* tighten IFC timing */
#endif

#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
	/* Make SEC reads and writes snoopable */
	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
		     SCFG_SNPCNFGCR_SECWRSNP |
		     SCFG_SNPCNFGCR_SATARDSNP |
		     SCFG_SNPCNFGCR_SATAWRSNP);

	/*
	 * Enable snoop requests and DVM message requests for
	 * Slave insterface S4 (A53 core cluster)
	 */
	if (current_el() == 3) {
		out_le32(&cci->slave[4].snoop_ctrl,
			 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
	}

	/* Erratum */
	erratum_a008850_early(); /* part 1 of 2 */
	erratum_a009929();
	erratum_a009660();
	erratum_a010539();
	erratum_a009008();
	erratum_a009798();
	erratum_a008997();
	erratum_a009007();
}
#endif

#ifdef CONFIG_QSPI_AHB_INIT
/* Enable 4bytes address support and fast read */
int qspi_ahb_init(void)
{
	u32 *qspi_lut, lut_key, *qspi_key;

	qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
	qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;

	lut_key = in_be32(qspi_key);

	if (lut_key == 0x5af05af0) {
		/* That means the register is BE */
		out_be32(qspi_key, 0x5af05af0);
		/* Unlock the lut table */
		out_be32(qspi_key + 1, 0x00000002);
		out_be32(qspi_lut, 0x0820040c);
		out_be32(qspi_lut + 1, 0x1c080c08);
		out_be32(qspi_lut + 2, 0x00002400);
		/* Lock the lut table */
		out_be32(qspi_key, 0x5af05af0);
		out_be32(qspi_key + 1, 0x00000001);
	} else {
		/* That means the register is LE */
		out_le32(qspi_key, 0x5af05af0);
		/* Unlock the lut table */
		out_le32(qspi_key + 1, 0x00000002);
		out_le32(qspi_lut, 0x0820040c);
		out_le32(qspi_lut + 1, 0x1c080c08);
		out_le32(qspi_lut + 2, 0x00002400);
		/* Lock the lut table */
		out_le32(qspi_key, 0x5af05af0);
		out_le32(qspi_key + 1, 0x00000001);
	}

	return 0;
}
#endif

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_SCSI_AHCI_PLAT
	sata_init();
#endif
#ifdef CONFIG_CHAIN_OF_TRUST
	fsl_setenv_chain_of_trust();
#endif
#ifdef CONFIG_QSPI_AHB_INIT
	qspi_ahb_init();
#endif

	return 0;
}
#endif
Commit	Line	Data
b991b981	1	/*
9f3183d2	2	* Copyright 2014-2015 Freescale Semiconductor
b991b981 SW	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
63b2316c	8	#include <fsl_immap.h>
b991b981	9	#include <fsl_ifc.h>
989c5f0a TY	10	#include <ahci.h>
989c5f0a TY	11	#include <scsi.h>
b392a6d4	12	#include <asm/arch/fsl_serdes.h>
9f3183d2	13	#include <asm/arch/soc.h>
d746fef4	14	#include <asm/io.h>
b2d5ac59	15	#include <asm/global_data.h>
b4017364	16	#include <asm/arch-fsl-layerscape/config.h>
b392a6d4	17	#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
341238fd	18	#include <fsl_csu.h>
b392a6d4	19	#endif
b7f2bbff	20	#ifdef CONFIG_SYS_FSL_DDR
074596c0 SL	21	#include <fsl_ddr_sdram.h>
074596c0 SL	22	#include <fsl_ddr.h>
b7f2bbff	23	#endif
d0412885 AB	24	#ifdef CONFIG_CHAIN_OF_TRUST
	25	#include <fsl_validate.h>
	26	#endif
6d9b82d0	27	#include <fsl_immap.h>
b2d5ac59 SW	28
b2d5ac59 SW	29	DECLARE_GLOBAL_DATA_PTR;
d746fef4	30
3c1d218a YS	31	bool soc_has_dp_ddr(void)
	32	{
	33	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	34	u32 svr = gur_in32(&gur->svr);
	35
9ae836cd PJ	36	/* LS2085A, LS2088A, LS2048A has DP_DDR */
	37	if ((SVR_SOC_VER(svr) == SVR_LS2085A) \|\|
	38	(SVR_SOC_VER(svr) == SVR_LS2088A) \|\|
	39	(SVR_SOC_VER(svr) == SVR_LS2048A))
3c1d218a YS	40	return true;
	41
	42	return false;
	43	}
	44
	45	bool soc_has_aiop(void)
	46	{
	47	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	48	u32 svr = gur_in32(&gur->svr);
	49
	50	/* LS2085A has AIOP */
49cdce16	51	if (SVR_SOC_VER(svr) == SVR_LS2085A)
3c1d218a YS	52	return true;
	53
	54	return false;
	55	}
	56
2ab1553f RW	57	static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
	58	{
	59	scfg_clrsetbits32(scfg + offset / 4,
	60	0xF << 6,
	61	SCFG_USB_TXVREFTUNE << 6);
	62	}
	63
	64	static void erratum_a009008(void)
	65	{
	66	#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
	67	u32 __iomem scfg = (u32 __iomem )SCFG_BASE;
2a8a3539	68
2ab1553f RW	69	#if defined(CONFIG_ARCH_LS1043A) \|\| defined(CONFIG_ARCH_LS1046A)
	70	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
	71	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
	72	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
	73	#elif defined(CONFIG_ARCH_LS2080A)
	74	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
	75	#endif
	76	#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
	77	}
	78
2a8a3539 RW	79	static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
	80	{
	81	scfg_clrbits32(scfg + offset / 4,
	82	SCFG_USB_SQRXTUNE_MASK << 23);
	83	}
	84
	85	static void erratum_a009798(void)
	86	{
	87	#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
	88	u32 __iomem scfg = (u32 __iomem )SCFG_BASE;
	89
	90	#if defined(CONFIG_ARCH_LS1043A) \|\| defined(CONFIG_ARCH_LS1046A)
	91	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
	92	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
	93	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
	94	#elif defined(CONFIG_ARCH_LS2080A)
	95	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
	96	#endif
	97	#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
	98	}
	99
9d1cd910 RW	100	#if defined(CONFIG_ARCH_LS1043A) \|\| defined(CONFIG_ARCH_LS1046A)
	101	static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
	102	{
	103	scfg_clrsetbits32(scfg + offset / 4,
	104	0x7F << 9,
	105	SCFG_USB_PCSTXSWINGFULL << 9);
	106	}
	107	#endif
	108
	109	static void erratum_a008997(void)
	110	{
	111	#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
	112	#if defined(CONFIG_ARCH_LS1043A) \|\| defined(CONFIG_ARCH_LS1046A)
	113	u32 __iomem scfg = (u32 __iomem )SCFG_BASE;
	114
	115	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
	116	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
	117	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
	118	#endif
	119	#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
	120	}
	121
15d59b53 RW	122	#if defined(CONFIG_ARCH_LS1043A) \|\| defined(CONFIG_ARCH_LS1046A)
	123
	124	#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
	125	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
	126	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
	127	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
	128	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
	129
	130	#elif defined(CONFIG_ARCH_LS2080A)
	131
	132	#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
	133	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
	134	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
	135	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
	136	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
	137
	138	#endif
	139
	140	static void erratum_a009007(void)
	141	{
	142	#if defined(CONFIG_ARCH_LS1043A) \|\| defined(CONFIG_ARCH_LS1046A)
	143	void __iomem usb_phy = (void __iomem )SCFG_USB_PHY1;
	144
	145	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
	146
	147	usb_phy = (void __iomem *)SCFG_USB_PHY2;
	148	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
	149
	150	usb_phy = (void __iomem *)SCFG_USB_PHY3;
	151	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
	152	#elif defined(CONFIG_ARCH_LS2080A)
	153	void __iomem dcsr = (void __iomem )DCSR_BASE;
	154
	155	PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
	156	PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
	157	#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
	158	}
	159
40836e21	160	#if defined(CONFIG_FSL_LSCH3)
000f4e76 YY	161	/*
	162	* This erratum requires setting a value to eddrtqcr1 to
	163	* optimal the DDR performance.
	164	*/
	165	static void erratum_a008336(void)
	166	{
40836e21	167	#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
000f4e76 YY	168	u32 *eddrtqcr1;
000f4e76 YY	169
000f4e76 YY	170	#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
000f4e76 YY	171	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
1a87c24f SL	172	if (fsl_ddr_get_version(0) == 0x50200)
1a87c24f SL	173	out_le32(eddrtqcr1, 0x63b30002);
000f4e76 YY	174	#endif
	175	#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
	176	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
1a87c24f SL	177	if (fsl_ddr_get_version(0) == 0x50200)
1a87c24f SL	178	out_le32(eddrtqcr1, 0x63b30002);
000f4e76 YY	179	#endif
	180	#endif
	181	}
	182
	183	/*
	184	* This erratum requires a register write before being Memory
	185	* controller 3 being enabled.
	186	*/
	187	static void erratum_a008514(void)
	188	{
40836e21	189	#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
000f4e76 YY	190	u32 *eddrtqcr1;
000f4e76 YY	191
000f4e76 YY	192	#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
	193	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
	194	out_le32(eddrtqcr1, 0x63b20002);
	195	#endif
	196	#endif
	197	}
b4017364 PK	198	#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
	199	#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
	200
	201	static unsigned long get_internval_val_mhz(void)
	202	{
00caae6d	203	char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
b4017364 PK	204	/*
	205	* interval is the number of platform cycles(MHz) between
	206	* wake up events generated by EPU.
	207	*/
	208	ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
	209
	210	if (interval)
	211	interval_mhz = simple_strtoul(interval, NULL, 10);
	212
	213	return interval_mhz;
	214	}
	215
	216	void erratum_a009635(void)
	217	{
	218	u32 val;
	219	unsigned long interval_mhz = get_internval_val_mhz();
	220
	221	if (!interval_mhz)
	222	return;
	223
	224	val = in_le32(DCSR_CGACRE5);
	225	writel(val \| 0x00000200, DCSR_CGACRE5);
	226
	227	val = in_le32(EPU_EPCMPR5);
	228	writel(interval_mhz, EPU_EPCMPR5);
	229	val = in_le32(EPU_EPCCR5);
	230	writel(val \| 0x82820000, EPU_EPCCR5);
	231	val = in_le32(EPU_EPSMCR5);
	232	writel(val \| 0x002f0000, EPU_EPSMCR5);
	233	val = in_le32(EPU_EPECR5);
	234	writel(val \| 0x20000000, EPU_EPECR5);
	235	val = in_le32(EPU_EPGCR);
	236	writel(val \| 0x80000000, EPU_EPGCR);
	237	}
	238	#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
	239
b2d5ac59 SW	240	static void erratum_rcw_src(void)
b2d5ac59 SW	241	{
faed6bde	242	#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
b2d5ac59 SW	243	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	244	u32 __iomem dcfg_dcsr = (u32 __iomem )DCFG_DCSR_BASE;
	245	u32 val;
	246
	247	val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
	248	val &= ~DCFG_PORSR1_RCW_SRC;
	249	val \|= DCFG_PORSR1_RCW_SRC_NOR;
	250	out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
	251	#endif
	252	}
	253
ab10d73d YS	254	#define I2C_DEBUG_REG 0x6
	255	#define I2C_GLITCH_EN 0x8
	256	/*
	257	* This erratum requires setting glitch_en bit to enable
	258	* digital glitch filter to improve clock stability.
	259	*/
dd48f0bf	260	#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
ab10d73d YS	261	static void erratum_a009203(void)
	262	{
	263	u8 __iomem *ptr;
	264	#ifdef CONFIG_SYS_I2C
	265	#ifdef I2C1_BASE_ADDR
	266	ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
	267
	268	writeb(I2C_GLITCH_EN, ptr);
	269	#endif
	270	#ifdef I2C2_BASE_ADDR
	271	ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
	272
	273	writeb(I2C_GLITCH_EN, ptr);
	274	#endif
	275	#ifdef I2C3_BASE_ADDR
	276	ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
	277
	278	writeb(I2C_GLITCH_EN, ptr);
	279	#endif
	280	#ifdef I2C4_BASE_ADDR
	281	ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
	282
	283	writeb(I2C_GLITCH_EN, ptr);
	284	#endif
	285	#endif
	286	}
dd48f0bf	287	#endif
40836e21	288
4a97a0c9 SJ	289	void bypass_smmu(void)
	290	{
	291	u32 val;
	292	val = (in_le32(SMMU_SCR0) \| SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
	293	out_le32(SMMU_SCR0, val);
	294	val = (in_le32(SMMU_NSCR0) \| SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
	295	out_le32(SMMU_NSCR0, val);
	296	}
b991b981 SW	297	void fsl_lsch3_early_init_f(void)
b991b981 SW	298	{
b2d5ac59	299	erratum_rcw_src();
e45ff0ce	300	#ifdef CONFIG_FSL_IFC
b991b981	301	init_early_memctl_regs(); /* tighten IFC timing */
e45ff0ce	302	#endif
dd48f0bf	303	#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
ab10d73d	304	erratum_a009203();
dd48f0bf	305	#endif
000f4e76 YY	306	erratum_a008514();
000f4e76 YY	307	erratum_a008336();
2ab1553f	308	erratum_a009008();
2a8a3539	309	erratum_a009798();
9d1cd910	310	erratum_a008997();
15d59b53	311	erratum_a009007();
4a97a0c9 SJ	312	#ifdef CONFIG_CHAIN_OF_TRUST
	313	/* In case of Secure Boot, the IBR configures the SMMU
	314	* to allow only Secure transactions.
	315	* SMMU must be reset in bypass mode.
	316	* Set the ClientPD bit and Clear the USFCFG Bit
	317	*/
	318	if (fsl_check_boot_mode_secure() == 1)
	319	bypass_smmu();
	320	#endif
b991b981	321	}
8281c58f	322
989c5f0a TY	323	#ifdef CONFIG_SCSI_AHCI_PLAT
	324	int sata_init(void)
	325	{
	326	struct ccsr_ahci __iomem *ccsr_ahci;
	327
bdbcb522	328	#ifdef CONFIG_SYS_SATA2
989c5f0a TY	329	ccsr_ahci = (void *)CONFIG_SYS_SATA2;
	330	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
	331	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
435cca16	332	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
bdbcb522	333	#endif
989c5f0a	334
bdbcb522	335	#ifdef CONFIG_SYS_SATA1
989c5f0a TY	336	ccsr_ahci = (void *)CONFIG_SYS_SATA1;
	337	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
	338	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
435cca16	339	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
989c5f0a TY	340
989c5f0a TY	341	ahci_init((void __iomem *)CONFIG_SYS_SATA1);
8eab1a58	342	scsi_scan(false);
bdbcb522	343	#endif
989c5f0a TY	344
	345	return 0;
	346	}
	347	#endif
	348
22a44d08	349	#elif defined(CONFIG_FSL_LSCH2)
989c5f0a TY	350	#ifdef CONFIG_SCSI_AHCI_PLAT
	351	int sata_init(void)
	352	{
	353	struct ccsr_ahci __iomem ccsr_ahci = (void )CONFIG_SYS_SATA;
	354
1b2b4066 SX	355	/* Disable SATA ECC */
1b2b4066 SX	356	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
989c5f0a	357	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
989c5f0a	358	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
4de6ce15	359	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
989c5f0a TY	360
989c5f0a TY	361	ahci_init((void __iomem *)CONFIG_SYS_SATA);
8eab1a58	362	scsi_scan(false);
989c5f0a TY	363
	364	return 0;
	365	}
	366	#endif
	367
0d6faf2b MH	368	static void erratum_a009929(void)
	369	{
	370	#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
	371	struct ccsr_gur gur = (void )CONFIG_SYS_FSL_GUTS_ADDR;
	372	u32 __iomem dcsr_cop_ccp = (void )CONFIG_SYS_DCSR_COP_CCP_ADDR;
	373	u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
	374
	375	rstrqmr1 \|= 0x00000400;
	376	gur_out32(&gur->rstrqmr1, rstrqmr1);
	377	writel(0x01000000, dcsr_cop_ccp);
	378	#endif
	379	}
	380
bbc8e053 MH	381	/*
	382	* This erratum requires setting a value to eddrtqcr1 to optimal
	383	* the DDR performance. The eddrtqcr1 register is in SCFG space
	384	* of LS1043A and the offset is 0x157_020c.
	385	*/
	386	#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
	387	&& defined(CONFIG_SYS_FSL_ERRATUM_A008514)
	388	#error A009660 and A008514 can not be both enabled.
	389	#endif
	390
	391	static void erratum_a009660(void)
	392	{
	393	#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
	394	u32 eddrtqcr1 = (void )CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
	395	out_be32(eddrtqcr1, 0x63b20042);
	396	#endif
	397	}
	398
074596c0 SL	399	static void erratum_a008850_early(void)
	400	{
	401	#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
	402	/* part 1 of 2 */
63b2316c AK	403	struct ccsr_cci400 __iomem cci = (void )(CONFIG_SYS_IMMR +
63b2316c AK	404	CONFIG_SYS_CCI400_OFFSET);
074596c0 SL	405	struct ccsr_ddr __iomem ddr = (void )CONFIG_SYS_FSL_DDR_ADDR;
074596c0 SL	406
399e2bb6 YS	407	/* Skip if running at lower exception level */
	408	if (current_el() < 3)
	409	return;
	410
074596c0 SL	411	/* disables propagation of barrier transactions to DDRC from CCI400 */
	412	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
	413
	414	/* disable the re-ordering in DDRC */
	415	ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS \| DDR_EOR_WD_REOD_DIS);
	416	#endif
	417	}
	418
	419	void erratum_a008850_post(void)
	420	{
	421	#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
	422	/* part 2 of 2 */
63b2316c AK	423	struct ccsr_cci400 __iomem cci = (void )(CONFIG_SYS_IMMR +
63b2316c AK	424	CONFIG_SYS_CCI400_OFFSET);
074596c0 SL	425	struct ccsr_ddr __iomem ddr = (void )CONFIG_SYS_FSL_DDR_ADDR;
	426	u32 tmp;
	427
399e2bb6 YS	428	/* Skip if running at lower exception level */
	429	if (current_el() < 3)
	430	return;
	431
074596c0 SL	432	/* enable propagation of barrier transactions to DDRC from CCI400 */
	433	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
	434
	435	/* enable the re-ordering in DDRC */
	436	tmp = ddr_in32(&ddr->eor);
	437	tmp &= ~(DDR_EOR_RD_REOD_DIS \| DDR_EOR_WD_REOD_DIS);
	438	ddr_out32(&ddr->eor, tmp);
	439	#endif
	440	}
	441
b392a6d4 HZ	442	#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
	443	void erratum_a010315(void)
	444	{
	445	int i;
	446
	447	for (i = PCIE1; i <= PCIE4; i++)
	448	if (!is_serdes_configured(i)) {
	449	debug("PCIe%d: disabled all R/W permission!\n", i);
	450	set_pcie_ns_access(i, 0);
	451	}
	452	}
	453	#endif
	454
0ea3671d HZ	455	static void erratum_a010539(void)
	456	{
	457	#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
	458	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	459	u32 porsr1;
	460
	461	porsr1 = in_be32(&gur->porsr1);
	462	porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
	463	out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
	464	porsr1);
	465	#endif
	466	}
	467
031acdba HZ	468	/* Get VDD in the unit mV from voltage ID */
	469	int get_core_volt_from_fuse(void)
	470	{
	471	struct ccsr_gur gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	472	int vdd;
	473	u32 fusesr;
	474	u8 vid;
	475
	476	fusesr = in_be32(&gur->dcfg_fusesr);
	477	debug("%s: fusesr = 0x%x\n", __func__, fusesr);
	478	vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
	479	FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
	480	if ((vid == 0) \|\| (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
	481	vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
	482	FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
	483	}
	484	debug("%s: VID = 0x%x\n", __func__, vid);
	485	switch (vid) {
	486	case 0x00: /* VID isn't supported */
	487	vdd = -EINVAL;
	488	debug("%s: The VID feature is not supported\n", __func__);
	489	break;
	490	case 0x08: /* 0.9V silicon */
	491	vdd = 900;
	492	break;
	493	case 0x10: /* 1.0V silicon */
	494	vdd = 1000;
	495	break;
	496	default: /* Other core voltage */
	497	vdd = -EINVAL;
	498	printf("%s: The VID(%x) isn't supported\n", __func__, vid);
	499	break;
	500	}
	501	debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
	502
	503	return vdd;
	504	}
	505
	506	__weak int board_switch_core_volt(u32 vdd)
	507	{
	508	return 0;
	509	}
	510
	511	static int setup_core_volt(u32 vdd)
	512	{
	513	return board_setup_core_volt(vdd);
	514	}
	515
	516	#ifdef CONFIG_SYS_FSL_DDR
	517	static void ddr_enable_0v9_volt(bool en)
	518	{
	519	struct ccsr_ddr __iomem ddr = (void )CONFIG_SYS_FSL_DDR_ADDR;
	520	u32 tmp;
	521
	522	tmp = ddr_in32(&ddr->ddr_cdr1);
	523
	524	if (en)
	525	tmp \|= DDR_CDR1_V0PT9_EN;
	526	else
	527	tmp &= ~DDR_CDR1_V0PT9_EN;
	528
	529	ddr_out32(&ddr->ddr_cdr1, tmp);
	530	}
	531	#endif
532
533	int setup_chip_volt(void)
534	{
535	int vdd;
536
537	vdd = get_core_volt_from_fuse();
538	/* Nothing to do for silicons doesn't support VID */
539	if (vdd < 0)
540	return vdd;
541
542	if (setup_core_volt(vdd))
543	printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
544	#ifdef CONFIG_SYS_HAS_SERDES
545	if (setup_serdes_volt(vdd))
546	printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
547	#endif
548
549	#ifdef CONFIG_SYS_FSL_DDR
550	if (vdd == 900)
551	ddr_enable_0v9_volt(true);
552	#endif
553
554	return 0;
555	}
556
8281c58f MH	557	void fsl_lsch2_early_init_f(void)
8281c58f MH	558	{
63b2316c AK	559	struct ccsr_cci400 cci = (struct ccsr_cci400 )(CONFIG_SYS_IMMR +
63b2316c AK	560	CONFIG_SYS_CCI400_OFFSET);
70f959c3	561	struct ccsr_scfg scfg = (struct ccsr_scfg )CONFIG_SYS_FSL_SCFG_ADDR;
8281c58f	562
341238fd HZ	563	#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
	564	enable_layerscape_ns_access();
	565	#endif
	566
8281c58f MH	567	#ifdef CONFIG_FSL_IFC
	568	init_early_memctl_regs(); /* tighten IFC timing */
	569	#endif
	570
258b8c93	571	#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
166ef1e9 GQ	572	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
166ef1e9 GQ	573	#endif
70f959c3 AB	574	/* Make SEC reads and writes snoopable */
70f959c3 AB	575	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP \|
4de6ce15 TY	576	SCFG_SNPCNFGCR_SECWRSNP \|
	577	SCFG_SNPCNFGCR_SATARDSNP \|
	578	SCFG_SNPCNFGCR_SATAWRSNP);
70f959c3	579
8281c58f MH	580	/*
	581	* Enable snoop requests and DVM message requests for
	582	* Slave insterface S4 (A53 core cluster)
	583	*/
399e2bb6 YS	584	if (current_el() == 3) {
	585	out_le32(&cci->slave[4].snoop_ctrl,
	586	CCI400_DVM_MESSAGE_REQ_EN \| CCI400_SNOOP_REQ_EN);
	587	}
0d6faf2b MH	588
0d6faf2b MH	589	/* Erratum */
074596c0	590	erratum_a008850_early(); /* part 1 of 2 */
0d6faf2b	591	erratum_a009929();
bbc8e053	592	erratum_a009660();
0ea3671d	593	erratum_a010539();
2ab1553f	594	erratum_a009008();
2a8a3539	595	erratum_a009798();
9d1cd910	596	erratum_a008997();
15d59b53	597	erratum_a009007();
8281c58f	598	}
9f3183d2	599	#endif
b2d5ac59	600
dd2ad2f1 YY	601	#ifdef CONFIG_QSPI_AHB_INIT
	602	/* Enable 4bytes address support and fast read */
	603	int qspi_ahb_init(void)
	604	{
	605	u32 qspi_lut, lut_key, qspi_key;
	606
	607	qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
	608	qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
	609
	610	lut_key = in_be32(qspi_key);
	611
	612	if (lut_key == 0x5af05af0) {
	613	/* That means the register is BE */
	614	out_be32(qspi_key, 0x5af05af0);
	615	/* Unlock the lut table */
	616	out_be32(qspi_key + 1, 0x00000002);
	617	out_be32(qspi_lut, 0x0820040c);
	618	out_be32(qspi_lut + 1, 0x1c080c08);
	619	out_be32(qspi_lut + 2, 0x00002400);
	620	/* Lock the lut table */
	621	out_be32(qspi_key, 0x5af05af0);
	622	out_be32(qspi_key + 1, 0x00000001);
	623	} else {
	624	/* That means the register is LE */
	625	out_le32(qspi_key, 0x5af05af0);
	626	/* Unlock the lut table */
	627	out_le32(qspi_key + 1, 0x00000002);
	628	out_le32(qspi_lut, 0x0820040c);
	629	out_le32(qspi_lut + 1, 0x1c080c08);
	630	out_le32(qspi_lut + 2, 0x00002400);
	631	/* Lock the lut table */
	632	out_le32(qspi_key, 0x5af05af0);
	633	out_le32(qspi_key + 1, 0x00000001);
	634	}
	635
	636	return 0;
	637	}
	638	#endif
	639
9f3183d2 MH	640	#ifdef CONFIG_BOARD_LATE_INIT
9f3183d2 MH	641	int board_late_init(void)
b2d5ac59	642	{
989c5f0a TY	643	#ifdef CONFIG_SCSI_AHCI_PLAT
	644	sata_init();
	645	#endif
d0412885 AB	646	#ifdef CONFIG_CHAIN_OF_TRUST
	647	fsl_setenv_chain_of_trust();
	648	#endif
dd2ad2f1 YY	649	#ifdef CONFIG_QSPI_AHB_INIT
	650	qspi_ahb_init();
	651	#endif
989c5f0a	652
9f3183d2	653	return 0;
b2d5ac59 SW	654	}
b2d5ac59 SW	655	#endif