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2f78eae5 YS |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/io.h> | |
9 | #include <asm/system.h> | |
10 | #include <asm/armv8/mmu.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/arch-fsl-lsch3/immap_lsch3.h> | |
13 | #include "cpu.h" | |
40f8dec5 | 14 | #include "mp.h" |
2f78eae5 | 15 | #include "speed.h" |
b940ca64 | 16 | #include <fsl_mc.h> |
2f78eae5 YS |
17 | |
18 | DECLARE_GLOBAL_DATA_PTR; | |
19 | ||
20 | #ifndef CONFIG_SYS_DCACHE_OFF | |
21 | /* | |
22 | * To start MMU before DDR is available, we create MMU table in SRAM. | |
23 | * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three | |
24 | * levels of translation tables here to cover 40-bit address space. | |
25 | * We use 4KB granule size, with 40 bits physical address, T0SZ=24 | |
26 | * Level 0 IA[39], table address @0 | |
27 | * Level 1 IA[31:30], table address @01000, 0x2000 | |
28 | * Level 2 IA[29:21], table address @0x3000 | |
29 | */ | |
30 | ||
31 | #define SECTION_SHIFT_L0 39UL | |
32 | #define SECTION_SHIFT_L1 30UL | |
33 | #define SECTION_SHIFT_L2 21UL | |
34 | #define BLOCK_SIZE_L0 0x8000000000UL | |
35 | #define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) | |
36 | #define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) | |
37 | #define CONFIG_SYS_IFC_BASE 0x30000000 | |
38 | #define CONFIG_SYS_IFC_SIZE 0x10000000 | |
39 | #define CONFIG_SYS_IFC_BASE2 0x500000000 | |
40 | #define CONFIG_SYS_IFC_SIZE2 0x100000000 | |
41 | #define TCR_EL2_PS_40BIT (2 << 16) | |
42 | #define LSCH3_VA_BITS (40) | |
43 | #define LSCH3_TCR (TCR_TG0_4K | \ | |
44 | TCR_EL2_PS_40BIT | \ | |
45 | TCR_SHARED_NON | \ | |
46 | TCR_ORGN_NC | \ | |
47 | TCR_IRGN_NC | \ | |
48 | TCR_T0SZ(LSCH3_VA_BITS)) | |
49 | ||
50 | /* | |
51 | * Final MMU | |
52 | * Let's start from the same layout as early MMU and modify as needed. | |
53 | * IFC regions will be cache-inhibit. | |
54 | */ | |
55 | #define FINAL_QBMAN_CACHED_MEM 0x818000000UL | |
56 | #define FINAL_QBMAN_CACHED_SIZE 0x4000000 | |
57 | ||
58 | ||
59 | static inline void early_mmu_setup(void) | |
60 | { | |
61 | int el; | |
62 | u64 i; | |
63 | u64 section_l1t0, section_l1t1, section_l2; | |
64 | u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; | |
65 | u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); | |
66 | u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); | |
67 | u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); | |
68 | ||
69 | ||
70 | level0_table[0] = | |
71 | (u64)level1_table_0 | PMD_TYPE_TABLE; | |
72 | level0_table[1] = | |
73 | (u64)level1_table_1 | PMD_TYPE_TABLE; | |
74 | ||
75 | /* | |
76 | * set level 1 table 0 to cache_inhibit, covering 0 to 512GB | |
77 | * set level 1 table 1 to cache enabled, covering 512GB to 1TB | |
78 | * set level 2 table to cache-inhibit, covering 0 to 1GB | |
79 | */ | |
80 | section_l1t0 = 0; | |
81 | section_l1t1 = BLOCK_SIZE_L0; | |
82 | section_l2 = 0; | |
83 | for (i = 0; i < 512; i++) { | |
84 | set_pgtable_section(level1_table_0, i, section_l1t0, | |
85 | MT_DEVICE_NGNRNE); | |
86 | set_pgtable_section(level1_table_1, i, section_l1t1, | |
87 | MT_NORMAL); | |
88 | set_pgtable_section(level2_table, i, section_l2, | |
89 | MT_DEVICE_NGNRNE); | |
90 | section_l1t0 += BLOCK_SIZE_L1; | |
91 | section_l1t1 += BLOCK_SIZE_L1; | |
92 | section_l2 += BLOCK_SIZE_L2; | |
93 | } | |
94 | ||
95 | level1_table_0[0] = | |
96 | (u64)level2_table | PMD_TYPE_TABLE; | |
97 | level1_table_0[1] = | |
98 | 0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT | | |
99 | PMD_ATTRINDX(MT_DEVICE_NGNRNE); | |
100 | level1_table_0[2] = | |
101 | 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | | |
102 | PMD_ATTRINDX(MT_NORMAL); | |
103 | level1_table_0[3] = | |
104 | 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | | |
105 | PMD_ATTRINDX(MT_NORMAL); | |
106 | ||
107 | /* Rewrite table to enable cache */ | |
108 | set_pgtable_section(level2_table, | |
109 | CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, | |
110 | CONFIG_SYS_FSL_OCRAM_BASE, | |
111 | MT_NORMAL); | |
112 | for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2; | |
113 | i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE) | |
114 | >> SECTION_SHIFT_L2; i++) { | |
115 | section_l2 = i << SECTION_SHIFT_L2; | |
116 | set_pgtable_section(level2_table, i, | |
117 | section_l2, MT_NORMAL); | |
118 | } | |
119 | ||
120 | el = current_el(); | |
121 | set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES); | |
122 | set_sctlr(get_sctlr() | CR_M); | |
123 | } | |
124 | ||
125 | /* | |
126 | * This final tale looks similar to early table, but different in detail. | |
127 | * These tables are in regular memory. Cache on IFC is disabled. One sub table | |
128 | * is added to enable cache for QBMan. | |
129 | */ | |
130 | static inline void final_mmu_setup(void) | |
131 | { | |
132 | int el; | |
133 | u64 i, tbl_base, tbl_limit, section_base; | |
134 | u64 section_l1t0, section_l1t1, section_l2; | |
135 | u64 *level0_table = (u64 *)gd->arch.tlb_addr; | |
136 | u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000); | |
137 | u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000); | |
138 | u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000); | |
139 | u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000); | |
140 | ||
141 | ||
142 | level0_table[0] = | |
143 | (u64)level1_table_0 | PMD_TYPE_TABLE; | |
144 | level0_table[1] = | |
145 | (u64)level1_table_1 | PMD_TYPE_TABLE; | |
146 | ||
147 | /* | |
148 | * set level 1 table 0 to cache_inhibit, covering 0 to 512GB | |
149 | * set level 1 table 1 to cache enabled, covering 512GB to 1TB | |
150 | * set level 2 table 0 to cache-inhibit, covering 0 to 1GB | |
151 | */ | |
152 | section_l1t0 = 0; | |
153 | section_l1t1 = BLOCK_SIZE_L0; | |
154 | section_l2 = 0; | |
155 | for (i = 0; i < 512; i++) { | |
156 | set_pgtable_section(level1_table_0, i, section_l1t0, | |
157 | MT_DEVICE_NGNRNE); | |
158 | set_pgtable_section(level1_table_1, i, section_l1t1, | |
159 | MT_NORMAL); | |
160 | set_pgtable_section(level2_table_0, i, section_l2, | |
161 | MT_DEVICE_NGNRNE); | |
162 | section_l1t0 += BLOCK_SIZE_L1; | |
163 | section_l1t1 += BLOCK_SIZE_L1; | |
164 | section_l2 += BLOCK_SIZE_L2; | |
165 | } | |
166 | ||
167 | level1_table_0[0] = | |
168 | (u64)level2_table_0 | PMD_TYPE_TABLE; | |
169 | level1_table_0[2] = | |
170 | 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | | |
171 | PMD_ATTRINDX(MT_NORMAL); | |
172 | level1_table_0[3] = | |
173 | 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | | |
174 | PMD_ATTRINDX(MT_NORMAL); | |
175 | ||
176 | /* Rewrite table to enable cache */ | |
177 | set_pgtable_section(level2_table_0, | |
178 | CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, | |
179 | CONFIG_SYS_FSL_OCRAM_BASE, | |
180 | MT_NORMAL); | |
181 | ||
182 | /* | |
183 | * Fill in other part of tables if cache is needed | |
184 | * If finer granularity than 1GB is needed, sub table | |
185 | * should be created. | |
186 | */ | |
187 | section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1); | |
188 | i = section_base >> SECTION_SHIFT_L1; | |
189 | level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE; | |
190 | section_l2 = section_base; | |
191 | for (i = 0; i < 512; i++) { | |
192 | set_pgtable_section(level2_table_1, i, section_l2, | |
193 | MT_DEVICE_NGNRNE); | |
194 | section_l2 += BLOCK_SIZE_L2; | |
195 | } | |
196 | tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1); | |
197 | tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) & | |
198 | (BLOCK_SIZE_L1 - 1); | |
199 | for (i = tbl_base >> SECTION_SHIFT_L2; | |
200 | i < tbl_limit >> SECTION_SHIFT_L2; i++) { | |
201 | section_l2 = section_base + (i << SECTION_SHIFT_L2); | |
202 | set_pgtable_section(level2_table_1, i, | |
203 | section_l2, MT_NORMAL); | |
204 | } | |
205 | ||
206 | /* flush new MMU table */ | |
207 | flush_dcache_range(gd->arch.tlb_addr, | |
208 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
209 | ||
210 | /* point TTBR to the new table */ | |
211 | el = current_el(); | |
212 | asm volatile("dsb sy"); | |
213 | if (el == 1) { | |
214 | asm volatile("msr ttbr0_el1, %0" | |
215 | : : "r" ((u64)level0_table) : "memory"); | |
216 | } else if (el == 2) { | |
217 | asm volatile("msr ttbr0_el2, %0" | |
218 | : : "r" ((u64)level0_table) : "memory"); | |
219 | } else if (el == 3) { | |
220 | asm volatile("msr ttbr0_el3, %0" | |
221 | : : "r" ((u64)level0_table) : "memory"); | |
222 | } else { | |
223 | hang(); | |
224 | } | |
225 | asm volatile("isb"); | |
226 | ||
227 | /* | |
228 | * MMU is already enabled, just need to invalidate TLB to load the | |
229 | * new table. The new table is compatible with the current table, if | |
230 | * MMU somehow walks through the new table before invalidation TLB, | |
231 | * it still works. So we don't need to turn off MMU here. | |
232 | */ | |
233 | } | |
234 | ||
235 | int arch_cpu_init(void) | |
236 | { | |
237 | icache_enable(); | |
238 | __asm_invalidate_dcache_all(); | |
239 | __asm_invalidate_tlb_all(); | |
240 | early_mmu_setup(); | |
241 | set_sctlr(get_sctlr() | CR_C); | |
242 | return 0; | |
243 | } | |
244 | ||
245 | /* | |
246 | * flush_l3_cache | |
247 | * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power | |
248 | * state, by writing to HP-F P-state request register. | |
249 | * Fixme: This function should moved to a common file if other SoCs also use | |
250 | * the same Dickens. | |
251 | */ | |
252 | #define HNF0_PSTATE_REQ 0x04200010 | |
253 | #define HNF1_PSTATE_REQ 0x04210010 | |
254 | #define HNF2_PSTATE_REQ 0x04220010 | |
255 | #define HNF3_PSTATE_REQ 0x04230010 | |
256 | #define HNF4_PSTATE_REQ 0x04240010 | |
257 | #define HNF5_PSTATE_REQ 0x04250010 | |
258 | #define HNF6_PSTATE_REQ 0x04260010 | |
259 | #define HNF7_PSTATE_REQ 0x04270010 | |
260 | #define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC) | |
261 | #define HNFPSTAT_FAM 0x3 | |
262 | #define HNFPSTAT_SFONLY 0x01 | |
263 | ||
264 | static void hnf_pstate_req(u64 *ptr, u64 state) | |
265 | { | |
266 | int timeout = 1000; | |
267 | out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3)); | |
268 | ptr++; | |
269 | /* checking if the transition is completed */ | |
270 | while (timeout > 0) { | |
271 | if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3)) | |
272 | break; | |
273 | udelay(100); | |
274 | timeout--; | |
275 | } | |
276 | } | |
277 | ||
278 | void flush_l3_cache(void) | |
279 | { | |
280 | hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY); | |
281 | hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY); | |
282 | hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY); | |
283 | hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY); | |
284 | hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY); | |
285 | hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY); | |
286 | hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY); | |
287 | hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY); | |
288 | hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM); | |
289 | hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM); | |
290 | hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM); | |
291 | hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM); | |
292 | hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM); | |
293 | hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM); | |
294 | hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM); | |
295 | hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM); | |
296 | } | |
297 | ||
298 | /* | |
299 | * This function is called from lib/board.c. | |
300 | * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. | |
301 | * There is no need to disable d-cache for this operation. | |
302 | */ | |
303 | void enable_caches(void) | |
304 | { | |
305 | final_mmu_setup(); | |
306 | __asm_invalidate_tlb_all(); | |
307 | } | |
308 | #endif | |
309 | ||
310 | static inline u32 initiator_type(u32 cluster, int init_id) | |
311 | { | |
312 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
313 | u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; | |
314 | u32 type = in_le32(&gur->tp_ityp[idx]); | |
315 | ||
316 | if (type & TP_ITYP_AV) | |
317 | return type; | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
322 | u32 cpu_mask(void) | |
323 | { | |
324 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
325 | int i = 0, count = 0; | |
326 | u32 cluster, type, mask = 0; | |
327 | ||
328 | do { | |
329 | int j; | |
330 | cluster = in_le32(&gur->tp_cluster[i].lower); | |
331 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { | |
332 | type = initiator_type(cluster, j); | |
333 | if (type) { | |
334 | if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) | |
335 | mask |= 1 << count; | |
336 | count++; | |
337 | } | |
338 | } | |
339 | i++; | |
340 | } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); | |
341 | ||
342 | return mask; | |
343 | } | |
344 | ||
345 | /* | |
346 | * Return the number of cores on this SOC. | |
347 | */ | |
348 | int cpu_numcores(void) | |
349 | { | |
350 | return hweight32(cpu_mask()); | |
351 | } | |
352 | ||
353 | int fsl_qoriq_core_to_cluster(unsigned int core) | |
354 | { | |
355 | struct ccsr_gur __iomem *gur = | |
356 | (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
357 | int i = 0, count = 0; | |
358 | u32 cluster; | |
359 | ||
360 | do { | |
361 | int j; | |
362 | cluster = in_le32(&gur->tp_cluster[i].lower); | |
363 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { | |
364 | if (initiator_type(cluster, j)) { | |
365 | if (count == core) | |
366 | return i; | |
367 | count++; | |
368 | } | |
369 | } | |
370 | i++; | |
371 | } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); | |
372 | ||
373 | return -1; /* cannot identify the cluster */ | |
374 | } | |
375 | ||
376 | u32 fsl_qoriq_core_to_type(unsigned int core) | |
377 | { | |
378 | struct ccsr_gur __iomem *gur = | |
379 | (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
380 | int i = 0, count = 0; | |
381 | u32 cluster, type; | |
382 | ||
383 | do { | |
384 | int j; | |
385 | cluster = in_le32(&gur->tp_cluster[i].lower); | |
386 | for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { | |
387 | type = initiator_type(cluster, j); | |
388 | if (type) { | |
389 | if (count == core) | |
390 | return type; | |
391 | count++; | |
392 | } | |
393 | } | |
394 | i++; | |
395 | } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); | |
396 | ||
397 | return -1; /* cannot identify the cluster */ | |
398 | } | |
399 | ||
400 | #ifdef CONFIG_DISPLAY_CPUINFO | |
401 | int print_cpuinfo(void) | |
402 | { | |
403 | struct sys_info sysinfo; | |
404 | char buf[32]; | |
405 | unsigned int i, core; | |
406 | u32 type; | |
407 | ||
408 | get_sys_info(&sysinfo); | |
409 | puts("Clock Configuration:"); | |
410 | for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { | |
411 | if (!(i % 3)) | |
412 | puts("\n "); | |
413 | type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); | |
414 | printf("CPU%d(%s):%-4s MHz ", core, | |
415 | type == TY_ITYP_VER_A7 ? "A7 " : | |
416 | (type == TY_ITYP_VER_A53 ? "A53" : | |
417 | (type == TY_ITYP_VER_A57 ? "A57" : " ")), | |
418 | strmhz(buf, sysinfo.freq_processor[core])); | |
419 | } | |
420 | printf("\n Bus: %-4s MHz ", | |
421 | strmhz(buf, sysinfo.freq_systembus)); | |
422 | printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus)); | |
423 | puts("\n"); | |
424 | ||
425 | return 0; | |
426 | } | |
427 | #endif | |
b940ca64 GR |
428 | |
429 | int cpu_eth_init(bd_t *bis) | |
430 | { | |
431 | int error = 0; | |
432 | ||
433 | #ifdef CONFIG_FSL_MC_ENET | |
434 | error = mc_init(bis); | |
435 | #endif | |
436 | return error; | |
437 | } | |
40f8dec5 YS |
438 | |
439 | ||
440 | int arch_early_init_r(void) | |
441 | { | |
442 | int rv; | |
443 | rv = fsl_lsch3_wake_seconday_cores(); | |
444 | ||
445 | if (rv) | |
446 | printf("Did not wake secondary cores\n"); | |
447 | ||
448 | return 0; | |
449 | } |