[people/ms/u-boot.git] / arch / arm / cpu / armv8 / fsl-lsch3 / lowlevel.S

/*
 * (C) Copyright 2014 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Extracted from armv8/start.S
 */

#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>

ENTRY(lowlevel_init)
	mov	x29, lr			/* Save LR */

	/* Set the SMMU page size in the sACR register */
	ldr	x1, =SMMU_BASE
	ldr	w0, [x1, #0x10]
	orr	w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
	str	w0, [x1, #0x10]

	/* Initialize GIC Secure Bank Status */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
	branch_if_slave x0, 1f
	ldr	x0, =GICD_BASE
	bl	gic_init_secure
1:
#ifdef CONFIG_GICV3
	ldr	x0, =GICR_BASE
	bl	gic_init_secure_percpu
#elif defined(CONFIG_GICV2)
	ldr	x0, =GICD_BASE
	ldr	x1, =GICC_BASE
	bl	gic_init_secure_percpu
#endif
#endif

	branch_if_master x0, x1, 1f

	/*
	 * Slave should wait for master clearing spin table.
	 * This sync prevent salves observing incorrect
	 * value of spin table and jumping to wrong place.
	 */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
#ifdef CONFIG_GICV2
	ldr	x0, =GICC_BASE
#endif
	bl	gic_wait_for_interrupt
#endif

	/*
	 * All processors will enter EL2 and optionally EL1.
	 */
	bl	armv8_switch_to_el2
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
	bl	armv8_switch_to_el1
#endif
	b	2f

1:
2:
	mov	lr, x29			/* Restore LR */
	ret
ENDPROC(lowlevel_init)
Commit	Line	Data
2f78eae5 YS	1	/*
	2	* (C) Copyright 2014 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*
	6	* Extracted from armv8/start.S
	7	*/
	8
	9	#include <config.h>
	10	#include <linux/linkage.h>
	11	#include <asm/macro.h>
	12
	13	ENTRY(lowlevel_init)
	14	mov x29, lr /* Save LR */
	15
	16	/* Set the SMMU page size in the sACR register */
	17	ldr x1, =SMMU_BASE
	18	ldr w0, [x1, #0x10]
	19	orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
	20	str w0, [x1, #0x10]
	21
	22	/* Initialize GIC Secure Bank Status */
	23	#if defined(CONFIG_GICV2) \|\| defined(CONFIG_GICV3)
	24	branch_if_slave x0, 1f
	25	ldr x0, =GICD_BASE
	26	bl gic_init_secure
	27	1:
	28	#ifdef CONFIG_GICV3
	29	ldr x0, =GICR_BASE
	30	bl gic_init_secure_percpu
	31	#elif defined(CONFIG_GICV2)
	32	ldr x0, =GICD_BASE
	33	ldr x1, =GICC_BASE
	34	bl gic_init_secure_percpu
	35	#endif
	36	#endif
	37
	38	branch_if_master x0, x1, 1f
	39
	40	/*
	41	* Slave should wait for master clearing spin table.
	42	* This sync prevent salves observing incorrect
	43	* value of spin table and jumping to wrong place.
	44	*/
	45	#if defined(CONFIG_GICV2) \|\| defined(CONFIG_GICV3)
	46	#ifdef CONFIG_GICV2
	47	ldr x0, =GICC_BASE
	48	#endif
	49	bl gic_wait_for_interrupt
	50	#endif
	51
	52	/*
	53	* All processors will enter EL2 and optionally EL1.
	54	*/
	55	bl armv8_switch_to_el2
	56	#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
	57	bl armv8_switch_to_el1
	58	#endif
	59	b 2f
	60
	61	1:
	62	2:
	63	mov lr, x29 /* Restore LR */
	64	ret
65	ENDPROC(lowlevel_init)