[people/ms/u-boot.git] / arch / arm / cpu / ixp / start.S

/* vi: set ts=8 sw=8 noet: */
/*
 *  u-boot - Startup Code for XScale IXP
 *
 * Copyright (C) 2003	Kyle Harris <kharris@nexus-tech.net>
 *
 * Based on startup code example contained in the
 * Intel IXP4xx Programmer's Guide and past u-boot Start.S
 * samples.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/arch/ixp425.h>

#define MMU_Control_M  0x001    /* Enable MMU */
#define MMU_Control_A  0x002    /* Enable address alignment faults */
#define MMU_Control_C  0x004    /* Enable cache */
#define MMU_Control_W  0x008    /* Enable write-buffer */
#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
#define MMU_Control_L  0x040    /* Compatability: */
#define MMU_Control_B  0x080    /* Enable Big-Endian */
#define MMU_Control_S  0x100    /* Enable system protection */
#define MMU_Control_R  0x200    /* Enable ROM protection */
#define MMU_Control_I  0x1000   /* Enable Instruction cache */
#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)


/*
 * Macro definitions
 */
	/* Delay a bit */
	.macro DELAY_FOR cycles, reg0
	ldr     \reg0, =\cycles
	subs    \reg0, \reg0, #1
	subne   pc,  pc, #0xc
	.endm

	/* wait for coprocessor write complete */
	.macro CPWAIT reg
	mrc  p15,0,\reg,c2,c0,0
	mov  \reg,\reg
	sub  pc,pc,#4
	.endm

.globl _start
_start:
	ldr	pc, _reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_reset:                 .word reset
_undefined_instruction: .word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef


/*
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * - relocate armboot to ram
 * - setup stack
 * - jump to second stage
 */

.globl _TEXT_BASE
_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end__ - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/* disable mmu, set big-endian */
	mov	r0, #0xf8
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

	/* invalidate I & D caches & BTB */
	mcr	p15, 0, r0, c7, c7, 0
	CPWAIT	r0

	/* invalidate I & Data TLB */
	mcr	p15, 0, r0, c8, c7, 0
	CPWAIT r0

	/* drain write and fill buffers */
	mcr	p15, 0, r0, c7, c10, 4
	CPWAIT	r0

	/* disable write buffer coalescing */
	mrc	p15, 0, r0, c1, c0, 1
	orr	r0, r0, #1
	mcr	p15, 0, r0, c1, c0, 1
	CPWAIT	r0

	/* set EXP CS0 to the optimum timing */
	ldr	r1, =CONFIG_SYS_EXP_CS0
	ldr     r2, =IXP425_EXP_CS0
	str     r1, [r2]

	/* make sure flash is visible at 0 */
	mov	r1, #CONFIG_SYS_SDR_CONFIG
	ldr     r2, =IXP425_SDR_CONFIG
	str     r1, [r2]

	/* disable refresh cycles */
	mov	r1, #0
	ldr     r3, =IXP425_SDR_REFRESH
	str	r1, [r3]

	/* send nop command */
	mov	r1, #3
	ldr	r4, =IXP425_SDR_IR
	str	r1, [r4]
	DELAY_FOR 0x4000, r0

	/* set SDRAM internal refresh val */
	ldr	r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
	str     r1, [r3]
	DELAY_FOR 0x4000, r0

	/* send precharge-all command to close all open banks */
	mov     r1, #2
	str     r1, [r4]
	DELAY_FOR 0x4000, r0

	/* provide 8 auto-refresh cycles */
	mov     r1, #4
	mov     r5, #8
111:    str	r1, [r4]
	DELAY_FOR 0x100, r0
	subs	r5, r5, #1
	bne	111b

	/* set mode register in sdram */
	mov	r1, #CONFIG_SYS_SDR_MODE_CONFIG
	str	r1, [r4]
	DELAY_FOR 0x4000, r0

	/* send normal operation command */
	mov	r1, #6
	str	r1, [r4]
	DELAY_FOR 0x4000, r0

	/* invalidate I & D caches & BTB */
	mcr	p15, 0, r0, c7, c7, 0
	CPWAIT	r0

	/* invalidate I & Data TLB */
	mcr	p15, 0, r0, c8, c7, 0
	CPWAIT r0

	/* drain write and fill buffers */
	mcr	p15, 0, r0, c7, c10, 4
	CPWAIT	r0

	/* remove flash mirror at 0x00000000 */
	ldr	r2, =IXP425_EXP_CFG0
	ldr     r1, [r2]
	bic     r1, r1, #0x80000000
	str     r1, [r2]

	/* invalidate I & Data TLB */
	mcr	p15, 0, r0, c8, c7, 0
	CPWAIT r0

	/* enable I cache */
	mrc     p15, 0, r0, c1, c0, 0
	orr     r0, r0, #MMU_Control_I
	mcr     p15, 0, r0, c1, c0, 0
	CPWAIT  r0

	mrs	r0,cpsr			/* set the cpu to SVC32 mode	    */
	bic	r0,r0,#0x1f		/* (superviser mode, M=10011)	    */
	orr	r0,r0,#0x13
	msr	cpsr,r0

/* Set initial stackpointer in SDRAM to call board_init_f */
call_board_init_f:
	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
	ldr	r0,=0x00000000
	bl	board_init_f

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 */
	.globl	relocate_code
relocate_code:
	mov	r4, r0	/* save addr_sp */
	mov	r5, r1	/* save addr of gd */
	mov	r6, r2	/* save addr of destination */

	/* Set up the stack						    */
stack_setup:
	mov	sp, r4

	adr	r0, _start
	cmp	r0, r6
	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
	beq	clear_bss		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _bss_start_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	sub	r9, r6, r0		/* r9 <- relocation offset */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

clear_bss:
#ifndef CONFIG_SPL_BUILD
	ldr	r0, _bss_start_ofs
	ldr	r1, _bss_end_ofs
	mov	r4, r6			/* reloc addr */
	add	r0, r0, r4
	add	r1, r1, r4
	mov	r2, #0x00000000		/* clear			    */

clbss_l:cmp	r0, r1			/* clear loop... */
	bhs	clbss_e			/* if reached end of bss, exit */
	str	r2, [r0]
	add	r0, r0, #4
	b	clbss_l
clbss_e:

	bl coloured_LED_init
	bl red_led_on
#endif

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */
	ldr	r0, _board_init_r_ofs
	adr	r1, _start
	add	lr, r0, r1
	add	lr, lr, r9
	/* setup parameters for board_init_r */
	mov	r0, r5		/* gd_t */
	mov	r1, r6		/* dest_addr */
	/* jump to it ... */
	mov	pc, lr

_board_init_r_ofs:
	.word board_init_r - _start

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

/****************************************************************************/
/*									    */
/* Interrupt handling							    */
/*									    */
/****************************************************************************/

/* IRQ stack frame							    */

#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13

	/* use bad_save_user_regs for abort/prefetch/undef/swi ...	    */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
	add	r8, sp, #S_PC

	ldr	r2, IRQ_STACK_START_IN
	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r4}			/* save sp_SVC, lr_SVC, pc, cpsr, old_r */
	mov	r0, sp
	.endm


	/* use irq_save_user_regs / irq_restore_user_regs for		     */
	/* IRQ/FIQ handling						     */

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			/* Calling r0-r12	     */
	add	r8, sp, #S_PC
	stmdb	r8, {sp, lr}^			/* Calling SP, LR	     */
	str	lr, [r8, #0]			/* Save calling PC	     */
	mrs	r6, spsr
	str	r6, [r8, #4]			/* Save CPSR		     */
	str	r0, [r8, #8]			/* Save OLD_R0		     */
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str	lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	msr	spsr_c, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm


/****************************************************************************/
/*									    */
/* exception handlers							    */
/*									    */
/****************************************************************************/

	.align	5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	irq_save_user_regs		/* someone ought to write a more    */
	bl	do_fiq			/* effiction fiq_save_user_regs	    */
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif

/****************************************************************************/
/*                                                                          */
/* Reset function: Use Watchdog to reset                                    */
/*                                                                          */
/****************************************************************************/

	.align	5
.globl reset_cpu

reset_cpu:
	ldr	r1, =0x482e
	ldr     r2, =IXP425_OSWK
	str     r1, [r2]
	ldr	r1, =0x0fff
	ldr     r2, =IXP425_OSWT
	str     r1, [r2]
	ldr	r1, =0x5
	ldr     r2, =IXP425_OSWE
	str     r1, [r2]
	b	reset_endless

reset_endless:
	b	reset_endless
Commit	Line	Data
2d5b561e WD	1	/* vi: set ts=8 sw=8 noet: */
	2	/*
	3	* u-boot - Startup Code for XScale IXP
	4	*
	5	* Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
	6	*
	7	* Based on startup code example contained in the
	8	* Intel IXP4xx Programmer's Guide and past u-boot Start.S
	9	* samples.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
25ddd1fb	30	#include <asm-offsets.h>
2d5b561e WD	31	#include <config.h>
	32	#include <version.h>
	33	#include <asm/arch/ixp425.h>
	34
42d1f039 WD	35	#define MMU_Control_M 0x001 /* Enable MMU */
	36	#define MMU_Control_A 0x002 /* Enable address alignment faults */
	37	#define MMU_Control_C 0x004 /* Enable cache */
	38	#define MMU_Control_W 0x008 /* Enable write-buffer */
	39	#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
	40	#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
	41	#define MMU_Control_L 0x040 /* Compatability: */
	42	#define MMU_Control_B 0x080 /* Enable Big-Endian */
	43	#define MMU_Control_S 0x100 /* Enable system protection */
	44	#define MMU_Control_R 0x200 /* Enable ROM protection */
	45	#define MMU_Control_I 0x1000 /* Enable Instruction cache */
	46	#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
2d5b561e WD	47	#define MMU_Control_Init (MMU_Control_P\|MMU_Control_D\|MMU_Control_L)
	48
	49
	50	/*
	51	* Macro definitions
	52	*/
42d1f039 WD	53	/* Delay a bit */
	54	.macro DELAY_FOR cycles, reg0
	55	ldr \reg0, =\cycles
	56	subs \reg0, \reg0, #1
	57	subne pc, pc, #0xc
	58	.endm
	59
	60	/* wait for coprocessor write complete */
	61	.macro CPWAIT reg
	62	mrc p15,0,\reg,c2,c0,0
	63	mov \reg,\reg
	64	sub pc,pc,#4
	65	.endm
2d5b561e WD	66
2d5b561e WD	67	.globl _start
ce04bb41 MS	68	_start:
ce04bb41 MS	69	ldr pc, _reset
2d5b561e WD	70	ldr pc, _undefined_instruction
	71	ldr pc, _software_interrupt
	72	ldr pc, _prefetch_abort
	73	ldr pc, _data_abort
	74	ldr pc, _not_used
	75	ldr pc, _irq
	76	ldr pc, _fiq
	77
ce04bb41	78	_reset: .word reset
2d5b561e WD	79	_undefined_instruction: .word undefined_instruction
	80	_software_interrupt: .word software_interrupt
	81	_prefetch_abort: .word prefetch_abort
	82	_data_abort: .word data_abort
	83	_not_used: .word not_used
	84	_irq: .word irq
	85	_fiq: .word fiq
	86
	87	.balignl 16,0xdeadbeef
	88
	89
	90	/*
	91	* Startup Code (reset vector)
	92	*
	93	* do important init only if we don't start from memory!
	94	* - relocate armboot to ram
	95	* - setup stack
	96	* - jump to second stage
	97	*/
	98
2af0a099	99	.globl _TEXT_BASE
2d5b561e	100	_TEXT_BASE:
14d0a02a	101	.word CONFIG_SYS_TEXT_BASE
2d5b561e	102
2d5b561e	103	/*
f6e20fc6	104	* These are defined in the board-specific linker script.
3336ca60 AA	105	* Subtracting _start from them lets the linker put their
	106	* relative position in the executable instead of leaving
	107	* them null.
2d5b561e	108	*/
3336ca60 AA	109	.globl _bss_start_ofs
	110	_bss_start_ofs:
	111	.word __bss_start - _start
2d5b561e	112
3336ca60 AA	113	.globl _bss_end_ofs
3336ca60 AA	114	_bss_end_ofs:
44c6e659	115	.word __bss_end__ - _start
2d5b561e	116
f326cbba PYC	117	.globl _end_ofs
	118	_end_ofs:
	119	.word _end - _start
	120
2d5b561e WD	121	#ifdef CONFIG_USE_IRQ
	122	/* IRQ stack memory (calculated at run-time) */
	123	.globl IRQ_STACK_START
	124	IRQ_STACK_START:
	125	.word 0x0badc0de
	126
	127	/* IRQ stack memory (calculated at run-time) */
	128	.globl FIQ_STACK_START
	129	FIQ_STACK_START:
	130	.word 0x0badc0de
	131	#endif
	132
2af0a099 HS	133	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	134	.globl IRQ_STACK_START_IN
	135	IRQ_STACK_START_IN:
	136	.word 0x0badc0de
	137
2af0a099 HS	138	/*
	139	* the actual reset code
	140	*/
	141
	142	reset:
	143	/* disable mmu, set big-endian */
	144	mov r0, #0xf8
	145	mcr p15, 0, r0, c1, c0, 0
	146	CPWAIT r0
	147
	148	/* invalidate I & D caches & BTB */
	149	mcr p15, 0, r0, c7, c7, 0
	150	CPWAIT r0
	151
	152	/* invalidate I & Data TLB */
	153	mcr p15, 0, r0, c8, c7, 0
	154	CPWAIT r0
	155
	156	/* drain write and fill buffers */
	157	mcr p15, 0, r0, c7, c10, 4
	158	CPWAIT r0
	159
	160	/* disable write buffer coalescing */
	161	mrc p15, 0, r0, c1, c0, 1
	162	orr r0, r0, #1
	163	mcr p15, 0, r0, c1, c0, 1
	164	CPWAIT r0
	165
	166	/* set EXP CS0 to the optimum timing */
	167	ldr r1, =CONFIG_SYS_EXP_CS0
	168	ldr r2, =IXP425_EXP_CS0
	169	str r1, [r2]
	170
	171	/* make sure flash is visible at 0 */
2af0a099 HS	172	mov r1, #CONFIG_SYS_SDR_CONFIG
	173	ldr r2, =IXP425_SDR_CONFIG
	174	str r1, [r2]
	175
	176	/* disable refresh cycles */
	177	mov r1, #0
	178	ldr r3, =IXP425_SDR_REFRESH
	179	str r1, [r3]
	180
	181	/* send nop command */
	182	mov r1, #3
	183	ldr r4, =IXP425_SDR_IR
	184	str r1, [r4]
	185	DELAY_FOR 0x4000, r0
	186
	187	/* set SDRAM internal refresh val */
	188	ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
	189	str r1, [r3]
	190	DELAY_FOR 0x4000, r0
	191
	192	/* send precharge-all command to close all open banks */
	193	mov r1, #2
	194	str r1, [r4]
	195	DELAY_FOR 0x4000, r0
	196
	197	/* provide 8 auto-refresh cycles */
	198	mov r1, #4
	199	mov r5, #8
	200	111: str r1, [r4]
	201	DELAY_FOR 0x100, r0
	202	subs r5, r5, #1
	203	bne 111b
	204
	205	/* set mode register in sdram */
	206	mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
	207	str r1, [r4]
	208	DELAY_FOR 0x4000, r0
	209
	210	/* send normal operation command */
	211	mov r1, #6
	212	str r1, [r4]
	213	DELAY_FOR 0x4000, r0
	214
2af0a099 HS	215	/* invalidate I & D caches & BTB */
	216	mcr p15, 0, r0, c7, c7, 0
	217	CPWAIT r0
	218
	219	/* invalidate I & Data TLB */
	220	mcr p15, 0, r0, c8, c7, 0
	221	CPWAIT r0
	222
	223	/* drain write and fill buffers */
	224	mcr p15, 0, r0, c7, c10, 4
	225	CPWAIT r0
	226
ce04bb41	227	/* remove flash mirror at 0x00000000 */
2af0a099 HS	228	ldr r2, =IXP425_EXP_CFG0
	229	ldr r1, [r2]
	230	bic r1, r1, #0x80000000
	231	str r1, [r2]
	232
2af0a099 HS	233	/* invalidate I & Data TLB */
	234	mcr p15, 0, r0, c8, c7, 0
	235	CPWAIT r0
	236
	237	/* enable I cache */
	238	mrc p15, 0, r0, c1, c0, 0
	239	orr r0, r0, #MMU_Control_I
	240	mcr p15, 0, r0, c1, c0, 0
	241	CPWAIT r0
	242
	243	mrs r0,cpsr /* set the cpu to SVC32 mode */
	244	bic r0,r0,#0x1f /* (superviser mode, M=10011) */
	245	orr r0,r0,#0x13
	246	msr cpsr,r0
	247
ce04bb41	248	/* Set initial stackpointer in SDRAM to call board_init_f */
2af0a099 HS	249	call_board_init_f:
2af0a099 HS	250	ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
296cae73	251	bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
2af0a099 HS	252	ldr r0,=0x00000000
	253	bl board_init_f
	254
	255	/------------------------------------------------------------------------------/
	256
	257	/*
	258	* void relocate_code (addr_sp, gd, addr_moni)
	259	*
	260	* This "function" does not return, instead it continues in RAM
	261	* after relocating the monitor code.
	262	*
	263	*/
	264	.globl relocate_code
	265	relocate_code:
	266	mov r4, r0 /* save addr_sp */
	267	mov r5, r1 /* save addr of gd */
	268	mov r6, r2 /* save addr of destination */
2af0a099 HS	269
	270	/* Set up the stack */
	271	stack_setup:
	272	mov sp, r4
	273
	274	adr r0, _start
a1a47d3c	275	cmp r0, r6
76abfa57	276	moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
a1a47d3c	277	beq clear_bss /* skip relocation */
a78fb68f	278	mov r1, r6 /* r1 <- scratch for copy_loop */
3336ca60 AA	279	ldr r3, _bss_start_ofs
3336ca60 AA	280	add r2, r0, r3 /* r2 <- source end address */
2af0a099	281
2af0a099 HS	282	copy_loop:
2af0a099 HS	283	ldmia r0!, {r9-r10} /* copy from source address [r0] */
a78fb68f	284	stmia r1!, {r9-r10} /* copy to target address [r1] */
da90d4ce AA	285	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	286	blo copy_loop
2af0a099	287
401bb30b	288	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	289	/*
	290	* fix .rel.dyn relocations
	291	*/
	292	ldr r0, _TEXT_BASE /* r0 <- Text base */
a78fb68f	293	sub r9, r6, r0 /* r9 <- relocation offset */
3336ca60 AA	294	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	295	add r10, r10, r0 /* r10 <- sym table in FLASH */
	296	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	297	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	298	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	299	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
2af0a099	300	fixloop:
3336ca60 AA	301	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	302	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	303	ldr r1, [r2, #4]
1f52d89f AB	304	and r7, r1, #0xff
1f52d89f AB	305	cmp r7, #23 /* relative fixup? */
3336ca60	306	beq fixrel
1f52d89f	307	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	308	beq fixabs
	309	/* ignore unknown type of fixup */
	310	b fixnext
	311	fixabs:
	312	/* absolute fix: set location to (offset) symbol value */
	313	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	314	add r1, r10, r1 /* r1 <- address of symbol in table */
	315	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	316	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	317	b fixnext
	318	fixrel:
	319	/* relative fix: increase location by offset */
	320	ldr r1, [r0]
	321	add r1, r1, r9
	322	fixnext:
	323	str r1, [r0]
	324	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
2af0a099	325	cmp r2, r3
79e63139	326	blo fixloop
2af0a099	327	#endif
2af0a099 HS	328
2af0a099 HS	329	clear_bss:
401bb30b	330	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	331	ldr r0, _bss_start_ofs
3336ca60 AA	332	ldr r1, _bss_end_ofs
a78fb68f	333	mov r4, r6 /* reloc addr */
2af0a099	334	add r0, r0, r4
2af0a099 HS	335	add r1, r1, r4
	336	mov r2, #0x00000000 /* clear */
	337
448217d4 ZH	338	clbss_l:cmp r0, r1 /* clear loop... */
	339	bhs clbss_e /* if reached end of bss, exit */
	340	str r2, [r0]
2af0a099	341	add r0, r0, #4
448217d4 ZH	342	b clbss_l
448217d4 ZH	343	clbss_e:
2af0a099 HS	344
2af0a099 HS	345	bl coloured_LED_init
2d3be7c4	346	bl red_led_on
2af0a099 HS	347	#endif
	348
	349	/*
	350	* We are done. Do not return, instead branch to second part of board
	351	* initialization, now running from RAM.
	352	*/
3336ca60 AA	353	ldr r0, _board_init_r_ofs
	354	adr r1, _start
	355	add lr, r0, r1
	356	add lr, lr, r9
2af0a099 HS	357	/* setup parameters for board_init_r */
2af0a099 HS	358	mov r0, r5 /* gd_t */
a78fb68f	359	mov r1, r6 /* dest_addr */
2af0a099	360	/* jump to it ... */
2af0a099 HS	361	mov pc, lr
2af0a099 HS	362
3336ca60 AA	363	_board_init_r_ofs:
3336ca60 AA	364	.word board_init_r - _start
2af0a099	365
3336ca60 AA	366	_rel_dyn_start_ofs:
	367	.word __rel_dyn_start - _start
	368	_rel_dyn_end_ofs:
	369	.word __rel_dyn_end - _start
	370	_dynsym_start_ofs:
	371	.word __dynsym_start - _start
2d5b561e	372
2d5b561e WD	373	/****************************************************************************/
	374	/* */
	375	/* Interrupt handling */
	376	/* */
	377	/****************************************************************************/
	378
	379	/* IRQ stack frame */
	380
	381	#define S_FRAME_SIZE 72
	382
	383	#define S_OLD_R0 68
	384	#define S_PSR 64
	385	#define S_PC 60
	386	#define S_LR 56
	387	#define S_SP 52
	388
	389	#define S_IP 48
	390	#define S_FP 44
	391	#define S_R10 40
	392	#define S_R9 36
	393	#define S_R8 32
	394	#define S_R7 28
	395	#define S_R6 24
	396	#define S_R5 20
	397	#define S_R4 16
	398	#define S_R3 12
	399	#define S_R2 8
	400	#define S_R1 4
	401	#define S_R0 0
	402
	403	#define MODE_SVC 0x13
	404
	405	/* use bad_save_user_regs for abort/prefetch/undef/swi ... */
	406
	407	.macro bad_save_user_regs
	408	sub sp, sp, #S_FRAME_SIZE
	409	stmia sp, {r0 - r12} /* Calling r0-r12 */
	410	add r8, sp, #S_PC
	411
2af0a099	412	ldr r2, IRQ_STACK_START_IN
2d5b561e WD	413	ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
	414	add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
	415
	416	add r5, sp, #S_SP
	417	mov r1, lr
	418	stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
	419	mov r0, sp
	420	.endm
	421
	422
	423	/* use irq_save_user_regs / irq_restore_user_regs for */
	424	/* IRQ/FIQ handling */
	425
	426	.macro irq_save_user_regs
	427	sub sp, sp, #S_FRAME_SIZE
	428	stmia sp, {r0 - r12} /* Calling r0-r12 */
	429	add r8, sp, #S_PC
	430	stmdb r8, {sp, lr}^ /* Calling SP, LR */
	431	str lr, [r8, #0] /* Save calling PC */
	432	mrs r6, spsr
	433	str r6, [r8, #4] /* Save CPSR */
	434	str r0, [r8, #8] /* Save OLD_R0 */
	435	mov r0, sp
	436	.endm
	437
	438	.macro irq_restore_user_regs
	439	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	440	mov r0, r0
	441	ldr lr, [sp, #S_PC] @ Get PC
	442	add sp, sp, #S_FRAME_SIZE
	443	subs pc, lr, #4 @ return & move spsr_svc into cpsr
	444	.endm
	445
	446	.macro get_bad_stack
2af0a099	447	ldr r13, IRQ_STACK_START_IN @ setup our mode stack
2d5b561e WD	448
	449	str lr, [r13] @ save caller lr / spsr
	450	mrs lr, spsr
	451	str lr, [r13, #4]
	452
	453	mov r13, #MODE_SVC @ prepare SVC-Mode
	454	msr spsr_c, r13
	455	mov lr, pc
	456	movs pc, lr
	457	.endm
	458
	459	.macro get_irq_stack @ setup IRQ stack
	460	ldr sp, IRQ_STACK_START
	461	.endm
	462
	463	.macro get_fiq_stack @ setup FIQ stack
	464	ldr sp, FIQ_STACK_START
	465	.endm
	466
	467
	468	/****************************************************************************/
	469	/* */
	470	/* exception handlers */
	471	/* */
	472	/****************************************************************************/
	473
	474	.align 5
	475	undefined_instruction:
	476	get_bad_stack
	477	bad_save_user_regs
	478	bl do_undefined_instruction
	479
	480	.align 5
	481	software_interrupt:
	482	get_bad_stack
	483	bad_save_user_regs
	484	bl do_software_interrupt
	485
	486	.align 5
	487	prefetch_abort:
	488	get_bad_stack
	489	bad_save_user_regs
	490	bl do_prefetch_abort
	491
	492	.align 5
	493	data_abort:
	494	get_bad_stack
	495	bad_save_user_regs
	496	bl do_data_abort
	497
	498	.align 5
	499	not_used:
	500	get_bad_stack
	501	bad_save_user_regs
	502	bl do_not_used
	503
	504	#ifdef CONFIG_USE_IRQ
	505
	506	.align 5
	507	irq:
	508	get_irq_stack
	509	irq_save_user_regs
	510	bl do_irq
	511	irq_restore_user_regs
512
513	.align 5
514	fiq:
515	get_fiq_stack
516	irq_save_user_regs /* someone ought to write a more */
517	bl do_fiq /* effiction fiq_save_user_regs */
518	irq_restore_user_regs
519
520	#else
521
522	.align 5
523	irq:
524	get_bad_stack
525	bad_save_user_regs
526	bl do_irq
527
528	.align 5
529	fiq:
530	get_bad_stack
531	bad_save_user_regs
532	bl do_fiq
533
534	#endif
535
536	/****************************************************************************/
537	/* */
538	/* Reset function: Use Watchdog to reset */
539	/* */
540	/****************************************************************************/
541
542	.align 5
543	.globl reset_cpu
544
545	reset_cpu:
53677ef1	546	ldr r1, =0x482e
2d5b561e WD	547	ldr r2, =IXP425_OSWK
2d5b561e WD	548	str r1, [r2]
53677ef1	549	ldr r1, =0x0fff
2d5b561e WD	550	ldr r2, =IXP425_OSWT
2d5b561e WD	551	str r1, [r2]
53677ef1	552	ldr r1, =0x5
2d5b561e WD	553	ldr r2, =IXP425_OSWE
	554	str r1, [r2]
	555	b reset_endless
	556
2d5b561e	557	reset_endless:
2d5b561e	558	b reset_endless