[people/ms/u-boot.git] / arch / arm / cpu / s3c44b0 / start.S

/*
 * Startup Code for S3C44B0 CPU-core
 *
 * (C) Copyright 2004
 * DAVE Srl
 *
 * http://www.dave-tech.it
 * http://www.wawnet.biz
 * mailto:info@wawnet.biz
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>

/*
 * Jump vector table
 */


.globl _start
_start:	b       reset
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate u-boot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	bl	lowlevel_init
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 */
	.globl	relocate_code
relocate_code:
	mov	r4, r0	/* save addr_sp */
	mov	r5, r1	/* save addr of gd */
	mov	r6, r2	/* save addr of destination */

	adr	r0, _start
	cmp	r0, r6
	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _bss_start_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	sub	r9, r6, r0		/* r9 <- relocation offset */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

relocate_done:

	bx	lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	bx	lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */

#define INTCON (0x01c00000+0x200000)
#define INTMSK (0x01c00000+0x20000c)
#define LOCKTIME (0x01c00000+0x18000c)
#define PLLCON (0x01c00000+0x180000)
#define CLKCON (0x01c00000+0x180004)
#define WTCON (0x01c00000+0x130000)
cpu_init_crit:
	/* disable watch dog */
	ldr	r0, =WTCON
	ldr	r1, =0x0
	str	r1, [r0]

	/*
	 * mask all IRQs by clearing all bits in the INTMRs
	 */
	ldr	r1,=INTMSK
	ldr	r0, =0x03fffeff
	str	r0, [r1]

	ldr	r1, =INTCON
	ldr	r0, =0x05
	str	r0, [r1]

	/* Set Clock Control Register */
	ldr	r1, =LOCKTIME
	ldrb	r0, =800
	strb	r0, [r1]

	ldr	r1, =PLLCON

#if CONFIG_S3C44B0_CLOCK_SPEED==66
	ldr	r0, =0x34031	/* 66MHz (Quartz=11MHz) */
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
	ldr	r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif

	str	r0, [r1]

	ldr	r1,=CLKCON
	ldr	r0, =0x7ff8
	str	r0, [r1]

	mov	pc, lr


/*************************************************/
/*	interrupt vectors	*/
/*************************************************/
real_vectors:
	b	reset
	b	undefined_instruction
	b	software_interrupt
	b	prefetch_abort
	b	data_abort
	b	not_used
	b	irq
	b	fiq

/*************************************************/

undefined_instruction:
	mov	r6, #3
	b	reset

software_interrupt:
	mov	r6, #4
	b	reset

prefetch_abort:
	mov	r6, #5
	b	reset

data_abort:
	mov	r6, #6
	b	reset

not_used:
	/* we *should* never reach this */
	mov	r6, #7
	b	reset

irq:
	mov	r6, #8
	b	reset

fiq:
	mov	r6, #9
	b	reset
Commit	Line	Data
074cff0d WD	1	/*
	2	* Startup Code for S3C44B0 CPU-core
	3	*
	4	* (C) Copyright 2004
	5	* DAVE Srl
	6	*
	7	* http://www.dave-tech.it
	8	* http://www.wawnet.biz
	9	* mailto:info@wawnet.biz
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
25ddd1fb	30	#include <asm-offsets.h>
074cff0d WD	31	#include <config.h>
	32	#include <version.h>
	33
074cff0d WD	34	/*
	35	* Jump vector table
	36	*/
	37
	38
	39	.globl _start
	40	_start: b reset
	41	add pc, pc, #0x0c000000
	42	add pc, pc, #0x0c000000
	43	add pc, pc, #0x0c000000
	44	add pc, pc, #0x0c000000
	45	add pc, pc, #0x0c000000
	46	add pc, pc, #0x0c000000
	47	add pc, pc, #0x0c000000
	48
	49	.balignl 16,0xdeadbeef
	50
	51
	52	/*
	53	*************************************************************************
	54	*
	55	* Startup Code (reset vector)
	56	*
	57	* do important init only if we don't start from memory!
	58	* relocate u-boot to ram
	59	* setup stack
	60	* jump to second stage
	61	*
	62	*************************************************************************
	63	*/
	64
0110955a	65	.globl _TEXT_BASE
074cff0d	66	_TEXT_BASE:
14d0a02a	67	.word CONFIG_SYS_TEXT_BASE
074cff0d	68
074cff0d	69	/*
42dfe7a1	70	* These are defined in the board-specific linker script.
3336ca60 AA	71	* Subtracting _start from them lets the linker put their
	72	* relative position in the executable instead of leaving
	73	* them null.
074cff0d	74	*/
3336ca60 AA	75	.globl _bss_start_ofs
	76	_bss_start_ofs:
	77	.word __bss_start - _start
42dfe7a1	78
3336ca60 AA	79	.globl _bss_end_ofs
3336ca60 AA	80	_bss_end_ofs:
3929fb0a	81	.word __bss_end - _start
074cff0d	82
f326cbba PYC	83	.globl _end_ofs
	84	_end_ofs:
	85	.word _end - _start
	86
074cff0d WD	87	#ifdef CONFIG_USE_IRQ
	88	/* IRQ stack memory (calculated at run-time) */
	89	.globl IRQ_STACK_START
	90	IRQ_STACK_START:
	91	.word 0x0badc0de
	92
	93	/* IRQ stack memory (calculated at run-time) */
	94	.globl FIQ_STACK_START
	95	FIQ_STACK_START:
	96	.word 0x0badc0de
	97	#endif
	98
0110955a HS	99	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	100	.globl IRQ_STACK_START_IN
	101	IRQ_STACK_START_IN:
	102	.word 0x0badc0de
	103
0110955a HS	104	/*
	105	* the actual reset code
	106	*/
	107
	108	reset:
	109	/*
	110	* set the cpu to SVC32 mode
	111	*/
	112	mrs r0,cpsr
	113	bic r0,r0,#0x1f
	114	orr r0,r0,#0xd3
	115	msr cpsr,r0
	116
	117	/*
	118	* we do sys-critical inits only at reboot,
	119	* not when booting from ram!
	120	*/
	121	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	122	bl cpu_init_crit
	123	/*
	124	* before relocating, we have to setup RAM timing
	125	* because memory timing is board-dependend, you will
	126	* find a lowlevel_init.S in your board directory.
	127	*/
	128	bl lowlevel_init
	129	#endif
	130
e05e5de7	131	bl _main
0110955a HS	132
	133	/------------------------------------------------------------------------------/
	134
	135	/*
	136	* void relocate_code (addr_sp, gd, addr_moni)
	137	*
	138	* This "function" does not return, instead it continues in RAM
	139	* after relocating the monitor code.
	140	*
	141	*/
	142	.globl relocate_code
	143	relocate_code:
	144	mov r4, r0 /* save addr_sp */
	145	mov r5, r1 /* save addr of gd */
	146	mov r6, r2 /* save addr of destination */
0110955a	147
0110955a	148	adr r0, _start
a1a47d3c	149	cmp r0, r6
76abfa57	150	moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
e05e5de7	151	beq relocate_done /* skip relocation */
a78fb68f	152	mov r1, r6 /* r1 <- scratch for copy_loop */
3336ca60 AA	153	ldr r3, _bss_start_ofs
3336ca60 AA	154	add r2, r0, r3 /* r2 <- source end address */
0110955a	155
0110955a HS	156	copy_loop:
0110955a HS	157	ldmia r0!, {r9-r10} /* copy from source address [r0] */
a78fb68f	158	stmia r1!, {r9-r10} /* copy to target address [r1] */
da90d4ce AA	159	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	160	blo copy_loop
0110955a	161
401bb30b	162	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	163	/*
	164	* fix .rel.dyn relocations
	165	*/
	166	ldr r0, _TEXT_BASE /* r0 <- Text base */
a78fb68f	167	sub r9, r6, r0 /* r9 <- relocation offset */
3336ca60 AA	168	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	169	add r10, r10, r0 /* r10 <- sym table in FLASH */
	170	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	171	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	172	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	173	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
0110955a	174	fixloop:
3336ca60 AA	175	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	176	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	177	ldr r1, [r2, #4]
1f52d89f AB	178	and r7, r1, #0xff
1f52d89f AB	179	cmp r7, #23 /* relative fixup? */
3336ca60	180	beq fixrel
1f52d89f	181	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	182	beq fixabs
	183	/* ignore unknown type of fixup */
	184	b fixnext
	185	fixabs:
	186	/* absolute fix: set location to (offset) symbol value */
	187	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	188	add r1, r10, r1 /* r1 <- address of symbol in table */
	189	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	190	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	191	b fixnext
	192	fixrel:
	193	/* relative fix: increase location by offset */
	194	ldr r1, [r0]
	195	add r1, r1, r9
	196	fixnext:
	197	str r1, [r0]
	198	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
0110955a	199	cmp r2, r3
79e63139	200	blo fixloop
0110955a	201	#endif
0110955a	202
e05e5de7	203	relocate_done:
074cff0d	204
e05e5de7	205	bx lr
3336ca60 AA	206
	207	_rel_dyn_start_ofs:
	208	.word __rel_dyn_start - _start
	209	_rel_dyn_end_ofs:
	210	.word __rel_dyn_end - _start
	211	_dynsym_start_ofs:
	212	.word __dynsym_start - _start
0110955a	213
e05e5de7 AA	214	.globl c_runtime_cpu_setup
	215	c_runtime_cpu_setup:
	216
	217	bx lr
	218
074cff0d WD	219	/*
	220	*************************************************************************
	221	*
	222	* CPU_init_critical registers
	223	*
	224	* setup important registers
	225	* setup memory timing
	226	*
	227	*************************************************************************
	228	*/
	229
	230	#define INTCON (0x01c00000+0x200000)
	231	#define INTMSK (0x01c00000+0x20000c)
	232	#define LOCKTIME (0x01c00000+0x18000c)
	233	#define PLLCON (0x01c00000+0x180000)
	234	#define CLKCON (0x01c00000+0x180004)
	235	#define WTCON (0x01c00000+0x130000)
	236	cpu_init_crit:
	237	/* disable watch dog */
53677ef1	238	ldr r0, =WTCON
074cff0d WD	239	ldr r1, =0x0
	240	str r1, [r0]
	241
	242	/*
	243	* mask all IRQs by clearing all bits in the INTMRs
	244	*/
	245	ldr r1,=INTMSK
	246	ldr r0, =0x03fffeff
	247	str r0, [r1]
	248
	249	ldr r1, =INTCON
	250	ldr r0, =0x05
	251	str r0, [r1]
	252
	253	/* Set Clock Control Register */
	254	ldr r1, =LOCKTIME
	255	ldrb r0, =800
	256	strb r0, [r1]
	257
	258	ldr r1, =PLLCON
	259
	260	#if CONFIG_S3C44B0_CLOCK_SPEED==66
53677ef1	261	ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
074cff0d WD	262	#elif CONFIG_S3C44B0_CLOCK_SPEED==75
	263	ldr r0, =0x610c1 /B2: Xtal=20mhz Fclk=75MHz /
	264	#else
	265	# error CONFIG_S3C44B0_CLOCK_SPEED undefined
	266	#endif
	267
	268	str r0, [r1]
	269
	270	ldr r1,=CLKCON
	271	ldr r0, =0x7ff8
	272	str r0, [r1]
	273
	274	mov pc, lr
	275
	276
	277	/*************************************************/
	278	/* interrupt vectors */
	279	/*************************************************/
	280	real_vectors:
	281	b reset
	282	b undefined_instruction
	283	b software_interrupt
	284	b prefetch_abort
	285	b data_abort
	286	b not_used
	287	b irq
	288	b fiq
	289
	290	/*************************************************/
	291
	292	undefined_instruction:
	293	mov r6, #3
	294	b reset
	295
	296	software_interrupt:
	297	mov r6, #4
	298	b reset
	299
	300	prefetch_abort:
	301	mov r6, #5
	302	b reset
	303
	304	data_abort:
	305	mov r6, #6
	306	b reset
	307
	308	not_used:
	309	/* we should never reach this */
	310	mov r6, #7
	311	b reset
	312
	313	irq:
	314	mov r6, #8
	315	b reset
	316
	317	fiq:
	318	mov r6, #9
	319	b reset