[people/ms/u-boot.git] / arch / arm / cpu / s3c44b0 / start.S

/*
 * Startup Code for S3C44B0 CPU-core
 *
 * (C) Copyright 2004
 * DAVE Srl
 *
 * http://www.dave-tech.it
 * http://www.wawnet.biz
 * mailto:info@wawnet.biz
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>

/*
 * Jump vector table
 */


.globl _start
_start:	b       reset
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate u-boot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	.word	CONFIG_SPL_TEXT_BASE
#else
	.word	CONFIG_SYS_TEXT_BASE
#endif

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	bl	lowlevel_init
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 */
	.globl	relocate_code
relocate_code:
	mov	r4, r0	/* save addr_sp */
	mov	r5, r1	/* save addr of gd */
	mov	r6, r2	/* save addr of destination */

	adr	r0, _start
	cmp	r0, r6
	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _bss_start_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	sub	r9, r6, r0		/* r9 <- relocation offset */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

relocate_done:

	bx	lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	bx	lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */

#define INTCON (0x01c00000+0x200000)
#define INTMSK (0x01c00000+0x20000c)
#define LOCKTIME (0x01c00000+0x18000c)
#define PLLCON (0x01c00000+0x180000)
#define CLKCON (0x01c00000+0x180004)
#define WTCON (0x01c00000+0x130000)
cpu_init_crit:
	/* disable watch dog */
	ldr	r0, =WTCON
	ldr	r1, =0x0
	str	r1, [r0]

	/*
	 * mask all IRQs by clearing all bits in the INTMRs
	 */
	ldr	r1,=INTMSK
	ldr	r0, =0x03fffeff
	str	r0, [r1]

	ldr	r1, =INTCON
	ldr	r0, =0x05
	str	r0, [r1]

	/* Set Clock Control Register */
	ldr	r1, =LOCKTIME
	ldrb	r0, =800
	strb	r0, [r1]

	ldr	r1, =PLLCON

#if CONFIG_S3C44B0_CLOCK_SPEED==66
	ldr	r0, =0x34031	/* 66MHz (Quartz=11MHz) */
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
	ldr	r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif

	str	r0, [r1]

	ldr	r1,=CLKCON
	ldr	r0, =0x7ff8
	str	r0, [r1]

	mov	pc, lr


/*************************************************/
/*	interrupt vectors	*/
/*************************************************/
real_vectors:
	b	reset
	b	undefined_instruction
	b	software_interrupt
	b	prefetch_abort
	b	data_abort
	b	not_used
	b	irq
	b	fiq

/*************************************************/

undefined_instruction:
	mov	r6, #3
	b	reset

software_interrupt:
	mov	r6, #4
	b	reset

prefetch_abort:
	mov	r6, #5
	b	reset

data_abort:
	mov	r6, #6
	b	reset

not_used:
	/* we *should* never reach this */
	mov	r6, #7
	b	reset

irq:
	mov	r6, #8
	b	reset

fiq:
	mov	r6, #9
	b	reset
Commit	Line	Data
074cff0d WD	1	/*
	2	* Startup Code for S3C44B0 CPU-core
	3	*
	4	* (C) Copyright 2004
	5	* DAVE Srl
	6	*
	7	* http://www.dave-tech.it
	8	* http://www.wawnet.biz
	9	* mailto:info@wawnet.biz
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
25ddd1fb	30	#include <asm-offsets.h>
074cff0d WD	31	#include <config.h>
	32	#include <version.h>
	33
074cff0d WD	34	/*
	35	* Jump vector table
	36	*/
	37
	38
	39	.globl _start
	40	_start: b reset
	41	add pc, pc, #0x0c000000
	42	add pc, pc, #0x0c000000
	43	add pc, pc, #0x0c000000
	44	add pc, pc, #0x0c000000
	45	add pc, pc, #0x0c000000
	46	add pc, pc, #0x0c000000
	47	add pc, pc, #0x0c000000
	48
	49	.balignl 16,0xdeadbeef
	50
	51
	52	/*
	53	*************************************************************************
	54	*
	55	* Startup Code (reset vector)
	56	*
	57	* do important init only if we don't start from memory!
	58	* relocate u-boot to ram
	59	* setup stack
	60	* jump to second stage
	61	*
	62	*************************************************************************
	63	*/
	64
0110955a	65	.globl _TEXT_BASE
074cff0d	66	_TEXT_BASE:
508611bc BT	67	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	68	.word CONFIG_SPL_TEXT_BASE
	69	#else
14d0a02a	70	.word CONFIG_SYS_TEXT_BASE
508611bc	71	#endif
074cff0d	72
074cff0d	73	/*
42dfe7a1	74	* These are defined in the board-specific linker script.
3336ca60 AA	75	* Subtracting _start from them lets the linker put their
	76	* relative position in the executable instead of leaving
	77	* them null.
074cff0d	78	*/
3336ca60 AA	79	.globl _bss_start_ofs
	80	_bss_start_ofs:
	81	.word __bss_start - _start
42dfe7a1	82
3336ca60 AA	83	.globl _bss_end_ofs
3336ca60 AA	84	_bss_end_ofs:
3929fb0a	85	.word __bss_end - _start
074cff0d	86
f326cbba PYC	87	.globl _end_ofs
	88	_end_ofs:
	89	.word _end - _start
	90
074cff0d WD	91	#ifdef CONFIG_USE_IRQ
	92	/* IRQ stack memory (calculated at run-time) */
	93	.globl IRQ_STACK_START
	94	IRQ_STACK_START:
	95	.word 0x0badc0de
	96
	97	/* IRQ stack memory (calculated at run-time) */
	98	.globl FIQ_STACK_START
	99	FIQ_STACK_START:
	100	.word 0x0badc0de
	101	#endif
	102
0110955a HS	103	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	104	.globl IRQ_STACK_START_IN
	105	IRQ_STACK_START_IN:
	106	.word 0x0badc0de
	107
0110955a HS	108	/*
	109	* the actual reset code
	110	*/
	111
	112	reset:
	113	/*
	114	* set the cpu to SVC32 mode
	115	*/
	116	mrs r0,cpsr
	117	bic r0,r0,#0x1f
	118	orr r0,r0,#0xd3
	119	msr cpsr,r0
	120
	121	/*
	122	* we do sys-critical inits only at reboot,
	123	* not when booting from ram!
	124	*/
	125	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	126	bl cpu_init_crit
	127	/*
	128	* before relocating, we have to setup RAM timing
	129	* because memory timing is board-dependend, you will
	130	* find a lowlevel_init.S in your board directory.
	131	*/
	132	bl lowlevel_init
	133	#endif
	134
e05e5de7	135	bl _main
0110955a HS	136
	137	/------------------------------------------------------------------------------/
	138
	139	/*
	140	* void relocate_code (addr_sp, gd, addr_moni)
	141	*
	142	* This "function" does not return, instead it continues in RAM
	143	* after relocating the monitor code.
	144	*
	145	*/
	146	.globl relocate_code
	147	relocate_code:
	148	mov r4, r0 /* save addr_sp */
	149	mov r5, r1 /* save addr of gd */
	150	mov r6, r2 /* save addr of destination */
0110955a	151
0110955a	152	adr r0, _start
a1a47d3c	153	cmp r0, r6
76abfa57	154	moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
e05e5de7	155	beq relocate_done /* skip relocation */
a78fb68f	156	mov r1, r6 /* r1 <- scratch for copy_loop */
3336ca60 AA	157	ldr r3, _bss_start_ofs
3336ca60 AA	158	add r2, r0, r3 /* r2 <- source end address */
0110955a	159
0110955a HS	160	copy_loop:
0110955a HS	161	ldmia r0!, {r9-r10} /* copy from source address [r0] */
a78fb68f	162	stmia r1!, {r9-r10} /* copy to target address [r1] */
da90d4ce AA	163	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	164	blo copy_loop
0110955a	165
401bb30b	166	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	167	/*
	168	* fix .rel.dyn relocations
	169	*/
	170	ldr r0, _TEXT_BASE /* r0 <- Text base */
a78fb68f	171	sub r9, r6, r0 /* r9 <- relocation offset */
3336ca60 AA	172	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	173	add r10, r10, r0 /* r10 <- sym table in FLASH */
	174	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	175	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	176	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	177	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
0110955a	178	fixloop:
3336ca60 AA	179	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	180	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	181	ldr r1, [r2, #4]
1f52d89f AB	182	and r7, r1, #0xff
1f52d89f AB	183	cmp r7, #23 /* relative fixup? */
3336ca60	184	beq fixrel
1f52d89f	185	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	186	beq fixabs
	187	/* ignore unknown type of fixup */
	188	b fixnext
	189	fixabs:
	190	/* absolute fix: set location to (offset) symbol value */
	191	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	192	add r1, r10, r1 /* r1 <- address of symbol in table */
	193	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	194	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	195	b fixnext
	196	fixrel:
	197	/* relative fix: increase location by offset */
	198	ldr r1, [r0]
	199	add r1, r1, r9
	200	fixnext:
	201	str r1, [r0]
	202	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
0110955a	203	cmp r2, r3
79e63139	204	blo fixloop
0110955a	205	#endif
0110955a	206
e05e5de7	207	relocate_done:
074cff0d	208
e05e5de7	209	bx lr
3336ca60 AA	210
	211	_rel_dyn_start_ofs:
	212	.word __rel_dyn_start - _start
	213	_rel_dyn_end_ofs:
	214	.word __rel_dyn_end - _start
	215	_dynsym_start_ofs:
	216	.word __dynsym_start - _start
0110955a	217
e05e5de7 AA	218	.globl c_runtime_cpu_setup
	219	c_runtime_cpu_setup:
	220
	221	bx lr
	222
074cff0d WD	223	/*
	224	*************************************************************************
	225	*
	226	* CPU_init_critical registers
	227	*
	228	* setup important registers
	229	* setup memory timing
	230	*
	231	*************************************************************************
	232	*/
	233
	234	#define INTCON (0x01c00000+0x200000)
	235	#define INTMSK (0x01c00000+0x20000c)
	236	#define LOCKTIME (0x01c00000+0x18000c)
	237	#define PLLCON (0x01c00000+0x180000)
	238	#define CLKCON (0x01c00000+0x180004)
	239	#define WTCON (0x01c00000+0x130000)
	240	cpu_init_crit:
	241	/* disable watch dog */
53677ef1	242	ldr r0, =WTCON
074cff0d WD	243	ldr r1, =0x0
	244	str r1, [r0]
	245
	246	/*
	247	* mask all IRQs by clearing all bits in the INTMRs
	248	*/
	249	ldr r1,=INTMSK
	250	ldr r0, =0x03fffeff
	251	str r0, [r1]
	252
	253	ldr r1, =INTCON
	254	ldr r0, =0x05
	255	str r0, [r1]
	256
	257	/* Set Clock Control Register */
	258	ldr r1, =LOCKTIME
	259	ldrb r0, =800
	260	strb r0, [r1]
	261
	262	ldr r1, =PLLCON
	263
	264	#if CONFIG_S3C44B0_CLOCK_SPEED==66
53677ef1	265	ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
074cff0d WD	266	#elif CONFIG_S3C44B0_CLOCK_SPEED==75
	267	ldr r0, =0x610c1 /B2: Xtal=20mhz Fclk=75MHz /
	268	#else
	269	# error CONFIG_S3C44B0_CLOCK_SPEED undefined
	270	#endif
	271
	272	str r0, [r1]
	273
	274	ldr r1,=CLKCON
	275	ldr r0, =0x7ff8
	276	str r0, [r1]
	277
	278	mov pc, lr
	279
	280
	281	/*************************************************/
	282	/* interrupt vectors */
	283	/*************************************************/
	284	real_vectors:
	285	b reset
	286	b undefined_instruction
	287	b software_interrupt
	288	b prefetch_abort
	289	b data_abort
	290	b not_used
	291	b irq
	292	b fiq
	293
	294	/*************************************************/
	295
	296	undefined_instruction:
	297	mov r6, #3
	298	b reset
	299
	300	software_interrupt:
	301	mov r6, #4
	302	b reset
	303
	304	prefetch_abort:
	305	mov r6, #5
	306	b reset
	307
	308	data_abort:
	309	mov r6, #6
	310	b reset
	311
	312	not_used:
	313	/* we should never reach this */
	314	mov r6, #7
	315	b reset
	316
	317	irq:
	318	mov r6, #8
	319	b reset
	320
	321	fiq:
	322	mov r6, #9
	323	b reset