[thirdparty/u-boot.git] / arch / arm / cpu / sa1100 / start.S

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 *  armboot - Startup Code for SA1100 CPU
 *
 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
 *  Copyright (c) 2001	Alex Züpke <azu@sysgo.de>
 */

#include <asm-offsets.h>
#include <config.h>

/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

	.globl	reset

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	mov	pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


/* Interrupt-Controller base address */
IC_BASE:	.word	0x90050000
#define ICMR	0x04


/* Reset-Controller */
RST_BASE:		.word   0x90030000
#define RSRR	0x00
#define RCSR	0x04


/* PWR */
PWR_BASE:		.word   0x90020000
#define PSPR    0x08
#define PPCR    0x14
cpuspeed:		.word   CONFIG_SYS_CPUSPEED


cpu_init_crit:
	/*
	 * mask all IRQs
	 */
	ldr	r0, IC_BASE
	mov	r1, #0x00
	str	r1, [r0, #ICMR]

	/* set clock speed */
	ldr	r0, PWR_BASE
	ldr	r1, cpuspeed
	str	r1, [r0, #PPCR]

#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	mov	ip,	lr
	bl	lowlevel_init
	mov	lr,	ip
#endif

	/*
	 * disable MMU stuff and enable I-cache
	 */
	mrc	p15,0,r0,c1,c0
	bic	r0, r0, #0x00002000	@ clear bit 13 (X)
	bic	r0, r0, #0x0000000f	@ clear bits 3-0 (WCAM)
	orr	r0, r0, #0x00001000	@ set bit 12 (I) Icache
	orr	r0, r0, #0x00000002	@ set bit 1 (A) Align
	mcr	p15,0,r0,c1,c0

	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	mov	pc, lr
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
fe8c2806 WD	2	/*
	3	* armboot - Startup Code for SA1100 CPU
	4	*
	5	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
	6	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
	7	* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
fa82f871	8	* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
fe8c2806 WD	9	*/
fe8c2806 WD	10
25ddd1fb	11	#include <asm-offsets.h>
fe8c2806	12	#include <config.h>
fe8c2806	13
fe8c2806 WD	14	/*
	15	*************************************************************************
	16	*
	17	* Startup Code (reset vector)
	18	*
	19	* do important init only if we don't start from memory!
	20	* relocate armboot to ram
	21	* setup stack
	22	* jump to second stage
	23	*
	24	*************************************************************************
	25	*/
	26
41623c91	27	.globl reset
e30ceca2 HS	28
	29	reset:
	30	/*
	31	* set the cpu to SVC32 mode
	32	*/
	33	mrs r0,cpsr
	34	bic r0,r0,#0x1f
	35	orr r0,r0,#0xd3
	36	msr cpsr,r0
	37
	38	/*
	39	* we do sys-critical inits only at reboot,
	40	* not when booting from ram!
	41	*/
	42	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	43	bl cpu_init_crit
	44	#endif
	45
e05e5de7	46	bl _main
e30ceca2 HS	47
	48	/------------------------------------------------------------------------------/
	49
e05e5de7 AA	50	.globl c_runtime_cpu_setup
	51	c_runtime_cpu_setup:
	52
	53	mov pc, lr
	54
fe8c2806 WD	55	/*
	56	*************************************************************************
	57	*
	58	* CPU_init_critical registers
	59	*
	60	* setup important registers
	61	* setup memory timing
	62	*
	63	*************************************************************************
	64	*/
	65
	66
16263087	67	/* Interrupt-Controller base address */
fe8c2806 WD	68	IC_BASE: .word 0x90050000
	69	#define ICMR 0x04
	70
	71
	72	/* Reset-Controller */
	73	RST_BASE: .word 0x90030000
	74	#define RSRR 0x00
	75	#define RCSR 0x04
	76
	77
	78	/* PWR */
	79	PWR_BASE: .word 0x90020000
	80	#define PSPR 0x08
	81	#define PPCR 0x14
6d0f6bcf	82	cpuspeed: .word CONFIG_SYS_CPUSPEED
fe8c2806 WD	83
	84
	85	cpu_init_crit:
	86	/*
	87	* mask all IRQs
	88	*/
	89	ldr r0, IC_BASE
	90	mov r1, #0x00
	91	str r1, [r0, #ICMR]
	92
	93	/* set clock speed */
	94	ldr r0, PWR_BASE
	95	ldr r1, cpuspeed
	96	str r1, [r0, #PPCR]
	97
b5bd0982	98	#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
fe8c2806 WD	99	/*
	100	* before relocating, we have to setup RAM timing
	101	* because memory timing is board-dependend, you will
400558b5	102	* find a lowlevel_init.S in your board directory.
fe8c2806 WD	103	*/
fe8c2806 WD	104	mov ip, lr
400558b5	105	bl lowlevel_init
fe8c2806	106	mov lr, ip
b5bd0982	107	#endif
fe8c2806 WD	108
	109	/*
	110	* disable MMU stuff and enable I-cache
	111	*/
	112	mrc p15,0,r0,c1,c0
	113	bic r0, r0, #0x00002000 @ clear bit 13 (X)
	114	bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
	115	orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
ba10b852	116	orr r0, r0, #0x00000002 @ set bit 1 (A) Align
fe8c2806 WD	117	mcr p15,0,r0,c1,c0
	118
	119	/*
	120	* flush v4 I/D caches
	121	*/
	122	mov r0, #0
	123	mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
	124	mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
	125
	126	mov pc, lr