[people/ms/u-boot.git] / arch / arm / cpu / sa1100 / start.S

/*
 *  armboot - Startup Code for SA1100 CPU
 *
 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
 *  Copyright (c) 2001	Alex Züpke <azu@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start:	b       reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction:	.word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	.word	CONFIG_SPL_TEXT_BASE
#else
	.word	CONFIG_SYS_TEXT_BASE
#endif

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This function relocates the monitor code.
 */
	.globl	relocate_code
relocate_code:
	mov	r4, r0	/* save addr_sp */
	mov	r5, r1	/* save addr of gd */
	mov	r6, r2	/* save addr of destination */

	adr	r0, _start
	cmp	r0, r6
	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _bss_start_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	sub	r9, r6, r0		/* r9 <- relocation offset */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

relocate_done:

	mov	pc, lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	mov	pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


/* Interrupt-Controller base address */
IC_BASE:	.word	0x90050000
#define ICMR	0x04


/* Reset-Controller */
RST_BASE:		.word   0x90030000
#define RSRR	0x00
#define RCSR	0x04


/* PWR */
PWR_BASE:		.word   0x90020000
#define PSPR    0x08
#define PPCR    0x14
cpuspeed:		.word   CONFIG_SYS_CPUSPEED


cpu_init_crit:
	/*
	 * mask all IRQs
	 */
	ldr	r0, IC_BASE
	mov	r1, #0x00
	str	r1, [r0, #ICMR]

	/* set clock speed */
	ldr	r0, PWR_BASE
	ldr	r1, cpuspeed
	str	r1, [r0, #PPCR]

	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	mov	ip,	lr
	bl	lowlevel_init
	mov	lr,	ip

	/*
	 * disable MMU stuff and enable I-cache
	 */
	mrc	p15,0,r0,c1,c0
	bic	r0, r0, #0x00002000	@ clear bit 13 (X)
	bic	r0, r0, #0x0000000f	@ clear bits 3-0 (WCAM)
	orr	r0, r0, #0x00001000	@ set bit 12 (I) Icache
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	mcr	p15,0,r0,c1,c0

	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	mov	pc, lr


/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add     r8, sp, #S_PC

	ldr	r2, IRQ_STACK_START_IN
	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
	mov	r0, sp
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add     r8, sp, #S_PC
	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
	str     lr, [r8, #0]                    @ Save calling PC
	mrs     r6, spsr
	str     r6, [r8, #4]                    @ Save CPSR
	str     r0, [r8, #8]                    @ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str     lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	msr	spsr_c, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif

	.align	5
.globl reset_cpu
reset_cpu:
	ldr	r0, RST_BASE
	mov	r1, #0x0			@ set bit 3-0 ...
	str	r1, [r0, #RCSR]			@ ... to clear in RCSR
	mov	r1, #0x1
	str	r1, [r0, #RSRR]			@ and perform reset
	b	reset_cpu			@ silly, but repeat endlessly
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* armboot - Startup Code for SA1100 CPU
	3	*
	4	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
	5	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
	6	* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
fa82f871	7	* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
fe8c2806 WD	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
25ddd1fb	28	#include <asm-offsets.h>
fe8c2806 WD	29	#include <config.h>
	30	#include <version.h>
	31
fe8c2806 WD	32	/*
	33	*************************************************************************
	34	*
	35	* Jump vector table as in table 3.1 in [1]
	36	*
	37	*************************************************************************
	38	*/
	39
	40
	41	.globl _start
	42	_start: b reset
	43	ldr pc, _undefined_instruction
	44	ldr pc, _software_interrupt
	45	ldr pc, _prefetch_abort
	46	ldr pc, _data_abort
	47	ldr pc, _not_used
	48	ldr pc, _irq
	49	ldr pc, _fiq
	50
	51	_undefined_instruction: .word undefined_instruction
	52	_software_interrupt: .word software_interrupt
	53	_prefetch_abort: .word prefetch_abort
	54	_data_abort: .word data_abort
	55	_not_used: .word not_used
	56	_irq: .word irq
	57	_fiq: .word fiq
	58
	59	.balignl 16,0xdeadbeef
	60
	61
	62	/*
	63	*************************************************************************
	64	*
	65	* Startup Code (reset vector)
	66	*
	67	* do important init only if we don't start from memory!
	68	* relocate armboot to ram
	69	* setup stack
	70	* jump to second stage
	71	*
	72	*************************************************************************
	73	*/
	74
e30ceca2	75	.globl _TEXT_BASE
fe8c2806	76	_TEXT_BASE:
508611bc BT	77	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	78	.word CONFIG_SPL_TEXT_BASE
	79	#else
14d0a02a	80	.word CONFIG_SYS_TEXT_BASE
508611bc	81	#endif
fe8c2806	82
fe8c2806	83	/*
f6e20fc6	84	* These are defined in the board-specific linker script.
3336ca60 AA	85	* Subtracting _start from them lets the linker put their
	86	* relative position in the executable instead of leaving
	87	* them null.
fe8c2806	88	*/
3336ca60 AA	89	.globl _bss_start_ofs
	90	_bss_start_ofs:
	91	.word __bss_start - _start
f6e20fc6	92
3336ca60 AA	93	.globl _bss_end_ofs
3336ca60 AA	94	_bss_end_ofs:
3929fb0a	95	.word __bss_end - _start
fe8c2806	96
f326cbba PYC	97	.globl _end_ofs
	98	_end_ofs:
	99	.word _end - _start
	100
fe8c2806 WD	101	#ifdef CONFIG_USE_IRQ
	102	/* IRQ stack memory (calculated at run-time) */
	103	.globl IRQ_STACK_START
	104	IRQ_STACK_START:
	105	.word 0x0badc0de
	106
	107	/* IRQ stack memory (calculated at run-time) */
	108	.globl FIQ_STACK_START
	109	FIQ_STACK_START:
	110	.word 0x0badc0de
	111	#endif
	112
e30ceca2 HS	113	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	114	.globl IRQ_STACK_START_IN
	115	IRQ_STACK_START_IN:
	116	.word 0x0badc0de
	117
e30ceca2 HS	118	/*
	119	* the actual reset code
	120	*/
	121
	122	reset:
	123	/*
	124	* set the cpu to SVC32 mode
	125	*/
	126	mrs r0,cpsr
	127	bic r0,r0,#0x1f
	128	orr r0,r0,#0xd3
	129	msr cpsr,r0
	130
	131	/*
	132	* we do sys-critical inits only at reboot,
	133	* not when booting from ram!
	134	*/
	135	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	136	bl cpu_init_crit
	137	#endif
	138
e05e5de7	139	bl _main
e30ceca2 HS	140
	141	/------------------------------------------------------------------------------/
	142
	143	/*
	144	* void relocate_code (addr_sp, gd, addr_moni)
	145	*
959eaa74	146	* This function relocates the monitor code.
e30ceca2 HS	147	*/
	148	.globl relocate_code
	149	relocate_code:
	150	mov r4, r0 /* save addr_sp */
	151	mov r5, r1 /* save addr of gd */
	152	mov r6, r2 /* save addr of destination */
e30ceca2	153
e30ceca2	154	adr r0, _start
a1a47d3c	155	cmp r0, r6
76abfa57	156	moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
e05e5de7	157	beq relocate_done /* skip relocation */
a78fb68f	158	mov r1, r6 /* r1 <- scratch for copy_loop */
3336ca60 AA	159	ldr r3, _bss_start_ofs
3336ca60 AA	160	add r2, r0, r3 /* r2 <- source end address */
e30ceca2	161
e30ceca2 HS	162	copy_loop:
e30ceca2 HS	163	ldmia r0!, {r9-r10} /* copy from source address [r0] */
a78fb68f	164	stmia r1!, {r9-r10} /* copy to target address [r1] */
da90d4ce AA	165	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	166	blo copy_loop
e30ceca2	167
401bb30b	168	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	169	/*
	170	* fix .rel.dyn relocations
	171	*/
	172	ldr r0, _TEXT_BASE /* r0 <- Text base */
a78fb68f	173	sub r9, r6, r0 /* r9 <- relocation offset */
3336ca60 AA	174	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	175	add r10, r10, r0 /* r10 <- sym table in FLASH */
	176	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	177	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	178	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	179	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
e30ceca2	180	fixloop:
3336ca60 AA	181	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	182	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	183	ldr r1, [r2, #4]
1f52d89f AB	184	and r7, r1, #0xff
1f52d89f AB	185	cmp r7, #23 /* relative fixup? */
3336ca60	186	beq fixrel
1f52d89f	187	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	188	beq fixabs
	189	/* ignore unknown type of fixup */
	190	b fixnext
	191	fixabs:
	192	/* absolute fix: set location to (offset) symbol value */
	193	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	194	add r1, r10, r1 /* r1 <- address of symbol in table */
	195	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	196	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	197	b fixnext
	198	fixrel:
	199	/* relative fix: increase location by offset */
	200	ldr r1, [r0]
	201	add r1, r1, r9
	202	fixnext:
	203	str r1, [r0]
	204	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
e30ceca2	205	cmp r2, r3
79e63139	206	blo fixloop
e30ceca2	207	#endif
e30ceca2	208
e05e5de7	209	relocate_done:
e30ceca2	210
e30ceca2 HS	211	mov pc, lr
e30ceca2 HS	212
3336ca60 AA	213	_rel_dyn_start_ofs:
	214	.word __rel_dyn_start - _start
	215	_rel_dyn_end_ofs:
	216	.word __rel_dyn_end - _start
	217	_dynsym_start_ofs:
	218	.word __dynsym_start - _start
e30ceca2	219
e05e5de7 AA	220	.globl c_runtime_cpu_setup
	221	c_runtime_cpu_setup:
	222
	223	mov pc, lr
	224
fe8c2806 WD	225	/*
	226	*************************************************************************
	227	*
	228	* CPU_init_critical registers
	229	*
	230	* setup important registers
	231	* setup memory timing
	232	*
	233	*************************************************************************
	234	*/
	235
	236
16263087	237	/* Interrupt-Controller base address */
fe8c2806 WD	238	IC_BASE: .word 0x90050000
	239	#define ICMR 0x04
	240
	241
	242	/* Reset-Controller */
	243	RST_BASE: .word 0x90030000
	244	#define RSRR 0x00
	245	#define RCSR 0x04
	246
	247
	248	/* PWR */
	249	PWR_BASE: .word 0x90020000
	250	#define PSPR 0x08
	251	#define PPCR 0x14
6d0f6bcf	252	cpuspeed: .word CONFIG_SYS_CPUSPEED
fe8c2806 WD	253
	254
	255	cpu_init_crit:
	256	/*
	257	* mask all IRQs
	258	*/
	259	ldr r0, IC_BASE
	260	mov r1, #0x00
	261	str r1, [r0, #ICMR]
	262
	263	/* set clock speed */
	264	ldr r0, PWR_BASE
	265	ldr r1, cpuspeed
	266	str r1, [r0, #PPCR]
	267
	268	/*
	269	* before relocating, we have to setup RAM timing
	270	* because memory timing is board-dependend, you will
400558b5	271	* find a lowlevel_init.S in your board directory.
fe8c2806 WD	272	*/
fe8c2806 WD	273	mov ip, lr
400558b5	274	bl lowlevel_init
fe8c2806 WD	275	mov lr, ip
	276
	277	/*
	278	* disable MMU stuff and enable I-cache
	279	*/
	280	mrc p15,0,r0,c1,c0
	281	bic r0, r0, #0x00002000 @ clear bit 13 (X)
	282	bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
	283	orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
	284	orr r0, r0, #0x00000002 @ set bit 2 (A) Align
	285	mcr p15,0,r0,c1,c0
	286
	287	/*
	288	* flush v4 I/D caches
	289	*/
	290	mov r0, #0
	291	mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
	292	mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
	293
	294	mov pc, lr
	295
	296
fe8c2806 WD	297	/*
	298	*************************************************************************
	299	*
	300	* Interrupt handling
	301	*
	302	*************************************************************************
	303	*/
	304
	305	@
	306	@ IRQ stack frame.
	307	@
	308	#define S_FRAME_SIZE 72
	309
	310	#define S_OLD_R0 68
	311	#define S_PSR 64
	312	#define S_PC 60
	313	#define S_LR 56
	314	#define S_SP 52
	315
	316	#define S_IP 48
	317	#define S_FP 44
	318	#define S_R10 40
	319	#define S_R9 36
	320	#define S_R8 32
	321	#define S_R7 28
	322	#define S_R6 24
	323	#define S_R5 20
	324	#define S_R4 16
	325	#define S_R3 12
	326	#define S_R2 8
	327	#define S_R1 4
	328	#define S_R0 0
	329
	330	#define MODE_SVC 0x13
	331	#define I_BIT 0x80
	332
	333	/*
	334	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	335	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	336	*/
	337
	338	.macro bad_save_user_regs
	339	sub sp, sp, #S_FRAME_SIZE
	340	stmia sp, {r0 - r12} @ Calling r0-r12
	341	add r8, sp, #S_PC
	342
e30ceca2	343	ldr r2, IRQ_STACK_START_IN
fe8c2806 WD	344	ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
	345	add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
	346
	347	add r5, sp, #S_SP
	348	mov r1, lr
	349	stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
	350	mov r0, sp
	351	.endm
	352
	353	.macro irq_save_user_regs
	354	sub sp, sp, #S_FRAME_SIZE
	355	stmia sp, {r0 - r12} @ Calling r0-r12
	356	add r8, sp, #S_PC
	357	stmdb r8, {sp, lr}^ @ Calling SP, LR
	358	str lr, [r8, #0] @ Save calling PC
	359	mrs r6, spsr
	360	str r6, [r8, #4] @ Save CPSR
	361	str r0, [r8, #8] @ Save OLD_R0
	362	mov r0, sp
	363	.endm
	364
	365	.macro irq_restore_user_regs
	366	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	367	mov r0, r0
	368	ldr lr, [sp, #S_PC] @ Get PC
	369	add sp, sp, #S_FRAME_SIZE
	370	subs pc, lr, #4 @ return & move spsr_svc into cpsr
	371	.endm
	372
	373	.macro get_bad_stack
e30ceca2	374	ldr r13, IRQ_STACK_START_IN @ setup our mode stack
fe8c2806 WD	375
	376	str lr, [r13] @ save caller lr / spsr
	377	mrs lr, spsr
	378	str lr, [r13, #4]
	379
	380	mov r13, #MODE_SVC @ prepare SVC-Mode
	381	msr spsr_c, r13
	382	mov lr, pc
	383	movs pc, lr
	384	.endm
	385
	386	.macro get_irq_stack @ setup IRQ stack
	387	ldr sp, IRQ_STACK_START
	388	.endm
	389
	390	.macro get_fiq_stack @ setup FIQ stack
	391	ldr sp, FIQ_STACK_START
	392	.endm
	393
	394	/*
	395	* exception handlers
	396	*/
	397	.align 5
	398	undefined_instruction:
	399	get_bad_stack
	400	bad_save_user_regs
53677ef1	401	bl do_undefined_instruction
fe8c2806 WD	402
	403	.align 5
	404	software_interrupt:
	405	get_bad_stack
	406	bad_save_user_regs
53677ef1	407	bl do_software_interrupt
fe8c2806 WD	408
	409	.align 5
	410	prefetch_abort:
	411	get_bad_stack
	412	bad_save_user_regs
53677ef1	413	bl do_prefetch_abort
fe8c2806 WD	414
	415	.align 5
	416	data_abort:
	417	get_bad_stack
	418	bad_save_user_regs
53677ef1	419	bl do_data_abort
fe8c2806 WD	420
	421	.align 5
	422	not_used:
	423	get_bad_stack
	424	bad_save_user_regs
53677ef1	425	bl do_not_used
fe8c2806 WD	426
	427	#ifdef CONFIG_USE_IRQ
	428
	429	.align 5
	430	irq:
	431	get_irq_stack
	432	irq_save_user_regs
53677ef1	433	bl do_irq
fe8c2806 WD	434	irq_restore_user_regs
	435
	436	.align 5
	437	fiq:
	438	get_fiq_stack
	439	/* someone ought to write a more effiction fiq_save_user_regs */
	440	irq_save_user_regs
53677ef1	441	bl do_fiq
fe8c2806 WD	442	irq_restore_user_regs
	443
	444	#else
	445
	446	.align 5
	447	irq:
	448	get_bad_stack
	449	bad_save_user_regs
53677ef1	450	bl do_irq
fe8c2806 WD	451
	452	.align 5
	453	fiq:
	454	get_bad_stack
	455	bad_save_user_regs
53677ef1	456	bl do_fiq
fe8c2806 WD	457
	458	#endif
	459
	460	.align 5
	461	.globl reset_cpu
	462	reset_cpu:
	463	ldr r0, RST_BASE
	464	mov r1, #0x0 @ set bit 3-0 ...
	465	str r1, [r0, #RCSR] @ ... to clear in RCSR
	466	mov r1, #0x1
	467	str r1, [r0, #RSRR] @ and perform reset
	468	b reset_cpu @ silly, but repeat endlessly