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6570438a YL |
1 | /* |
2 | * (C) Copyright 2010 - 2011 | |
3 | * NVIDIA Corporation <www.nvidia.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
6570438a YL |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/io.h> | |
6570438a YL |
10 | #include <asm/arch/clock.h> |
11 | #include <asm/arch/flow.h> | |
12 | #include <asm/arch/pinmux.h> | |
150c2493 TW |
13 | #include <asm/arch/tegra.h> |
14 | #include <asm/arch-tegra/ap.h> | |
15 | #include <asm/arch-tegra/clk_rst.h> | |
16 | #include <asm/arch-tegra/pmc.h> | |
17 | #include <asm/arch-tegra/warmboot.h> | |
6570438a YL |
18 | #include "warmboot_avp.h" |
19 | ||
20 | #define DEBUG_RESET_CORESIGHT | |
21 | ||
22 | void wb_start(void) | |
23 | { | |
24 | struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; | |
29f3e3f2 | 25 | struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
6570438a YL |
26 | struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; |
27 | struct clk_rst_ctlr *clkrst = | |
28 | (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; | |
29 | union osc_ctrl_reg osc_ctrl; | |
30 | union pllx_base_reg pllx_base; | |
31 | union pllx_misc_reg pllx_misc; | |
32 | union scratch3_reg scratch3; | |
33 | u32 reg; | |
34 | ||
35 | /* enable JTAG & TBE */ | |
36 | writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl); | |
37 | ||
38 | /* Are we running where we're supposed to be? */ | |
39 | asm volatile ( | |
40 | "adr %0, wb_start;" /* reg: wb_start address */ | |
41 | : "=r"(reg) /* output */ | |
42 | /* no input, no clobber list */ | |
43 | ); | |
44 | ||
150c2493 | 45 | if (reg != NV_WB_RUN_ADDRESS) |
6570438a YL |
46 | goto do_reset; |
47 | ||
48 | /* Are we running with AVP? */ | |
49 | if (readl(NV_PA_PG_UP_BASE + PG_UP_TAG_0) != PG_UP_TAG_AVP) | |
50 | goto do_reset; | |
51 | ||
52 | #ifdef DEBUG_RESET_CORESIGHT | |
53 | /* Assert CoreSight reset */ | |
54 | reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); | |
55 | reg |= SWR_CSITE_RST; | |
56 | writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); | |
57 | #endif | |
58 | ||
59 | /* TODO: Set the drive strength - maybe make this a board parameter? */ | |
60 | osc_ctrl.word = readl(&clkrst->crc_osc_ctrl); | |
61 | osc_ctrl.xofs = 4; | |
62 | osc_ctrl.xoe = 1; | |
63 | writel(osc_ctrl.word, &clkrst->crc_osc_ctrl); | |
64 | ||
65 | /* Power up the CPU complex if necessary */ | |
66 | if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) { | |
67 | reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START; | |
68 | writel(reg, &pmc->pmc_pwrgate_toggle); | |
69 | while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) | |
70 | ; | |
71 | } | |
72 | ||
73 | /* Remove the I/O clamps from the CPU power partition. */ | |
74 | reg = readl(&pmc->pmc_remove_clamping); | |
75 | reg |= CPU_CLMP; | |
76 | writel(reg, &pmc->pmc_remove_clamping); | |
77 | ||
78 | reg = EVENT_ZERO_VAL_20 | EVENT_MSEC | EVENT_MODE_STOP; | |
79 | writel(reg, &flow->halt_cop_events); | |
80 | ||
81 | /* Assert CPU complex reset */ | |
82 | reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]); | |
83 | reg |= CPU_RST; | |
84 | writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]); | |
85 | ||
86 | /* Hold both CPUs in reset */ | |
87 | reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_CPURESET1 | CPU_CMPLX_DERESET0 | | |
88 | CPU_CMPLX_DERESET1 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DBGRESET1; | |
89 | writel(reg, &clkrst->crc_cpu_cmplx_set); | |
90 | ||
91 | /* Halt CPU1 at the flow controller for uni-processor configurations */ | |
92 | writel(EVENT_MODE_STOP, &flow->halt_cpu1_events); | |
93 | ||
94 | /* | |
95 | * Set the CPU reset vector. SCRATCH41 contains the physical | |
96 | * address of the CPU-side restoration code. | |
97 | */ | |
98 | reg = readl(&pmc->pmc_scratch41); | |
99 | writel(reg, EXCEP_VECTOR_CPU_RESET_VECTOR); | |
100 | ||
101 | /* Select CPU complex clock source */ | |
102 | writel(CCLK_PLLP_BURST_POLICY, &clkrst->crc_cclk_brst_pol); | |
103 | ||
104 | /* Start the CPU0 clock and stop the CPU1 clock */ | |
105 | reg = CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 | CPU_CMPLX_CPU0_CLK_STP_RUN | | |
106 | CPU_CMPLX_CPU1_CLK_STP_STOP; | |
107 | writel(reg, &clkrst->crc_clk_cpu_cmplx); | |
108 | ||
109 | /* Enable the CPU complex clock */ | |
110 | reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]); | |
111 | reg |= CLK_ENB_CPU; | |
112 | writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]); | |
113 | ||
114 | /* Make sure the resets were held for at least 2 microseconds */ | |
115 | reg = readl(TIMER_USEC_CNTR); | |
116 | while (readl(TIMER_USEC_CNTR) <= (reg + 2)) | |
117 | ; | |
118 | ||
119 | #ifdef DEBUG_RESET_CORESIGHT | |
120 | /* | |
121 | * De-assert CoreSight reset. | |
122 | * NOTE: We're leaving the CoreSight clock on the oscillator for | |
123 | * now. It will be restored to its original clock source | |
124 | * when the CPU-side restoration code runs. | |
125 | */ | |
126 | reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); | |
127 | reg &= ~SWR_CSITE_RST; | |
128 | writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); | |
129 | #endif | |
130 | ||
131 | /* Unlock the CPU CoreSight interfaces */ | |
132 | reg = 0xC5ACCE55; | |
133 | writel(reg, CSITE_CPU_DBG0_LAR); | |
134 | writel(reg, CSITE_CPU_DBG1_LAR); | |
135 | ||
136 | /* | |
137 | * Sample the microsecond timestamp again. This is the time we must | |
138 | * use when returning from LP0 for PLL stabilization delays. | |
139 | */ | |
140 | reg = readl(TIMER_USEC_CNTR); | |
141 | writel(reg, &pmc->pmc_scratch1); | |
142 | ||
143 | pllx_base.word = 0; | |
144 | pllx_misc.word = 0; | |
145 | scratch3.word = readl(&pmc->pmc_scratch3); | |
146 | ||
147 | /* Get the OSC. For 19.2 MHz, use 19 to make the calculations easier */ | |
148 | reg = (readl(TIMER_USEC_CFG) & USEC_CFG_DIVISOR_MASK) + 1; | |
149 | ||
150 | /* | |
151 | * According to the TRM, for 19.2MHz OSC, the USEC_DIVISOR is 0x5f, and | |
152 | * USEC_DIVIDEND is 0x04. So, if USEC_DIVISOR > 26, OSC is 19.2 MHz. | |
153 | * | |
154 | * reg is used to calculate the pllx freq, which is used to determine if | |
155 | * to set dccon or not. | |
156 | */ | |
157 | if (reg > 26) | |
158 | reg = 19; | |
159 | ||
160 | /* PLLX_BASE.PLLX_DIVM */ | |
161 | if (scratch3.pllx_base_divm == reg) | |
162 | reg = 0; | |
163 | else | |
164 | reg = 1; | |
165 | ||
166 | /* PLLX_BASE.PLLX_DIVN */ | |
167 | pllx_base.divn = scratch3.pllx_base_divn; | |
168 | reg = scratch3.pllx_base_divn << reg; | |
169 | ||
170 | /* PLLX_BASE.PLLX_DIVP */ | |
171 | pllx_base.divp = scratch3.pllx_base_divp; | |
172 | reg = reg >> scratch3.pllx_base_divp; | |
173 | ||
174 | pllx_base.bypass = 1; | |
175 | ||
176 | /* PLLX_MISC_DCCON must be set for pllx frequency > 600 MHz. */ | |
177 | if (reg > 600) | |
178 | pllx_misc.dccon = 1; | |
179 | ||
180 | /* PLLX_MISC_LFCON */ | |
181 | pllx_misc.lfcon = scratch3.pllx_misc_lfcon; | |
182 | ||
183 | /* PLLX_MISC_CPCON */ | |
184 | pllx_misc.cpcon = scratch3.pllx_misc_cpcon; | |
185 | ||
186 | writel(pllx_misc.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_misc); | |
187 | writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); | |
188 | ||
189 | pllx_base.enable = 1; | |
190 | writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); | |
191 | pllx_base.bypass = 0; | |
192 | writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); | |
193 | ||
194 | writel(0, flow->halt_cpu_events); | |
195 | ||
196 | reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DERESET0; | |
197 | writel(reg, &clkrst->crc_cpu_cmplx_clr); | |
198 | ||
199 | reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE | | |
200 | PLLM_OUT1_RATIO_VAL_8; | |
65530a84 | 201 | writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]); |
6570438a YL |
202 | |
203 | reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 | | |
204 | SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 | | |
205 | SCLK_SYS_STATE_IDLE; | |
206 | writel(reg, &clkrst->crc_sclk_brst_pol); | |
207 | ||
208 | /* avp_resume: no return after the write */ | |
209 | reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]); | |
210 | reg &= ~CPU_RST; | |
211 | writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]); | |
212 | ||
213 | /* avp_halt: */ | |
214 | avp_halt: | |
215 | reg = EVENT_MODE_STOP | EVENT_JTAG; | |
216 | writel(reg, flow->halt_cop_events); | |
217 | goto avp_halt; | |
218 | ||
219 | do_reset: | |
220 | /* | |
221 | * Execution comes here if something goes wrong. The chip is reset and | |
222 | * a cold boot is performed. | |
223 | */ | |
224 | writel(SWR_TRIG_SYS_RST, &clkrst->crc_rst_dev[TEGRA_DEV_L]); | |
225 | goto do_reset; | |
226 | } | |
227 | ||
228 | /* | |
229 | * wb_end() is a dummy function, and must be directly following wb_start(), | |
230 | * and is used to calculate the size of wb_start(). | |
231 | */ | |
232 | void wb_end(void) | |
233 | { | |
234 | } |