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arm: mvebu: Add DM and OF_CONTROL support to SPL
[people/ms/u-boot.git] / arch / arm / dts / armada-370-xp.dtsi
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39a230aa
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1/*
2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
20 *
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 *
49 * This file contains the definitions that are common to the Armada
50 * 370 and Armada XP SoC.
51 */
52
53/include/ "skeleton64.dtsi"
54
55#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
56
57/ {
58 model = "Marvell Armada 370 and XP SoC";
59 compatible = "marvell,armada-370-xp";
60
61 aliases {
62 serial0 = &uart0;
63 serial1 = &uart1;
64 };
65
66 cpus {
67 #address-cells = <1>;
68 #size-cells = <0>;
69 cpu@0 {
70 compatible = "marvell,sheeva-v7";
71 device_type = "cpu";
72 reg = <0>;
73 };
74 };
75
76 pmu {
77 compatible = "arm,cortex-a9-pmu";
78 interrupts-extended = <&mpic 3>;
79 };
80
81 soc {
82 #address-cells = <2>;
83 #size-cells = <1>;
84 controller = <&mbusc>;
85 interrupt-parent = <&mpic>;
86 pcie-mem-aperture = <0xf8000000 0x7e00000>;
87 pcie-io-aperture = <0xffe00000 0x100000>;
88
89 devbus-bootcs {
90 compatible = "marvell,mvebu-devbus";
91 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
92 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
93 #address-cells = <1>;
94 #size-cells = <1>;
95 clocks = <&coreclk 0>;
96 status = "disabled";
97 };
98
99 devbus-cs0 {
100 compatible = "marvell,mvebu-devbus";
101 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
102 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
103 #address-cells = <1>;
104 #size-cells = <1>;
105 clocks = <&coreclk 0>;
106 status = "disabled";
107 };
108
109 devbus-cs1 {
110 compatible = "marvell,mvebu-devbus";
111 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
112 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
113 #address-cells = <1>;
114 #size-cells = <1>;
115 clocks = <&coreclk 0>;
116 status = "disabled";
117 };
118
119 devbus-cs2 {
120 compatible = "marvell,mvebu-devbus";
121 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
122 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
123 #address-cells = <1>;
124 #size-cells = <1>;
125 clocks = <&coreclk 0>;
126 status = "disabled";
127 };
128
129 devbus-cs3 {
130 compatible = "marvell,mvebu-devbus";
131 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
132 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
133 #address-cells = <1>;
134 #size-cells = <1>;
135 clocks = <&coreclk 0>;
136 status = "disabled";
137 };
138
139 internal-regs {
140 compatible = "simple-bus";
141 #address-cells = <1>;
142 #size-cells = <1>;
143 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
6451223a 144 u-boot,dm-pre-reloc;
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145
146 rtc@10300 {
147 compatible = "marvell,orion-rtc";
148 reg = <0x10300 0x20>;
149 interrupts = <50>;
150 };
151
152 spi0: spi@10600 {
153 reg = <0x10600 0x28>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156 cell-index = <0>;
157 interrupts = <30>;
158 clocks = <&coreclk 0>;
159 status = "disabled";
160 };
161
162 spi1: spi@10680 {
163 reg = <0x10680 0x28>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 cell-index = <1>;
167 interrupts = <92>;
168 clocks = <&coreclk 0>;
169 status = "disabled";
170 };
171
172 i2c0: i2c@11000 {
173 compatible = "marvell,mv64xxx-i2c";
174 #address-cells = <1>;
175 #size-cells = <0>;
176 interrupts = <31>;
177 timeout-ms = <1000>;
178 clocks = <&coreclk 0>;
179 status = "disabled";
180 };
181
182 i2c1: i2c@11100 {
183 compatible = "marvell,mv64xxx-i2c";
184 #address-cells = <1>;
185 #size-cells = <0>;
186 interrupts = <32>;
187 timeout-ms = <1000>;
188 clocks = <&coreclk 0>;
189 status = "disabled";
190 };
191
192 uart0: serial@12000 {
193 compatible = "snps,dw-apb-uart";
194 reg = <0x12000 0x100>;
195 reg-shift = <2>;
196 interrupts = <41>;
197 reg-io-width = <1>;
198 clocks = <&coreclk 0>;
199 status = "disabled";
200 };
201
202 uart1: serial@12100 {
203 compatible = "snps,dw-apb-uart";
204 reg = <0x12100 0x100>;
205 reg-shift = <2>;
206 interrupts = <42>;
207 reg-io-width = <1>;
208 clocks = <&coreclk 0>;
209 status = "disabled";
210 };
211
212 pinctrl: pin-ctrl@18000 {
213 reg = <0x18000 0x38>;
214 };
215
216 coredivclk: corediv-clock@18740 {
217 compatible = "marvell,armada-370-corediv-clock";
218 reg = <0x18740 0xc>;
219 #clock-cells = <1>;
220 clocks = <&mainpll>;
221 clock-output-names = "nand";
222 };
223
224 mbusc: mbus-controller@20000 {
225 compatible = "marvell,mbus-controller";
226 reg = <0x20000 0x100>, <0x20180 0x20>,
227 <0x20250 0x8>;
228 };
229
230 mpic: interrupt-controller@20a00 {
231 compatible = "marvell,mpic";
232 #interrupt-cells = <1>;
233 #size-cells = <1>;
234 interrupt-controller;
235 msi-controller;
236 };
237
238 coherency-fabric@20200 {
239 compatible = "marvell,coherency-fabric";
240 reg = <0x20200 0xb0>, <0x21010 0x1c>;
241 };
242
243 timer@20300 {
244 reg = <0x20300 0x30>, <0x21040 0x30>;
245 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
246 };
247
248 watchdog@20300 {
249 reg = <0x20300 0x34>, <0x20704 0x4>;
250 };
251
252 pmsu@22000 {
253 compatible = "marvell,armada-370-pmsu";
254 reg = <0x22000 0x1000>;
255 };
256
257 usb@50000 {
258 compatible = "marvell,orion-ehci";
259 reg = <0x50000 0x500>;
260 interrupts = <45>;
261 status = "disabled";
262 };
263
264 usb@51000 {
265 compatible = "marvell,orion-ehci";
266 reg = <0x51000 0x500>;
267 interrupts = <46>;
268 status = "disabled";
269 };
270
271 eth0: ethernet@70000 {
272 reg = <0x70000 0x4000>;
273 interrupts = <8>;
274 clocks = <&gateclk 4>;
275 status = "disabled";
276 };
277
278 mdio: mdio {
279 #address-cells = <1>;
280 #size-cells = <0>;
281 compatible = "marvell,orion-mdio";
282 reg = <0x72004 0x4>;
283 clocks = <&gateclk 4>;
284 };
285
286 eth1: ethernet@74000 {
287 reg = <0x74000 0x4000>;
288 interrupts = <10>;
289 clocks = <&gateclk 3>;
290 status = "disabled";
291 };
292
293 sata@a0000 {
294 compatible = "marvell,armada-370-sata";
295 reg = <0xa0000 0x5000>;
296 interrupts = <55>;
297 clocks = <&gateclk 15>, <&gateclk 30>;
298 clock-names = "0", "1";
299 status = "disabled";
300 };
301
302 nand@d0000 {
303 compatible = "marvell,armada370-nand";
304 reg = <0xd0000 0x54>;
305 #address-cells = <1>;
306 #size-cells = <1>;
307 interrupts = <113>;
308 clocks = <&coredivclk 0>;
309 status = "disabled";
310 };
311
312 mvsdio@d4000 {
313 compatible = "marvell,orion-sdio";
314 reg = <0xd4000 0x200>;
315 interrupts = <54>;
316 clocks = <&gateclk 17>;
317 bus-width = <4>;
318 cap-sdio-irq;
319 cap-sd-highspeed;
320 cap-mmc-highspeed;
321 status = "disabled";
322 };
323 };
324 };
325
326 clocks {
327 /* 2 GHz fixed main PLL */
328 mainpll: mainpll {
329 compatible = "fixed-clock";
330 #clock-cells = <0>;
331 clock-frequency = <2000000000>;
332 };
333 };
334 };