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bf2150b9 SR |
1 | /* |
2 | * Copyright (C) 2016 Marvell Technology Group Ltd. | |
3 | * | |
4 | * This file is dual-licensed: you can use it either under the terms | |
5 | * of the GPLv2 or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of the | |
12 | * License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * Or, alternatively, | |
20 | * | |
21 | * b) Permission is hereby granted, free of charge, to any person | |
22 | * obtaining a copy of this software and associated documentation | |
23 | * files (the "Software"), to deal in the Software without | |
24 | * restriction, including without limitation the rights to use, | |
25 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
26 | * sell copies of the Software, and to permit persons to whom the | |
27 | * Software is furnished to do so, subject to the following | |
28 | * conditions: | |
29 | * | |
30 | * The above copyright notice and this permission notice shall be | |
31 | * included in all copies or substantial portions of the Software. | |
32 | * | |
33 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
34 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
35 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
36 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
37 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
38 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
39 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
40 | * OTHER DEALINGS IN THE SOFTWARE. | |
41 | */ | |
42 | ||
43 | /* | |
44 | * Device Tree file for Marvell Armada CP110 Slave. | |
45 | */ | |
46 | ||
acbdc8e8 SR |
47 | #include <dt-bindings/comphy/comphy_data.h> |
48 | ||
bf2150b9 SR |
49 | / { |
50 | cp110-slave { | |
51 | #address-cells = <2>; | |
52 | #size-cells = <2>; | |
53 | compatible = "simple-bus"; | |
54 | interrupt-parent = <&gic>; | |
55 | ranges; | |
56 | ||
57 | config-space { | |
58 | #address-cells = <1>; | |
59 | #size-cells = <1>; | |
60 | compatible = "simple-bus"; | |
61 | interrupt-parent = <&gic>; | |
62 | ranges = <0x0 0x0 0xf4000000 0x2000000>; | |
63 | ||
a6555ebe TP |
64 | cps_ethernet: ethernet@0 { |
65 | compatible = "marvell,armada-7k-pp22"; | |
66 | reg = <0x0 0x100000>, <0x129000 0xb000>; | |
67 | clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; | |
68 | clock-names = "pp_clk", "gop_clk", "mg_clk"; | |
69 | status = "disabled"; | |
70 | dma-coherent; | |
71 | ||
72 | cps_eth0: eth0 { | |
73 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; | |
74 | port-id = <0>; | |
75 | gop-port-id = <0>; | |
76 | status = "disabled"; | |
77 | }; | |
78 | ||
79 | cps_eth1: eth1 { | |
80 | interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; | |
81 | port-id = <1>; | |
82 | gop-port-id = <2>; | |
83 | status = "disabled"; | |
84 | }; | |
85 | ||
86 | cps_eth2: eth2 { | |
87 | interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; | |
88 | port-id = <2>; | |
89 | gop-port-id = <3>; | |
90 | status = "disabled"; | |
91 | }; | |
92 | }; | |
93 | ||
94 | cps_mdio: mdio@12a200 { | |
95 | #address-cells = <1>; | |
96 | #size-cells = <0>; | |
97 | compatible = "marvell,orion-mdio"; | |
98 | reg = <0x12a200 0x10>; | |
99 | }; | |
100 | ||
bf2150b9 SR |
101 | cps_syscon0: system-controller@440000 { |
102 | compatible = "marvell,cp110-system-controller0", | |
103 | "syscon"; | |
104 | reg = <0x440000 0x1000>; | |
105 | #clock-cells = <2>; | |
106 | core-clock-output-names = | |
107 | "cps-apll", "cps-ppv2-core", "cps-eip", | |
108 | "cps-core", "cps-nand-core"; | |
109 | gate-clock-output-names = | |
110 | "cps-audio", "cps-communit", "cps-nand", | |
111 | "cps-ppv2", "cps-sdio", "cps-mg-domain", | |
112 | "cps-mg-core", "cps-xor1", "cps-xor0", | |
113 | "cps-gop-dp", "none", "cps-pcie_x10", | |
114 | "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", | |
115 | "cps-sata", "cps-sata-usb", "cps-main", | |
116 | "cps-sd-mmc", "none", "none", | |
117 | "cps-slow-io", "cps-usb3h0", "cps-usb3h1", | |
118 | "cps-usb3dev", "cps-eip150", "cps-eip197"; | |
119 | }; | |
120 | ||
f99386c5 KP |
121 | cps_pinctl: cps-pinctl@440000 { |
122 | compatible = "marvell,mvebu-pinctrl", | |
123 | "marvell,a80x0-cp1-pinctrl"; | |
124 | bank-name ="cp1-110"; | |
125 | reg = <0x440000 0x20>; | |
126 | pin-count = <63>; | |
127 | max-func = <0xf>; | |
128 | ||
129 | cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 { | |
130 | marvell,pins = < 0 1 2 3 4 5 6 7 | |
131 | 8 9 10 11 >; | |
132 | marvell,function = <3>; | |
133 | }; | |
134 | cps_spi1_pins: cps-spi-pins-1 { | |
135 | marvell,pins = < 13 14 15 16 >; | |
136 | marvell,function = <3>; | |
137 | }; | |
138 | }; | |
139 | ||
995a9f42 KP |
140 | cps_gpio0: gpio@440100 { |
141 | compatible = "marvell,orion-gpio"; | |
142 | reg = <0x440100 0x40>; | |
143 | ngpios = <32>; | |
144 | gpiobase = <20>; | |
145 | gpio-controller; | |
146 | #gpio-cells = <2>; | |
147 | }; | |
148 | ||
149 | cps_gpio1: gpio@440140 { | |
150 | compatible = "marvell,orion-gpio"; | |
151 | reg = <0x440140 0x40>; | |
152 | ngpios = <31>; | |
153 | gpiobase = <52>; | |
154 | gpio-controller; | |
155 | #gpio-cells = <2>; | |
156 | }; | |
157 | ||
bf2150b9 SR |
158 | cps_sata0: sata@540000 { |
159 | compatible = "marvell,armada-8k-ahci"; | |
160 | reg = <0x540000 0x30000>; | |
161 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
162 | clocks = <&cps_syscon0 1 15>; | |
163 | status = "disabled"; | |
164 | }; | |
165 | ||
166 | cps_usb3_0: usb3@500000 { | |
167 | compatible = "marvell,armada-8k-xhci", | |
168 | "generic-xhci"; | |
169 | reg = <0x500000 0x4000>; | |
170 | dma-coherent; | |
171 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; | |
172 | clocks = <&cps_syscon0 1 22>; | |
173 | status = "disabled"; | |
174 | }; | |
175 | ||
176 | cps_usb3_1: usb3@510000 { | |
177 | compatible = "marvell,armada-8k-xhci", | |
178 | "generic-xhci"; | |
179 | reg = <0x510000 0x4000>; | |
180 | dma-coherent; | |
181 | interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; | |
182 | clocks = <&cps_syscon0 1 23>; | |
183 | status = "disabled"; | |
184 | }; | |
185 | ||
186 | cps_xor0: xor@6a0000 { | |
187 | compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; | |
188 | reg = <0x6a0000 0x1000>, | |
189 | <0x6b0000 0x1000>; | |
190 | dma-coherent; | |
191 | msi-parent = <&gic_v2m0>; | |
192 | clocks = <&cps_syscon0 1 8>; | |
193 | }; | |
194 | ||
195 | cps_xor1: xor@6c0000 { | |
196 | compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; | |
197 | reg = <0x6c0000 0x1000>, | |
198 | <0x6d0000 0x1000>; | |
199 | dma-coherent; | |
200 | msi-parent = <&gic_v2m0>; | |
201 | clocks = <&cps_syscon0 1 7>; | |
202 | }; | |
203 | ||
204 | cps_spi0: spi@700600 { | |
205 | compatible = "marvell,armada-380-spi"; | |
206 | reg = <0x700600 0x50>; | |
207 | #address-cells = <0x1>; | |
208 | #size-cells = <0x0>; | |
209 | cell-index = <1>; | |
210 | clocks = <&cps_syscon0 0 3>; | |
211 | status = "disabled"; | |
212 | }; | |
213 | ||
214 | cps_spi1: spi@700680 { | |
215 | compatible = "marvell,armada-380-spi"; | |
216 | reg = <0x700680 0x50>; | |
217 | #address-cells = <1>; | |
218 | #size-cells = <0>; | |
219 | cell-index = <2>; | |
220 | clocks = <&cps_syscon0 1 21>; | |
221 | status = "disabled"; | |
222 | }; | |
223 | ||
224 | cps_i2c0: i2c@701000 { | |
225 | compatible = "marvell,mv78230-i2c"; | |
226 | reg = <0x701000 0x20>; | |
227 | #address-cells = <1>; | |
228 | #size-cells = <0>; | |
229 | interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; | |
230 | clocks = <&cps_syscon0 1 21>; | |
231 | status = "disabled"; | |
232 | }; | |
233 | ||
234 | cps_i2c1: i2c@701100 { | |
235 | compatible = "marvell,mv78230-i2c"; | |
236 | reg = <0x701100 0x20>; | |
237 | #address-cells = <1>; | |
238 | #size-cells = <0>; | |
239 | interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; | |
240 | clocks = <&cps_syscon0 1 21>; | |
241 | status = "disabled"; | |
242 | }; | |
acbdc8e8 SR |
243 | |
244 | cps_comphy: comphy@441000 { | |
245 | compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; | |
246 | reg = <0x441000 0x8>, | |
247 | <0x120000 0x8>; | |
248 | mux-bitcount = <4>; | |
249 | max-lanes = <6>; | |
250 | }; | |
251 | ||
252 | cps_utmi0: utmi@580000 { | |
253 | compatible = "marvell,mvebu-utmi-2.6.0"; | |
254 | reg = <0x580000 0x1000>, /* utmi-unit */ | |
255 | <0x440420 0x4>, /* usb-cfg */ | |
256 | <0x440440 0x4>; /* utmi-cfg */ | |
e89acc4b | 257 | utmi-port = <UTMI_PHY_TO_USB3_HOST0>; |
acbdc8e8 SR |
258 | status = "disabled"; |
259 | }; | |
bf2150b9 SR |
260 | }; |
261 | ||
262 | cps_pcie0: pcie@f4600000 { | |
263 | compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; | |
264 | reg = <0 0xf4600000 0 0x10000>, | |
265 | <0 0xfaf00000 0 0x80000>; | |
266 | reg-names = "ctrl", "config"; | |
267 | #address-cells = <3>; | |
268 | #size-cells = <2>; | |
269 | #interrupt-cells = <1>; | |
270 | device_type = "pci"; | |
271 | dma-coherent; | |
272 | msi-parent = <&gic_v2m0>; | |
273 | ||
274 | bus-range = <0 0xff>; | |
275 | ranges = | |
276 | /* downstream I/O */ | |
277 | <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000 | |
278 | /* non-prefetchable memory */ | |
279 | 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; | |
280 | interrupt-map-mask = <0 0 0 0>; | |
281 | interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; | |
282 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; | |
283 | num-lanes = <1>; | |
284 | clocks = <&cps_syscon0 1 13>; | |
285 | status = "disabled"; | |
286 | }; | |
287 | ||
288 | cps_pcie1: pcie@f4620000 { | |
289 | compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; | |
290 | reg = <0 0xf4620000 0 0x10000>, | |
291 | <0 0xfbf00000 0 0x80000>; | |
292 | reg-names = "ctrl", "config"; | |
293 | #address-cells = <3>; | |
294 | #size-cells = <2>; | |
295 | #interrupt-cells = <1>; | |
296 | device_type = "pci"; | |
297 | dma-coherent; | |
298 | msi-parent = <&gic_v2m0>; | |
299 | ||
300 | bus-range = <0 0xff>; | |
301 | ranges = | |
302 | /* downstream I/O */ | |
303 | <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000 | |
304 | /* non-prefetchable memory */ | |
305 | 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; | |
306 | interrupt-map-mask = <0 0 0 0>; | |
307 | interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; | |
308 | interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; | |
309 | ||
310 | num-lanes = <1>; | |
311 | clocks = <&cps_syscon0 1 11>; | |
312 | status = "disabled"; | |
313 | }; | |
314 | ||
315 | cps_pcie2: pcie@f4640000 { | |
316 | compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; | |
317 | reg = <0 0xf4640000 0 0x10000>, | |
318 | <0 0xfcf00000 0 0x80000>; | |
319 | reg-names = "ctrl", "config"; | |
320 | #address-cells = <3>; | |
321 | #size-cells = <2>; | |
322 | #interrupt-cells = <1>; | |
323 | device_type = "pci"; | |
324 | dma-coherent; | |
325 | msi-parent = <&gic_v2m0>; | |
326 | ||
327 | bus-range = <0 0xff>; | |
328 | ranges = | |
329 | /* downstream I/O */ | |
330 | <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000 | |
331 | /* non-prefetchable memory */ | |
332 | 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; | |
333 | interrupt-map-mask = <0 0 0 0>; | |
334 | interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; | |
335 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; | |
336 | ||
337 | num-lanes = <1>; | |
338 | clocks = <&cps_syscon0 1 12>; | |
339 | status = "disabled"; | |
340 | }; | |
341 | }; | |
342 | }; |