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cd339347 WY |
1 | /* |
2 | * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Atmel, | |
5 | * 2012 Hong Xu <hong.xu@atmel.com> | |
6 | * | |
7 | * Licensed under GPLv2 or later. | |
8 | */ | |
9 | ||
10 | #include "skeleton.dtsi" | |
11 | #include <dt-bindings/dma/at91.h> | |
12 | #include <dt-bindings/pinctrl/at91.h> | |
13 | #include <dt-bindings/interrupt-controller/irq.h> | |
14 | #include <dt-bindings/gpio/gpio.h> | |
15 | #include <dt-bindings/clock/at91.h> | |
16 | ||
17 | / { | |
18 | model = "Atmel AT91SAM9N12 SoC"; | |
19 | compatible = "atmel,at91sam9n12"; | |
20 | interrupt-parent = <&aic>; | |
21 | ||
22 | aliases { | |
23 | serial0 = &dbgu; | |
24 | serial1 = &usart0; | |
25 | serial2 = &usart1; | |
26 | serial3 = &usart2; | |
27 | serial4 = &usart3; | |
28 | gpio0 = &pioA; | |
29 | gpio1 = &pioB; | |
30 | gpio2 = &pioC; | |
31 | gpio3 = &pioD; | |
32 | tcb0 = &tcb0; | |
33 | tcb1 = &tcb1; | |
34 | i2c0 = &i2c0; | |
35 | i2c1 = &i2c1; | |
36 | ssc0 = &ssc0; | |
37 | pwm0 = &pwm0; | |
38 | spi0 = &spi0; | |
39 | }; | |
40 | cpus { | |
41 | #address-cells = <0>; | |
42 | #size-cells = <0>; | |
43 | ||
44 | cpu { | |
45 | compatible = "arm,arm926ej-s"; | |
46 | device_type = "cpu"; | |
47 | }; | |
48 | }; | |
49 | ||
50 | memory { | |
51 | reg = <0x20000000 0x10000000>; | |
52 | }; | |
53 | ||
54 | clocks { | |
55 | slow_xtal: slow_xtal { | |
56 | compatible = "fixed-clock"; | |
57 | #clock-cells = <0>; | |
58 | clock-frequency = <0>; | |
59 | }; | |
60 | ||
61 | main_xtal: main_xtal { | |
62 | compatible = "fixed-clock"; | |
63 | #clock-cells = <0>; | |
64 | clock-frequency = <0>; | |
65 | }; | |
66 | }; | |
67 | ||
68 | sram: sram@00300000 { | |
69 | compatible = "mmio-sram"; | |
70 | reg = <0x00300000 0x8000>; | |
71 | }; | |
72 | ||
73 | ahb { | |
74 | compatible = "simple-bus"; | |
75 | #address-cells = <1>; | |
76 | #size-cells = <1>; | |
77 | ranges; | |
78 | u-boot,dm-pre-reloc; | |
79 | ||
80 | apb { | |
81 | compatible = "simple-bus"; | |
82 | #address-cells = <1>; | |
83 | #size-cells = <1>; | |
84 | ranges; | |
85 | u-boot,dm-pre-reloc; | |
86 | ||
87 | aic: interrupt-controller@fffff000 { | |
88 | #interrupt-cells = <3>; | |
89 | compatible = "atmel,at91rm9200-aic"; | |
90 | interrupt-controller; | |
91 | reg = <0xfffff000 0x200>; | |
92 | atmel,external-irqs = <31>; | |
93 | }; | |
94 | ||
95 | ramc0: ramc@ffffe800 { | |
96 | compatible = "atmel,at91sam9g45-ddramc"; | |
97 | reg = <0xffffe800 0x200>; | |
98 | clocks = <&ddrck>; | |
99 | clock-names = "ddrck"; | |
100 | }; | |
101 | ||
102 | pmc: pmc@fffffc00 { | |
103 | compatible = "atmel,at91sam9n12-pmc", "syscon"; | |
104 | reg = <0xfffffc00 0x200>; | |
105 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
106 | interrupt-controller; | |
107 | #address-cells = <1>; | |
108 | #size-cells = <0>; | |
109 | #interrupt-cells = <1>; | |
110 | u-boot,dm-pre-reloc; | |
111 | ||
112 | main_rc_osc: main_rc_osc { | |
113 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; | |
114 | #clock-cells = <0>; | |
115 | interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; | |
116 | clock-frequency = <12000000>; | |
117 | clock-accuracy = <50000000>; | |
118 | }; | |
119 | ||
120 | main_osc: main_osc { | |
121 | compatible = "atmel,at91rm9200-clk-main-osc"; | |
122 | #clock-cells = <0>; | |
123 | interrupts-extended = <&pmc AT91_PMC_MOSCS>; | |
124 | clocks = <&main_xtal>; | |
125 | }; | |
126 | ||
127 | main: mainck { | |
128 | compatible = "atmel,at91sam9x5-clk-main"; | |
129 | #clock-cells = <0>; | |
130 | interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; | |
131 | clocks = <&main_rc_osc>, <&main_osc>; | |
132 | }; | |
133 | ||
134 | plla: pllack@0 { | |
135 | compatible = "atmel,at91rm9200-clk-pll"; | |
136 | #clock-cells = <0>; | |
137 | interrupts-extended = <&pmc AT91_PMC_LOCKA>; | |
138 | clocks = <&main>; | |
139 | reg = <0>; | |
140 | atmel,clk-input-range = <2000000 32000000>; | |
141 | #atmel,pll-clk-output-range-cells = <4>; | |
142 | atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, | |
143 | <695000000 750000000 1 0>, | |
144 | <645000000 700000000 2 0>, | |
145 | <595000000 650000000 3 0>, | |
146 | <545000000 600000000 0 1>, | |
147 | <495000000 555000000 1 1>, | |
148 | <445000000 500000000 2 1>, | |
149 | <400000000 450000000 3 1>; | |
150 | }; | |
151 | ||
152 | plladiv: plladivck { | |
153 | compatible = "atmel,at91sam9x5-clk-plldiv"; | |
154 | #clock-cells = <0>; | |
155 | clocks = <&plla>; | |
156 | }; | |
157 | ||
158 | pllb: pllbck@1 { | |
159 | compatible = "atmel,at91rm9200-clk-pll"; | |
160 | #clock-cells = <0>; | |
161 | interrupts-extended = <&pmc AT91_PMC_LOCKB>; | |
162 | clocks = <&main>; | |
163 | reg = <1>; | |
164 | atmel,clk-input-range = <2000000 32000000>; | |
165 | #atmel,pll-clk-output-range-cells = <3>; | |
166 | atmel,pll-clk-output-ranges = <30000000 100000000 0>; | |
167 | }; | |
168 | ||
169 | mck: masterck { | |
170 | compatible = "atmel,at91sam9x5-clk-master"; | |
171 | #clock-cells = <0>; | |
172 | interrupts-extended = <&pmc AT91_PMC_MCKRDY>; | |
173 | clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; | |
174 | atmel,clk-output-range = <0 133333333>; | |
175 | atmel,clk-divisors = <1 2 4 3>; | |
176 | atmel,master-clk-have-div3-pres; | |
177 | u-boot,dm-pre-reloc; | |
178 | }; | |
179 | ||
180 | usb: usbck { | |
181 | compatible = "atmel,at91sam9n12-clk-usb"; | |
182 | #clock-cells = <0>; | |
183 | clocks = <&pllb>; | |
184 | }; | |
185 | ||
186 | prog: progck { | |
187 | compatible = "atmel,at91sam9x5-clk-programmable"; | |
188 | #address-cells = <1>; | |
189 | #size-cells = <0>; | |
190 | interrupt-parent = <&pmc>; | |
191 | clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; | |
192 | ||
193 | prog0: prog@0 { | |
194 | #clock-cells = <0>; | |
195 | reg = <0>; | |
196 | interrupts = <AT91_PMC_PCKRDY(0)>; | |
197 | }; | |
198 | ||
199 | prog1: prog@1 { | |
200 | #clock-cells = <0>; | |
201 | reg = <1>; | |
202 | interrupts = <AT91_PMC_PCKRDY(1)>; | |
203 | }; | |
204 | }; | |
205 | ||
206 | systemck { | |
207 | compatible = "atmel,at91rm9200-clk-system"; | |
208 | #address-cells = <1>; | |
209 | #size-cells = <0>; | |
210 | ||
211 | ddrck: ddrck@2 { | |
212 | #clock-cells = <0>; | |
213 | reg = <2>; | |
214 | clocks = <&mck>; | |
215 | }; | |
216 | ||
217 | lcdck: lcdck@3 { | |
218 | #clock-cells = <0>; | |
219 | reg = <3>; | |
220 | clocks = <&mck>; | |
221 | }; | |
222 | ||
223 | uhpck: uhpck@6 { | |
224 | #clock-cells = <0>; | |
225 | reg = <6>; | |
226 | clocks = <&usb>; | |
227 | }; | |
228 | ||
229 | udpck: udpck@7 { | |
230 | #clock-cells = <0>; | |
231 | reg = <7>; | |
232 | clocks = <&usb>; | |
233 | }; | |
234 | ||
235 | pck0: pck0@8 { | |
236 | #clock-cells = <0>; | |
237 | reg = <8>; | |
238 | clocks = <&prog0>; | |
239 | }; | |
240 | ||
241 | pck1: pck1@9 { | |
242 | #clock-cells = <0>; | |
243 | reg = <9>; | |
244 | clocks = <&prog1>; | |
245 | }; | |
246 | }; | |
247 | ||
248 | periphck { | |
249 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
250 | #address-cells = <1>; | |
251 | #size-cells = <0>; | |
252 | clocks = <&mck>; | |
253 | u-boot,dm-pre-reloc; | |
254 | ||
255 | pioAB_clk: pioAB_clk@2 { | |
256 | #clock-cells = <0>; | |
257 | reg = <2>; | |
258 | u-boot,dm-pre-reloc; | |
259 | }; | |
260 | ||
261 | pioCD_clk: pioCD_clk@3 { | |
262 | #clock-cells = <0>; | |
263 | reg = <3>; | |
264 | u-boot,dm-pre-reloc; | |
265 | }; | |
266 | ||
267 | fuse_clk: fuse_clk@4 { | |
268 | #clock-cells = <0>; | |
269 | reg = <4>; | |
270 | }; | |
271 | ||
272 | usart0_clk: usart0_clk@5 { | |
273 | #clock-cells = <0>; | |
274 | reg = <5>; | |
275 | }; | |
276 | ||
277 | usart1_clk: usart1_clk@6 { | |
278 | #clock-cells = <0>; | |
279 | reg = <6>; | |
280 | }; | |
281 | ||
282 | usart2_clk: usart2_clk@7 { | |
283 | #clock-cells = <0>; | |
284 | reg = <7>; | |
285 | }; | |
286 | ||
287 | usart3_clk: usart3_clk@8 { | |
288 | #clock-cells = <0>; | |
289 | reg = <8>; | |
290 | }; | |
291 | ||
292 | twi0_clk: twi0_clk@9 { | |
293 | reg = <9>; | |
294 | #clock-cells = <0>; | |
295 | }; | |
296 | ||
297 | twi1_clk: twi1_clk@10 { | |
298 | #clock-cells = <0>; | |
299 | reg = <10>; | |
300 | }; | |
301 | ||
302 | mci0_clk: mci0_clk@12 { | |
303 | #clock-cells = <0>; | |
304 | reg = <12>; | |
305 | }; | |
306 | ||
307 | spi0_clk: spi0_clk@13 { | |
308 | #clock-cells = <0>; | |
309 | reg = <13>; | |
310 | }; | |
311 | ||
312 | spi1_clk: spi1_clk@14 { | |
313 | #clock-cells = <0>; | |
314 | reg = <14>; | |
315 | }; | |
316 | ||
317 | uart0_clk: uart0_clk@15 { | |
318 | #clock-cells = <0>; | |
319 | reg = <15>; | |
320 | }; | |
321 | ||
322 | uart1_clk: uart1_clk@16 { | |
323 | #clock-cells = <0>; | |
324 | reg = <16>; | |
325 | }; | |
326 | ||
327 | tcb_clk: tcb_clk@17 { | |
328 | #clock-cells = <0>; | |
329 | reg = <17>; | |
330 | }; | |
331 | ||
332 | pwm_clk: pwm_clk@18 { | |
333 | #clock-cells = <0>; | |
334 | reg = <18>; | |
335 | }; | |
336 | ||
337 | adc_clk: adc_clk@19 { | |
338 | #clock-cells = <0>; | |
339 | reg = <19>; | |
340 | }; | |
341 | ||
342 | dma0_clk: dma0_clk@20 { | |
343 | #clock-cells = <0>; | |
344 | reg = <20>; | |
345 | }; | |
346 | ||
347 | uhphs_clk: uhphs_clk@22 { | |
348 | #clock-cells = <0>; | |
349 | reg = <22>; | |
350 | }; | |
351 | ||
352 | udphs_clk: udphs_clk@23 { | |
353 | #clock-cells = <0>; | |
354 | reg = <23>; | |
355 | }; | |
356 | ||
357 | lcdc_clk: lcdc_clk@25 { | |
358 | #clock-cells = <0>; | |
359 | reg = <25>; | |
360 | }; | |
361 | ||
362 | sha_clk: sha_clk@27 { | |
363 | #clock-cells = <0>; | |
364 | reg = <27>; | |
365 | }; | |
366 | ||
367 | ssc0_clk: ssc0_clk@28 { | |
368 | #clock-cells = <0>; | |
369 | reg = <28>; | |
370 | }; | |
371 | ||
372 | aes_clk: aes_clk@29 { | |
373 | #clock-cells = <0>; | |
374 | reg = <29>; | |
375 | }; | |
376 | ||
377 | trng_clk: trng_clk@30 { | |
378 | #clock-cells = <0>; | |
379 | reg = <30>; | |
380 | }; | |
381 | }; | |
382 | }; | |
383 | ||
384 | rstc@fffffe00 { | |
385 | compatible = "atmel,at91sam9g45-rstc"; | |
386 | reg = <0xfffffe00 0x10>; | |
387 | clocks = <&clk32k>; | |
388 | }; | |
389 | ||
390 | pit: timer@fffffe30 { | |
391 | compatible = "atmel,at91sam9260-pit"; | |
392 | reg = <0xfffffe30 0xf>; | |
393 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
394 | clocks = <&mck>; | |
395 | }; | |
396 | ||
397 | shdwc@fffffe10 { | |
398 | compatible = "atmel,at91sam9x5-shdwc"; | |
399 | reg = <0xfffffe10 0x10>; | |
400 | clocks = <&clk32k>; | |
401 | }; | |
402 | ||
403 | sckc@fffffe50 { | |
404 | compatible = "atmel,at91sam9x5-sckc"; | |
405 | reg = <0xfffffe50 0x4>; | |
406 | ||
407 | slow_osc: slow_osc { | |
408 | compatible = "atmel,at91sam9x5-clk-slow-osc"; | |
409 | #clock-cells = <0>; | |
410 | clocks = <&slow_xtal>; | |
411 | }; | |
412 | ||
413 | slow_rc_osc: slow_rc_osc { | |
414 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; | |
415 | #clock-cells = <0>; | |
416 | clock-frequency = <32768>; | |
417 | clock-accuracy = <50000000>; | |
418 | }; | |
419 | ||
420 | clk32k: slck { | |
421 | compatible = "atmel,at91sam9x5-clk-slow"; | |
422 | #clock-cells = <0>; | |
423 | clocks = <&slow_rc_osc>, <&slow_osc>; | |
424 | }; | |
425 | }; | |
426 | ||
427 | mmc0: mmc@f0008000 { | |
428 | compatible = "atmel,hsmci"; | |
429 | reg = <0xf0008000 0x600>; | |
430 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; | |
431 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; | |
432 | dma-names = "rxtx"; | |
433 | clocks = <&mci0_clk>; | |
434 | clock-names = "mci_clk"; | |
435 | #address-cells = <1>; | |
436 | #size-cells = <0>; | |
437 | status = "disabled"; | |
438 | }; | |
439 | ||
440 | tcb0: timer@f8008000 { | |
441 | compatible = "atmel,at91sam9x5-tcb"; | |
442 | reg = <0xf8008000 0x100>; | |
443 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; | |
444 | clocks = <&tcb_clk>, <&clk32k>; | |
445 | clock-names = "t0_clk", "slow_clk"; | |
446 | }; | |
447 | ||
448 | tcb1: timer@f800c000 { | |
449 | compatible = "atmel,at91sam9x5-tcb"; | |
450 | reg = <0xf800c000 0x100>; | |
451 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; | |
452 | clocks = <&tcb_clk>, <&clk32k>; | |
453 | clock-names = "t0_clk", "slow_clk"; | |
454 | }; | |
455 | ||
456 | hlcdc: hlcdc@f8038000 { | |
457 | compatible = "atmel,at91sam9n12-hlcdc"; | |
458 | reg = <0xf8038000 0x2000>; | |
459 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; | |
460 | clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; | |
461 | clock-names = "periph_clk", "sys_clk", "slow_clk"; | |
462 | status = "disabled"; | |
463 | ||
464 | hlcdc-display-controller { | |
465 | compatible = "atmel,hlcdc-display-controller"; | |
466 | #address-cells = <1>; | |
467 | #size-cells = <0>; | |
468 | ||
469 | port@0 { | |
470 | #address-cells = <1>; | |
471 | #size-cells = <0>; | |
472 | reg = <0>; | |
473 | }; | |
474 | }; | |
475 | ||
476 | hlcdc_pwm: hlcdc-pwm { | |
477 | compatible = "atmel,hlcdc-pwm"; | |
478 | pinctrl-names = "default"; | |
479 | pinctrl-0 = <&pinctrl_lcd_pwm>; | |
480 | #pwm-cells = <3>; | |
481 | }; | |
482 | }; | |
483 | ||
484 | dma: dma-controller@ffffec00 { | |
485 | compatible = "atmel,at91sam9g45-dma"; | |
486 | reg = <0xffffec00 0x200>; | |
487 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; | |
488 | #dma-cells = <2>; | |
489 | clocks = <&dma0_clk>; | |
490 | clock-names = "dma_clk"; | |
491 | }; | |
492 | ||
493 | pinctrl@fffff400 { | |
494 | #address-cells = <1>; | |
495 | #size-cells = <1>; | |
496 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; | |
497 | ranges = <0xfffff400 0xfffff400 0x800>; | |
498 | reg = <0xfffff400 0x200 | |
499 | 0xfffff600 0x200 | |
500 | 0xfffff800 0x200 | |
501 | 0xfffffa00 0x200 | |
502 | >; | |
503 | ||
504 | atmel,mux-mask = < | |
505 | /* A B C */ | |
506 | 0xffffffff 0xffe07983 0x00000000 /* pioA */ | |
507 | 0x00040000 0x00047e0f 0x00000000 /* pioB */ | |
508 | 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ | |
509 | 0x003fffff 0x003f8000 0x00000000 /* pioD */ | |
510 | >; | |
511 | u-boot,dm-pre-reloc; | |
512 | ||
513 | /* shared pinctrl settings */ | |
514 | dbgu { | |
515 | u-boot,dm-pre-reloc; | |
516 | pinctrl_dbgu: dbgu-0 { | |
517 | atmel,pins = | |
518 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP | |
519 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
520 | }; | |
521 | }; | |
522 | ||
523 | lcd { | |
524 | pinctrl_lcd_base: lcd-base-0 { | |
525 | atmel,pins = | |
526 | <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ | |
527 | AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ | |
528 | AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */ | |
529 | AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ | |
530 | AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ | |
531 | }; | |
532 | ||
533 | pinctrl_lcd_pwm: lcd-pwm-0 { | |
534 | atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ | |
535 | }; | |
536 | ||
537 | pinctrl_lcd_rgb888: lcd-rgb-3 { | |
538 | atmel,pins = | |
539 | <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ | |
540 | AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ | |
541 | AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ | |
542 | AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ | |
543 | AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ | |
544 | AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ | |
545 | AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ | |
546 | AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ | |
547 | AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ | |
548 | AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ | |
549 | AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ | |
550 | AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ | |
551 | AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ | |
552 | AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ | |
553 | AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ | |
554 | AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ | |
555 | AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ | |
556 | AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ | |
557 | AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ | |
558 | AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ | |
559 | AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ | |
560 | AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ | |
561 | AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ | |
562 | AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ | |
563 | }; | |
564 | }; | |
565 | ||
566 | usart0 { | |
567 | pinctrl_usart0: usart0-0 { | |
568 | atmel,pins = | |
569 | <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ | |
570 | AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */ | |
571 | }; | |
572 | ||
573 | pinctrl_usart0_rts: usart0_rts-0 { | |
574 | atmel,pins = | |
575 | <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ | |
576 | }; | |
577 | ||
578 | pinctrl_usart0_cts: usart0_cts-0 { | |
579 | atmel,pins = | |
580 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ | |
581 | }; | |
582 | }; | |
583 | ||
584 | usart1 { | |
585 | pinctrl_usart1: usart1-0 { | |
586 | atmel,pins = | |
587 | <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ | |
588 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ | |
589 | }; | |
590 | }; | |
591 | ||
592 | usart2 { | |
593 | pinctrl_usart2: usart2-0 { | |
594 | atmel,pins = | |
595 | <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ | |
596 | AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */ | |
597 | }; | |
598 | ||
599 | pinctrl_usart2_rts: usart2_rts-0 { | |
600 | atmel,pins = | |
601 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ | |
602 | }; | |
603 | ||
604 | pinctrl_usart2_cts: usart2_cts-0 { | |
605 | atmel,pins = | |
606 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ | |
607 | }; | |
608 | }; | |
609 | ||
610 | usart3 { | |
611 | pinctrl_usart3: usart3-0 { | |
612 | atmel,pins = | |
613 | <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */ | |
614 | AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */ | |
615 | }; | |
616 | ||
617 | pinctrl_usart3_rts: usart3_rts-0 { | |
618 | atmel,pins = | |
619 | <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ | |
620 | }; | |
621 | ||
622 | pinctrl_usart3_cts: usart3_cts-0 { | |
623 | atmel,pins = | |
624 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ | |
625 | }; | |
626 | }; | |
627 | ||
628 | uart0 { | |
629 | pinctrl_uart0: uart0-0 { | |
630 | atmel,pins = | |
631 | <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */ | |
632 | AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */ | |
633 | }; | |
634 | }; | |
635 | ||
636 | uart1 { | |
637 | pinctrl_uart1: uart1-0 { | |
638 | atmel,pins = | |
639 | <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */ | |
640 | AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */ | |
641 | }; | |
642 | }; | |
643 | ||
644 | nand { | |
645 | pinctrl_nand: nand-0 { | |
646 | atmel,pins = | |
647 | <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/ | |
648 | AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */ | |
649 | }; | |
650 | }; | |
651 | ||
652 | mmc0 { | |
653 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | |
654 | atmel,pins = | |
655 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ | |
656 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ | |
657 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ | |
658 | }; | |
659 | ||
660 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | |
661 | atmel,pins = | |
662 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ | |
663 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ | |
664 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ | |
665 | }; | |
666 | ||
667 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { | |
668 | atmel,pins = | |
669 | <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ | |
670 | AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ | |
671 | AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */ | |
672 | AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */ | |
673 | }; | |
674 | }; | |
675 | ||
676 | ssc0 { | |
677 | pinctrl_ssc0_tx: ssc0_tx-0 { | |
678 | atmel,pins = | |
679 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ | |
680 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ | |
681 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ | |
682 | }; | |
683 | ||
684 | pinctrl_ssc0_rx: ssc0_rx-0 { | |
685 | atmel,pins = | |
686 | <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ | |
687 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ | |
688 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ | |
689 | }; | |
690 | }; | |
691 | ||
692 | spi0 { | |
693 | pinctrl_spi0: spi0-0 { | |
694 | atmel,pins = | |
695 | <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ | |
696 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ | |
697 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ | |
698 | }; | |
699 | }; | |
700 | ||
701 | spi1 { | |
702 | pinctrl_spi1: spi1-0 { | |
703 | atmel,pins = | |
704 | <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ | |
705 | AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ | |
706 | AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ | |
707 | }; | |
708 | }; | |
709 | ||
710 | i2c0 { | |
711 | pinctrl_i2c0: i2c0-0 { | |
712 | atmel,pins = | |
713 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE | |
714 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
715 | }; | |
716 | }; | |
717 | ||
718 | i2c1 { | |
719 | pinctrl_i2c1: i2c1-0 { | |
720 | atmel,pins = | |
721 | <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE | |
722 | AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
723 | }; | |
724 | }; | |
725 | ||
726 | tcb0 { | |
727 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | |
728 | atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
729 | }; | |
730 | ||
731 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { | |
732 | atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
733 | }; | |
734 | ||
735 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { | |
736 | atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
737 | }; | |
738 | ||
739 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { | |
740 | atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
741 | }; | |
742 | ||
743 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { | |
744 | atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
745 | }; | |
746 | ||
747 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { | |
748 | atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
749 | }; | |
750 | ||
751 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { | |
752 | atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
753 | }; | |
754 | ||
755 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { | |
756 | atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
757 | }; | |
758 | ||
759 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { | |
760 | atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
761 | }; | |
762 | }; | |
763 | ||
764 | tcb1 { | |
765 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { | |
766 | atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
767 | }; | |
768 | ||
769 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { | |
770 | atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
771 | }; | |
772 | ||
773 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { | |
774 | atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
775 | }; | |
776 | ||
777 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { | |
778 | atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
779 | }; | |
780 | ||
781 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { | |
782 | atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
783 | }; | |
784 | ||
785 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { | |
786 | atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
787 | }; | |
788 | ||
789 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { | |
790 | atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
791 | }; | |
792 | ||
793 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { | |
794 | atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
795 | }; | |
796 | ||
797 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { | |
798 | atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; | |
799 | }; | |
800 | }; | |
801 | }; | |
802 | ||
803 | pioA: gpio@fffff400 { | |
804 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
805 | reg = <0xfffff400 0x200>; | |
806 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; | |
807 | #gpio-cells = <2>; | |
808 | gpio-controller; | |
809 | interrupt-controller; | |
810 | #interrupt-cells = <2>; | |
811 | clocks = <&pioAB_clk>; | |
812 | u-boot,dm-pre-reloc; | |
813 | }; | |
814 | ||
815 | pioB: gpio@fffff600 { | |
816 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
817 | reg = <0xfffff600 0x200>; | |
818 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; | |
819 | #gpio-cells = <2>; | |
820 | gpio-controller; | |
821 | interrupt-controller; | |
822 | #interrupt-cells = <2>; | |
823 | clocks = <&pioAB_clk>; | |
824 | u-boot,dm-pre-reloc; | |
825 | }; | |
826 | ||
827 | pioC: gpio@fffff800 { | |
828 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
829 | reg = <0xfffff800 0x200>; | |
830 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; | |
831 | #gpio-cells = <2>; | |
832 | gpio-controller; | |
833 | interrupt-controller; | |
834 | #interrupt-cells = <2>; | |
835 | clocks = <&pioCD_clk>; | |
836 | u-boot,dm-pre-reloc; | |
837 | }; | |
838 | ||
839 | pioD: gpio@fffffa00 { | |
840 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
841 | reg = <0xfffffa00 0x200>; | |
842 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; | |
843 | #gpio-cells = <2>; | |
844 | gpio-controller; | |
845 | interrupt-controller; | |
846 | #interrupt-cells = <2>; | |
847 | clocks = <&pioCD_clk>; | |
848 | u-boot,dm-pre-reloc; | |
849 | }; | |
850 | ||
851 | dbgu: serial@fffff200 { | |
852 | compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; | |
853 | reg = <0xfffff200 0x200>; | |
854 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
855 | pinctrl-names = "default"; | |
856 | pinctrl-0 = <&pinctrl_dbgu>; | |
857 | clocks = <&mck>; | |
858 | clock-names = "usart"; | |
859 | status = "disabled"; | |
860 | }; | |
861 | ||
862 | ssc0: ssc@f0010000 { | |
863 | compatible = "atmel,at91sam9g45-ssc"; | |
864 | reg = <0xf0010000 0x4000>; | |
865 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; | |
866 | dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, | |
867 | <&dma 0 AT91_DMA_CFG_PER_ID(22)>; | |
868 | dma-names = "tx", "rx"; | |
869 | pinctrl-names = "default"; | |
870 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
871 | clocks = <&ssc0_clk>; | |
872 | clock-names = "pclk"; | |
873 | status = "disabled"; | |
874 | }; | |
875 | ||
876 | usart0: serial@f801c000 { | |
877 | compatible = "atmel,at91sam9260-usart"; | |
878 | reg = <0xf801c000 0x4000>; | |
879 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; | |
880 | pinctrl-names = "default"; | |
881 | pinctrl-0 = <&pinctrl_usart0>; | |
882 | clocks = <&usart0_clk>; | |
883 | clock-names = "usart"; | |
884 | status = "disabled"; | |
885 | }; | |
886 | ||
887 | usart1: serial@f8020000 { | |
888 | compatible = "atmel,at91sam9260-usart"; | |
889 | reg = <0xf8020000 0x4000>; | |
890 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; | |
891 | pinctrl-names = "default"; | |
892 | pinctrl-0 = <&pinctrl_usart1>; | |
893 | clocks = <&usart1_clk>; | |
894 | clock-names = "usart"; | |
895 | status = "disabled"; | |
896 | }; | |
897 | ||
898 | usart2: serial@f8024000 { | |
899 | compatible = "atmel,at91sam9260-usart"; | |
900 | reg = <0xf8024000 0x4000>; | |
901 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; | |
902 | pinctrl-names = "default"; | |
903 | pinctrl-0 = <&pinctrl_usart2>; | |
904 | clocks = <&usart2_clk>; | |
905 | clock-names = "usart"; | |
906 | status = "disabled"; | |
907 | }; | |
908 | ||
909 | usart3: serial@f8028000 { | |
910 | compatible = "atmel,at91sam9260-usart"; | |
911 | reg = <0xf8028000 0x4000>; | |
912 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; | |
913 | pinctrl-names = "default"; | |
914 | pinctrl-0 = <&pinctrl_usart3>; | |
915 | clocks = <&usart3_clk>; | |
916 | clock-names = "usart"; | |
917 | status = "disabled"; | |
918 | }; | |
919 | ||
920 | i2c0: i2c@f8010000 { | |
921 | compatible = "atmel,at91sam9x5-i2c"; | |
922 | reg = <0xf8010000 0x100>; | |
923 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; | |
924 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, | |
925 | <&dma 1 AT91_DMA_CFG_PER_ID(14)>; | |
926 | dma-names = "tx", "rx"; | |
927 | #address-cells = <1>; | |
928 | #size-cells = <0>; | |
929 | pinctrl-names = "default"; | |
930 | pinctrl-0 = <&pinctrl_i2c0>; | |
931 | clocks = <&twi0_clk>; | |
932 | status = "disabled"; | |
933 | }; | |
934 | ||
935 | i2c1: i2c@f8014000 { | |
936 | compatible = "atmel,at91sam9x5-i2c"; | |
937 | reg = <0xf8014000 0x100>; | |
938 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; | |
939 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, | |
940 | <&dma 1 AT91_DMA_CFG_PER_ID(16)>; | |
941 | dma-names = "tx", "rx"; | |
942 | #address-cells = <1>; | |
943 | #size-cells = <0>; | |
944 | pinctrl-names = "default"; | |
945 | pinctrl-0 = <&pinctrl_i2c1>; | |
946 | clocks = <&twi1_clk>; | |
947 | status = "disabled"; | |
948 | }; | |
949 | ||
950 | spi0: spi@f0000000 { | |
951 | #address-cells = <1>; | |
952 | #size-cells = <0>; | |
953 | compatible = "atmel,at91rm9200-spi"; | |
954 | reg = <0xf0000000 0x100>; | |
955 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; | |
956 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, | |
957 | <&dma 1 AT91_DMA_CFG_PER_ID(2)>; | |
958 | dma-names = "tx", "rx"; | |
959 | pinctrl-names = "default"; | |
960 | pinctrl-0 = <&pinctrl_spi0>; | |
961 | clocks = <&spi0_clk>; | |
962 | clock-names = "spi_clk"; | |
963 | status = "disabled"; | |
964 | }; | |
965 | ||
966 | spi1: spi@f0004000 { | |
967 | #address-cells = <1>; | |
968 | #size-cells = <0>; | |
969 | compatible = "atmel,at91rm9200-spi"; | |
970 | reg = <0xf0004000 0x100>; | |
971 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; | |
972 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, | |
973 | <&dma 1 AT91_DMA_CFG_PER_ID(4)>; | |
974 | dma-names = "tx", "rx"; | |
975 | pinctrl-names = "default"; | |
976 | pinctrl-0 = <&pinctrl_spi1>; | |
977 | clocks = <&spi1_clk>; | |
978 | clock-names = "spi_clk"; | |
979 | status = "disabled"; | |
980 | }; | |
981 | ||
982 | watchdog@fffffe40 { | |
983 | compatible = "atmel,at91sam9260-wdt"; | |
984 | reg = <0xfffffe40 0x10>; | |
985 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
986 | clocks = <&clk32k>; | |
987 | atmel,watchdog-type = "hardware"; | |
988 | atmel,reset-type = "all"; | |
989 | atmel,dbg-halt; | |
990 | status = "disabled"; | |
991 | }; | |
992 | ||
993 | rtc@fffffeb0 { | |
994 | compatible = "atmel,at91rm9200-rtc"; | |
995 | reg = <0xfffffeb0 0x40>; | |
996 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
997 | clocks = <&clk32k>; | |
998 | status = "disabled"; | |
999 | }; | |
1000 | ||
1001 | pwm0: pwm@f8034000 { | |
1002 | compatible = "atmel,at91sam9rl-pwm"; | |
1003 | reg = <0xf8034000 0x300>; | |
1004 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; | |
1005 | #pwm-cells = <3>; | |
1006 | clocks = <&pwm_clk>; | |
1007 | status = "disabled"; | |
1008 | }; | |
1009 | ||
1010 | usb1: gadget@f803c000 { | |
1011 | compatible = "atmel,at91sam9260-udc"; | |
1012 | reg = <0xf803c000 0x4000>; | |
1013 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; | |
1014 | clocks = <&udphs_clk>, <&udpck>; | |
1015 | clock-names = "pclk", "hclk"; | |
1016 | status = "disabled"; | |
1017 | }; | |
1018 | }; | |
1019 | ||
1020 | nand0: nand@40000000 { | |
1021 | compatible = "atmel,at91rm9200-nand"; | |
1022 | #address-cells = <1>; | |
1023 | #size-cells = <1>; | |
1024 | reg = < 0x40000000 0x10000000 | |
1025 | 0xffffe000 0x00000600 | |
1026 | 0xffffe600 0x00000200 | |
1027 | 0x00108000 0x00018000 | |
1028 | >; | |
1029 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; | |
1030 | atmel,nand-addr-offset = <21>; | |
1031 | atmel,nand-cmd-offset = <22>; | |
1032 | atmel,nand-has-dma; | |
1033 | pinctrl-names = "default"; | |
1034 | pinctrl-0 = <&pinctrl_nand>; | |
1035 | gpios = <&pioD 5 GPIO_ACTIVE_HIGH | |
1036 | &pioD 4 GPIO_ACTIVE_HIGH | |
1037 | 0 | |
1038 | >; | |
1039 | status = "disabled"; | |
1040 | }; | |
1041 | ||
1042 | usb0: ohci@00500000 { | |
1043 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
1044 | reg = <0x00500000 0x00100000>; | |
1045 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; | |
1046 | clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; | |
1047 | clock-names = "ohci_clk", "hclk", "uhpck"; | |
1048 | status = "disabled"; | |
1049 | }; | |
1050 | }; | |
1051 | ||
1052 | i2c-gpio-0 { | |
1053 | compatible = "i2c-gpio"; | |
1054 | gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ | |
1055 | &pioA 31 GPIO_ACTIVE_HIGH /* scl */ | |
1056 | >; | |
1057 | i2c-gpio,sda-open-drain; | |
1058 | i2c-gpio,scl-open-drain; | |
1059 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
1060 | #address-cells = <1>; | |
1061 | #size-cells = <0>; | |
1062 | status = "disabled"; | |
1063 | }; | |
1064 | }; |