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dd54739d SG |
1 | /* |
2 | * Samsung's Exynos4x12 SoCs device tree source | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 | |
8 | * based board files can include this file and provide values for board specfic | |
9 | * bindings. | |
10 | * | |
11 | * Note: This file does not include device nodes for all the controllers in | |
12 | * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional | |
13 | * nodes can be added to this file. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | ` * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
20 | #include "exynos4.dtsi" | |
21 | #include "exynos4x12-pinctrl.dtsi" | |
c6b0b090 | 22 | #include "exynos4x12-pinctrl-uboot.dtsi" |
dd54739d SG |
23 | |
24 | / { | |
25 | aliases { | |
26 | pinctrl0 = &pinctrl_0; | |
27 | pinctrl1 = &pinctrl_1; | |
28 | pinctrl2 = &pinctrl_2; | |
29 | pinctrl3 = &pinctrl_3; | |
dd54739d SG |
30 | }; |
31 | ||
32 | pd_isp: isp-power-domain@10023CA0 { | |
33 | compatible = "samsung,exynos4210-pd"; | |
34 | reg = <0x10023CA0 0x20>; | |
35 | }; | |
36 | ||
37 | clock: clock-controller@10030000 { | |
38 | compatible = "samsung,exynos4412-clock"; | |
39 | reg = <0x10030000 0x20000>; | |
40 | #clock-cells = <1>; | |
41 | }; | |
42 | ||
43 | mct@10050000 { | |
44 | compatible = "samsung,exynos4412-mct"; | |
45 | reg = <0x10050000 0x800>; | |
46 | interrupt-parent = <&mct_map>; | |
47 | interrupts = <0>, <1>, <2>, <3>, <4>; | |
48 | clocks = <&clock 3>, <&clock 344>; | |
49 | clock-names = "fin_pll", "mct"; | |
50 | ||
51 | mct_map: mct-map { | |
52 | #interrupt-cells = <1>; | |
53 | #address-cells = <0>; | |
54 | #size-cells = <0>; | |
55 | interrupt-map = <0 &gic 0 57 0>, | |
56 | <1 &combiner 12 5>, | |
57 | <2 &combiner 12 6>, | |
58 | <3 &combiner 12 7>, | |
59 | <4 &gic 1 12 0>; | |
60 | }; | |
61 | }; | |
62 | ||
63 | pinctrl_0: pinctrl@11400000 { | |
64 | compatible = "samsung,exynos4x12-pinctrl"; | |
65 | reg = <0x11400000 0x1000>; | |
d8b385b7 | 66 | interrupt-parent = <&gic>; |
dd54739d SG |
67 | interrupts = <0 47 0>; |
68 | }; | |
69 | ||
70 | pinctrl_1: pinctrl@11000000 { | |
71 | compatible = "samsung,exynos4x12-pinctrl"; | |
72 | reg = <0x11000000 0x1000>; | |
d8b385b7 | 73 | interrupt-parent = <&gic>; |
dd54739d SG |
74 | interrupts = <0 46 0>; |
75 | ||
76 | wakup_eint: wakeup-interrupt-controller { | |
77 | compatible = "samsung,exynos4210-wakeup-eint"; | |
78 | interrupt-parent = <&gic>; | |
79 | interrupts = <0 32 0>; | |
80 | }; | |
81 | }; | |
82 | ||
83 | pinctrl_2: pinctrl@03860000 { | |
84 | compatible = "samsung,exynos4x12-pinctrl"; | |
85 | reg = <0x03860000 0x1000>; | |
86 | interrupt-parent = <&combiner>; | |
87 | interrupts = <10 0>; | |
88 | }; | |
89 | ||
90 | pinctrl_3: pinctrl@106E0000 { | |
91 | compatible = "samsung,exynos4x12-pinctrl"; | |
92 | reg = <0x106E0000 0x1000>; | |
d8b385b7 | 93 | interrupt-parent = <&gic>; |
dd54739d SG |
94 | interrupts = <0 72 0>; |
95 | }; | |
96 | ||
97 | g2d@10800000 { | |
98 | compatible = "samsung,exynos4212-g2d"; | |
99 | reg = <0x10800000 0x1000>; | |
d8b385b7 | 100 | interrupt-parent = <&gic>; |
dd54739d SG |
101 | interrupts = <0 89 0>; |
102 | clocks = <&clock 177>, <&clock 277>; | |
103 | clock-names = "sclk_fimg2d", "fimg2d"; | |
104 | status = "disabled"; | |
105 | }; | |
dd54739d | 106 | }; |