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34453736 PF |
1 | /* |
2 | * Copyright 2016 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <dt-bindings/clock/imx6sll-clock.h> | |
10 | #include <dt-bindings/gpio/gpio.h> | |
11 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
12 | #include "imx6sll-pinfunc.h" | |
13 | #include "skeleton.dtsi" | |
14 | ||
15 | / { | |
16 | aliases { | |
17 | gpio0 = &gpio1; | |
18 | gpio1 = &gpio2; | |
19 | gpio2 = &gpio3; | |
20 | gpio3 = &gpio4; | |
21 | gpio4 = &gpio5; | |
22 | gpio5 = &gpio6; | |
23 | i2c0 = &i2c1; | |
24 | i2c1 = &i2c2; | |
25 | i2c2 = &i2c3; | |
26 | mmc0 = &usdhc1; | |
27 | mmc1 = &usdhc2; | |
28 | mmc2 = &usdhc3; | |
29 | serial0 = &uart1; | |
30 | serial1 = &uart2; | |
31 | serial2 = &uart3; | |
32 | serial3 = &uart4; | |
33 | serial4 = &uart5; | |
34 | spi0 = &ecspi1; | |
35 | spi1 = &ecspi2; | |
36 | spi3 = &ecspi3; | |
37 | spi4 = &ecspi4; | |
38 | usbphy0 = &usbphy1; | |
39 | usbphy1 = &usbphy2; | |
40 | }; | |
41 | ||
42 | cpus { | |
43 | #address-cells = <1>; | |
44 | #size-cells = <0>; | |
45 | ||
46 | cpu0: cpu@0 { | |
47 | compatible = "arm,cortex-a9"; | |
48 | device_type = "cpu"; | |
49 | reg = <0>; | |
50 | next-level-cache = <&L2>; | |
51 | operating-points = < | |
52 | /* kHz uV */ | |
53 | 996000 1225000 | |
54 | 792000 1175000 | |
55 | 396000 1075000 | |
56 | 198000 975000 | |
57 | >; | |
58 | fsl,soc-operating-points = < | |
59 | /* ARM kHz SOC-PU uV */ | |
60 | 996000 1225000 | |
61 | 792000 1175000 | |
62 | 396000 1175000 | |
63 | 198000 1175000 | |
64 | >; | |
65 | clock-latency = <61036>; /* two CLK32 periods */ | |
66 | fsl,low-power-run; | |
67 | clocks = <&clks IMX6SLL_CLK_ARM>, | |
68 | <&clks IMX6SLL_CLK_PLL2_PFD2>, | |
69 | <&clks IMX6SLL_CLK_STEP>, | |
70 | <&clks IMX6SLL_CLK_PLL1_SW>, | |
71 | <&clks IMX6SLL_CLK_PLL1_SYS>, | |
72 | <&clks IMX6SLL_CLK_PLL1>, | |
73 | <&clks IMX6SLL_PLL1_BYPASS>, | |
74 | <&clks IMX6SLL_PLL1_BYPASS_SRC>; | |
75 | clock-names = "arm", "pll2_pfd2_396m", "step", | |
76 | "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", | |
77 | "pll1_bypass_src"; | |
78 | }; | |
79 | }; | |
80 | ||
81 | intc: interrupt-controller@00a01000 { | |
82 | compatible = "arm,cortex-a9-gic"; | |
83 | #interrupt-cells = <3>; | |
84 | interrupt-controller; | |
85 | reg = <0x00a01000 0x1000>, | |
86 | <0x00a00100 0x100>; | |
87 | interrupt-parent = <&intc>; | |
88 | }; | |
89 | ||
90 | clocks { | |
91 | #address-cells = <1>; | |
92 | #size-cells = <0>; | |
93 | ||
94 | ckil: clock@0 { | |
95 | compatible = "fixed-clock"; | |
96 | reg = <0>; | |
97 | #clock-cells = <0>; | |
98 | clock-frequency = <32768>; | |
99 | clock-output-names = "ckil"; | |
100 | }; | |
101 | ||
102 | osc: clock@1 { | |
103 | compatible = "fixed-clock"; | |
104 | reg = <1>; | |
105 | #clock-cells = <0>; | |
106 | clock-frequency = <24000000>; | |
107 | clock-output-names = "osc"; | |
108 | }; | |
109 | ||
110 | ipp_di0: clock@2 { | |
111 | compatible = "fixed-clock"; | |
112 | reg = <2>; | |
113 | #clock-cells = <0>; | |
114 | clock-frequency = <0>; | |
115 | clock-output-names = "ipp_di0"; | |
116 | }; | |
117 | ||
118 | ipp_di1: clock@3 { | |
119 | compatible = "fixed-clock"; | |
120 | reg = <3>; | |
121 | #clock-cells = <0>; | |
122 | clock-frequency = <0>; | |
123 | clock-output-names = "ipp_di1"; | |
124 | }; | |
125 | }; | |
126 | ||
127 | soc { | |
128 | #address-cells = <1>; | |
129 | #size-cells = <1>; | |
130 | compatible = "simple-bus"; | |
131 | interrupt-parent = <&gpc>; | |
132 | ranges; | |
133 | ||
134 | busfreq { | |
135 | compatible = "fsl,imx_busfreq"; | |
136 | clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>, | |
137 | <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>, | |
138 | <&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>, | |
139 | <&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>, | |
140 | <&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>, | |
141 | <&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>, | |
142 | <&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>, | |
143 | <&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>, | |
144 | <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>, | |
145 | <&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>, | |
146 | <&clks IMX6SLL_CLK_PLL1>; | |
147 | clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", | |
148 | "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", | |
149 | "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", | |
150 | "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; | |
151 | fsl,max_ddr_freq = <400000000>; | |
152 | }; | |
153 | ||
154 | ocrams: sram@00900000 { | |
155 | compatible = "fsl,lpm-sram"; | |
156 | reg = <0x00900000 0x4000>; | |
157 | }; | |
158 | ||
159 | ocrams_ddr: sram@00904000 { | |
160 | compatible = "fsl,ddr-lpm-sram"; | |
161 | reg = <0x00904000 0x1000>; | |
162 | }; | |
163 | ||
164 | ocram: sram@00905000 { | |
165 | compatible = "mmio-sram"; | |
166 | reg = <0x00905000 0x1B000>; | |
167 | }; | |
168 | ||
169 | L2: l2-cache@00a02000 { | |
170 | compatible = "arm,pl310-cache"; | |
171 | reg = <0x00a02000 0x1000>; | |
172 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; | |
173 | cache-unified; | |
174 | cache-level = <2>; | |
175 | arm,tag-latency = <4 2 3>; | |
176 | arm,data-latency = <4 2 3>; | |
177 | }; | |
178 | ||
179 | aips1: aips-bus@02000000 { | |
180 | compatible = "fsl,aips-bus", "simple-bus"; | |
181 | #address-cells = <1>; | |
182 | #size-cells = <1>; | |
183 | reg = <0x02000000 0x100000>; | |
184 | ranges; | |
185 | ||
186 | spba: spba-bus@02000000 { | |
187 | compatible = "fsl,spba-bus", "simple-bus"; | |
188 | #address-cells = <1>; | |
189 | #size-cells = <1>; | |
190 | reg = <0x02000000 0x40000>; | |
191 | ranges; | |
192 | ||
193 | spdif: spdif@02004000 { | |
194 | compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; | |
195 | reg = <0x02004000 0x4000>; | |
196 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
197 | dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; | |
198 | dma-names = "rx", "tx"; | |
199 | clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, | |
200 | <&clks IMX6SLL_CLK_OSC>, | |
201 | <&clks IMX6SLL_CLK_SPDIF>, | |
202 | <&clks IMX6SLL_CLK_DUMMY>, | |
203 | <&clks IMX6SLL_CLK_DUMMY>, | |
204 | <&clks IMX6SLL_CLK_DUMMY>, | |
205 | <&clks IMX6SLL_CLK_IPG>, | |
206 | <&clks IMX6SLL_CLK_DUMMY>, | |
207 | <&clks IMX6SLL_CLK_DUMMY>, | |
208 | <&clks IMX6SLL_CLK_SPBA>; | |
209 | clock-names = "core", "rxtx0", | |
210 | "rxtx1", "rxtx2", | |
211 | "rxtx3", "rxtx4", | |
212 | "rxtx5", "rxtx6", | |
213 | "rxtx7", "dma"; | |
214 | status = "disabled"; | |
215 | }; | |
216 | ||
217 | ecspi1: ecspi@02008000 { | |
218 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
219 | reg = <0x02008000 0x4000>; | |
220 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
221 | dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; | |
222 | dma-names = "rx", "tx"; | |
223 | clocks = <&clks IMX6SLL_CLK_ECSPI1>, | |
224 | <&clks IMX6SLL_CLK_ECSPI1>; | |
225 | clock-names = "ipg", "per"; | |
226 | status = "disabled"; | |
227 | }; | |
228 | ||
229 | ecspi2: ecspi@0200c000 { | |
230 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
231 | reg = <0x0200c000 0x4000>; | |
232 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
233 | dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; | |
234 | dma-names = "rx", "tx"; | |
235 | clocks = <&clks IMX6SLL_CLK_ECSPI2>, | |
236 | <&clks IMX6SLL_CLK_ECSPI2>; | |
237 | clock-names = "ipg", "per"; | |
238 | status = "disabled"; | |
239 | }; | |
240 | ||
241 | ecspi3: ecspi@02010000 { | |
242 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
243 | reg = <0x02010000 0x4000>; | |
244 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
245 | dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; | |
246 | dma-names = "rx", "tx"; | |
247 | clocks = <&clks IMX6SLL_CLK_ECSPI3>, | |
248 | <&clks IMX6SLL_CLK_ECSPI3>; | |
249 | clock-names = "ipg", "per"; | |
250 | status = "disabled"; | |
251 | }; | |
252 | ||
253 | ecspi4: ecspi@02014000 { | |
254 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
255 | reg = <0x02014000 0x4000>; | |
256 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
257 | dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; | |
258 | dma-names = "rx", "tx"; | |
259 | clocks = <&clks IMX6SLL_CLK_ECSPI4>, | |
260 | <&clks IMX6SLL_CLK_ECSPI4>; | |
261 | clock-names = "ipg", "per"; | |
262 | status = "disabled"; | |
263 | }; | |
264 | ||
265 | uart4: serial@02018000 { | |
266 | compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; | |
267 | reg = <0x02018000 0x4000>; | |
268 | interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
269 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; | |
270 | dma-names = "rx", "tx"; | |
271 | clocks = <&clks IMX6SLL_CLK_UART4_IPG>, | |
272 | <&clks IMX6SLL_CLK_UART4_SERIAL>; | |
273 | clock-names = "ipg", "per"; | |
274 | status = "disabled"; | |
275 | }; | |
276 | ||
277 | uart1: serial@02020000 { | |
278 | compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; | |
279 | reg = <0x02020000 0x4000>; | |
280 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
281 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; | |
282 | dma-names = "rx", "tx"; | |
283 | clocks = <&clks IMX6SLL_CLK_UART1_IPG>, | |
284 | <&clks IMX6SLL_CLK_UART1_SERIAL>; | |
285 | clock-names = "ipg", "per"; | |
286 | status = "disabled"; | |
287 | }; | |
288 | ||
289 | uart2: serial@02024000 { | |
290 | compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; | |
291 | reg = <0x02024000 0x4000>; | |
292 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
293 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; | |
294 | dma-names = "rx", "tx"; | |
295 | clocks = <&clks IMX6SLL_CLK_UART2_IPG>, | |
296 | <&clks IMX6SLL_CLK_UART2_SERIAL>; | |
297 | clock-names = "ipg", "per"; | |
298 | status = "disabled"; | |
299 | }; | |
300 | ||
301 | ssi1: ssi@02028000 { | |
302 | compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi"; | |
303 | reg = <0x02028000 0x4000>; | |
304 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
305 | dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; | |
306 | dma-names = "rx", "tx"; | |
307 | fsl,fifo-depth = <15>; | |
308 | clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, | |
309 | <&clks IMX6SLL_CLK_SSI1>; | |
310 | clock-names = "ipg", "baud"; | |
311 | status = "disabled"; | |
312 | }; | |
313 | ||
314 | ssi2: ssi2@0202c000 { | |
315 | compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi"; | |
316 | reg = <0x0202c000 0x4000>; | |
317 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | |
318 | dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; | |
319 | dma-names = "rx", "tx"; | |
320 | fsl,fifo-depth = <15>; | |
321 | clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, | |
322 | <&clks IMX6SLL_CLK_SSI2>; | |
323 | clock-names = "ipg", "baud"; | |
324 | status = "disabled"; | |
325 | }; | |
326 | ||
327 | ssi3: ssi@02030000 { | |
328 | compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi"; | |
329 | reg = <0x02030000 0x4000>; | |
330 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
331 | dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; | |
332 | dma-names = "rx", "tx"; | |
333 | fsl,fifo-depth = <15>; | |
334 | clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, | |
335 | <&clks IMX6SLL_CLK_SSI3>; | |
336 | clock-names = "ipg", "baud"; | |
337 | status = "disabled"; | |
338 | }; | |
339 | ||
340 | uart3: serial@02034000 { | |
341 | compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; | |
342 | reg = <0x02034000 0x4000>; | |
343 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
344 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; | |
345 | dma-name = "rx", "tx"; | |
346 | clocks = <&clks IMX6SLL_CLK_UART3_IPG>, | |
347 | <&clks IMX6SLL_CLK_UART3_SERIAL>; | |
348 | clock-names = "ipg", "per"; | |
349 | status = "disabled"; | |
350 | }; | |
351 | }; | |
352 | ||
353 | pwm1: pwm@02080000 { | |
354 | compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; | |
355 | reg = <0x02080000 0x4000>; | |
356 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
357 | clocks = <&clks IMX6SLL_CLK_PWM1>, | |
358 | <&clks IMX6SLL_CLK_PWM1>; | |
359 | clock-names = "ipg", "per"; | |
360 | #pwm-cells = <2>; | |
361 | }; | |
362 | ||
363 | pwm2: pwm@02084000 { | |
364 | compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; | |
365 | reg = <0x02084000 0x4000>; | |
366 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
367 | clocks = <&clks IMX6SLL_CLK_PWM2>, | |
368 | <&clks IMX6SLL_CLK_PWM2>; | |
369 | clock-names = "ipg", "per"; | |
370 | #pwm-cells = <2>; | |
371 | }; | |
372 | ||
373 | pwm3: pwm@02088000 { | |
374 | compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; | |
375 | reg = <0x02088000 0x4000>; | |
376 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
377 | clocks = <&clks IMX6SLL_CLK_PWM3>, | |
378 | <&clks IMX6SLL_CLK_PWM3>; | |
379 | clock-names = "ipg", "per"; | |
380 | #pwm-cells = <2>; | |
381 | }; | |
382 | ||
383 | pwm4: pwm@0208c000 { | |
384 | compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; | |
385 | reg = <0x0208c000 0x4000>; | |
386 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
387 | clocks = <&clks IMX6SLL_CLK_PWM4>, | |
388 | <&clks IMX6SLL_CLK_PWM4>; | |
389 | clock-names = "ipg", "per"; | |
390 | #pwm-cells = <2>; | |
391 | }; | |
392 | ||
393 | gpt1: gpt@02098000 { | |
394 | compatible = "fsl,imx6sll-gpt"; | |
395 | reg = <0x02098000 0x4000>; | |
396 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
397 | clocks = <&clks IMX6SLL_CLK_GPT_BUS>, | |
398 | <&clks IMX6SLL_CLK_GPT_SERIAL>; | |
399 | clock-names = "ipg", "per"; | |
400 | }; | |
401 | ||
402 | gpio1: gpio@0209c000 { | |
403 | compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; | |
404 | reg = <0x0209c000 0x4000>; | |
405 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, | |
406 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
407 | gpio-controller; | |
408 | #gpio-cells = <2>; | |
409 | interrupt-controller; | |
410 | #interrupt-cells = <2>; | |
411 | }; | |
412 | ||
413 | gpio2: gpio@020a0000 { | |
414 | compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; | |
415 | reg = <0x020a0000 0x4000>; | |
416 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
417 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
418 | gpio-controller; | |
419 | #gpio-cells = <2>; | |
420 | interrupt-controller; | |
421 | #interrupt-cells = <2>; | |
422 | }; | |
423 | ||
424 | gpio3: gpio@020a4000 { | |
425 | compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; | |
426 | reg = <0x020a4000 0x4000>; | |
427 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
428 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
429 | gpio-controller; | |
430 | #gpio-cells = <2>; | |
431 | interrupt-controller; | |
432 | #interrupt-cells = <2>; | |
433 | }; | |
434 | ||
435 | gpio4: gpio@020a8000 { | |
436 | compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; | |
437 | reg = <0x020a8000 0x4000>; | |
438 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
439 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
440 | gpio-controller; | |
441 | #gpio-cells = <2>; | |
442 | interrupt-controller; | |
443 | #interrupt-cells = <2>; | |
444 | }; | |
445 | ||
446 | gpio5: gpio@020ac000 { | |
447 | compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; | |
448 | reg = <0x020ac000 0x4000>; | |
449 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | |
450 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
451 | gpio-controller; | |
452 | #gpio-cells = <2>; | |
453 | interrupt-controller; | |
454 | #interrupt-cells = <2>; | |
455 | }; | |
456 | ||
457 | gpio6: gpio@020b0000 { | |
458 | compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; | |
459 | reg = <0x020b0000 0x4000>; | |
460 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | |
461 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
462 | gpio-controller; | |
463 | #gpio-cells = <2>; | |
464 | interrupt-controller; | |
465 | #interrupt-cells = <2>; | |
466 | }; | |
467 | ||
468 | kpp: kpp@020b8000 { | |
469 | compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; | |
470 | reg = <0x020b8000 0x4000>; | |
471 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
472 | clocks = <&clks IMX6SLL_CLK_KPP>; | |
473 | status = "disabled"; | |
474 | }; | |
475 | ||
476 | wdog1: wdog@020bc000 { | |
477 | compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; | |
478 | reg = <0x020bc000 0x4000>; | |
479 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
480 | clocks = <&clks IMX6SLL_CLK_WDOG1>; | |
481 | }; | |
482 | ||
483 | wdog2: wdog@020c0000 { | |
484 | compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; | |
485 | reg = <0x020c0000 0x4000>; | |
486 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
487 | clocks = <&clks IMX6SLL_CLK_WDOG2>; | |
488 | status = "disabled"; | |
489 | }; | |
490 | ||
491 | clks: ccm@020c4000 { | |
492 | compatible = "fsl,imx6sll-ccm"; | |
493 | reg = <0x020c4000 0x4000>; | |
494 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
495 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
496 | #clock-cells = <1>; | |
497 | clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; | |
498 | clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; | |
499 | }; | |
500 | ||
501 | anatop: anatop@020c8000 { | |
502 | compatible = "fsl,imx6sll-anatop", | |
503 | "fsl,imx6q-anatop", | |
504 | "syscon", "simple-bus"; | |
505 | reg = <0x020c8000 0x4000>; | |
506 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
507 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
508 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
509 | ||
510 | reg_3p0: regulator-3p0@120 { | |
511 | compatible = "fsl,anatop-regulator"; | |
512 | regulator-name = "vdd3p0"; | |
513 | regulator-min-microvolt = <2625000>; | |
514 | regulator-max-microvolt = <3400000>; | |
515 | anatop-reg-offset = <0x120>; | |
516 | anatop-vol-bit-shift = <8>; | |
517 | anatop-vol-bit-width = <5>; | |
518 | anatop-min-bit-val = <0>; | |
519 | anatop-min-voltage = <2625000>; | |
520 | anatop-max-voltage = <3400000>; | |
521 | anatop-enable-bit = <0>; | |
522 | }; | |
523 | }; | |
524 | ||
525 | tempmon: tempmon { | |
526 | compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; | |
527 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
528 | fsl,tempmon = <&anatop>; | |
529 | fsl,tempmon-data = <&ocotp>; | |
530 | clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; | |
531 | status = "disabled"; | |
532 | }; | |
533 | ||
534 | usbphy1: usbphy@020c9000 { | |
535 | compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", | |
536 | "fsl,imx23-usbphy"; | |
537 | reg = <0x020c9000 0x1000>; | |
538 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
539 | clocks = <&clks IMX6SLL_CLK_USBPHY1>; | |
540 | phy-3p0-supply = <®_3p0>; | |
541 | fsl,anatop = <&anatop>; | |
542 | }; | |
543 | ||
544 | usbphy2: usbphy@020ca000 { | |
545 | compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", | |
546 | "fsl,imx23-usbphy"; | |
547 | reg = <0x020ca000 0x1000>; | |
548 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
549 | clocks = <&clks IMX6SLL_CLK_USBPHY2>; | |
550 | phy-reg_3p0-supply = <®_3p0>; | |
551 | fsl,anatop = <&anatop>; | |
552 | }; | |
553 | ||
554 | snvs: snvs@020cc000 { | |
555 | compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; | |
556 | reg = <0x020cc000 0x4000>; | |
557 | ||
558 | snvs_rtc: snvs-rtc-lp { | |
559 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
560 | regmap = <&snvs>; | |
561 | offset = <0x34>; | |
562 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
563 | }; | |
564 | ||
565 | snvs_poweroff: snvs-poweroff { | |
566 | compatible = "syscon-poweroff"; | |
567 | regmap = <&snvs>; | |
568 | offset = <0x38>; | |
569 | mask = <0x61>; | |
570 | }; | |
571 | ||
572 | snvs_pwrkey: snvs-powerkey { | |
573 | compatible = "fsl,sec-v4.0-pwrkey"; | |
574 | regmap = <&snvs>; | |
575 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
576 | linux,keycode = <KEY_POWER>; | |
577 | wakeup; | |
578 | }; | |
579 | }; | |
580 | ||
581 | epit1: epit@020d0000 { | |
582 | reg = <0x020d0000 0x4000>; | |
583 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
584 | }; | |
585 | ||
586 | epit2: epit@020d4000 { | |
587 | reg = <0x020d4000 0x4000>; | |
588 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
589 | }; | |
590 | ||
591 | src: src@020d8000 { | |
592 | compatible = "fsl,imx6sll-src", "fsl,imx51-src"; | |
593 | reg = <0x020d8000 0x4000>; | |
594 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | |
595 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
596 | #reset-cells = <1>; | |
597 | }; | |
598 | ||
599 | gpc: gpc@020dc000 { | |
600 | compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; | |
601 | reg = <0x020dc000 0x4000>; | |
602 | interrupt-controller; | |
603 | #interrupt-cells = <3>; | |
604 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
605 | interrupt-parent = <&intc>; | |
606 | fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; | |
607 | }; | |
608 | ||
609 | iomuxc: iomuxc@020e0000 { | |
610 | compatible = "fsl,imx6sll-iomuxc"; | |
611 | reg = <0x020e0000 0x4000>; | |
612 | }; | |
613 | ||
614 | gpr: iomuxc-gpr@020e4000 { | |
615 | compatible = "fsl,imx6sll-iomuxc-gpr", | |
616 | "fsl,imx6q-iomuxc-gpr", "syscon"; | |
617 | reg = <0x020e4000 0x4000>; | |
618 | }; | |
619 | ||
620 | csi: csi@020e8000 { | |
621 | compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; | |
622 | reg = <0x020e8000 0x4000>; | |
623 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
624 | clocks = <&clks IMX6SLL_CLK_DUMMY>, | |
625 | <&clks IMX6SLL_CLK_CSI>, | |
626 | <&clks IMX6SLL_CLK_DUMMY>; | |
627 | clock-names = "disp-axi", "csi_mclk", "disp_dcic"; | |
628 | status = "disabled"; | |
629 | }; | |
630 | ||
631 | sdma: sdma@020ec000 { | |
632 | compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; | |
633 | reg = <0x020ec000 0x4000>; | |
634 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
635 | clocks = <&clks IMX6SLL_CLK_SDMA>, | |
636 | <&clks IMX6SLL_CLK_SDMA>; | |
637 | clock-names = "ipg", "ahb"; | |
638 | #dma-cells = <3>; | |
639 | iram = <&ocram>; | |
640 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; | |
641 | }; | |
642 | ||
643 | pxp: pxp@020f0000 { | |
644 | compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; | |
645 | reg = <0x020f0000 0x4000>; | |
646 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, | |
647 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
648 | clocks = <&clks IMX6SLL_CLK_DUMMY>, | |
649 | <&clks IMX6SLL_CLK_PXP>; | |
650 | clock-names = "pxp_ipg", "pxp_axi"; | |
651 | status = "disabled"; | |
652 | }; | |
653 | ||
654 | epdc: epdc@020f4000 { | |
655 | compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc"; | |
656 | reg = <0x020f4000 0x4000>; | |
657 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
658 | clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, <&clks IMX6SLL_CLK_EPDC_PIX>; | |
659 | clock-names = "epdc_axi", "epdc_pix"; | |
660 | status = "disabled"; | |
661 | }; | |
662 | ||
663 | lcdif: lcdif@020f8000 { | |
664 | compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; | |
665 | reg = <0x020f8000 0x4000>; | |
666 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
667 | clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, | |
668 | <&clks IMX6SLL_CLK_LCDIF_APB>, | |
669 | <&clks IMX6SLL_CLK_DUMMY>; | |
670 | clock-names = "pix", "axi", "disp_axi"; | |
671 | status = "disabled"; | |
672 | }; | |
673 | ||
674 | dcp: dcp@020fc000 { | |
675 | compatible = "fsl,imx6sl-dcp"; | |
676 | reg = <0x020fc000 0x4000>; | |
677 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, | |
678 | <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, | |
679 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
680 | clocks = <&clks IMX6SLL_CLK_DCP>; | |
681 | clock-names = "dcp"; | |
682 | }; | |
683 | }; | |
684 | ||
685 | aips2: aips-bus@02100000 { | |
686 | compatible = "fsl,aips-bus", "simple-bus"; | |
687 | #address-cells = <1>; | |
688 | #size-cells = <1>; | |
689 | reg = <0x02100000 0x100000>; | |
690 | ranges; | |
691 | ||
692 | usbotg1: usb@02184000 { | |
693 | compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", | |
694 | "fsl,imx27-usb"; | |
695 | reg = <0x02184000 0x200>; | |
696 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
697 | clocks = <&clks IMX6SLL_CLK_USBOH3>; | |
698 | fsl,usbphy = <&usbphy1>; | |
699 | fsl,usbmisc = <&usbmisc 0>; | |
700 | fsl,anatop = <&anatop>; | |
701 | ahb-burst-config = <0x0>; | |
702 | tx-burst-size-dword = <0x10>; | |
703 | rx-burst-size-dword = <0x10>; | |
704 | status = "disabled"; | |
705 | }; | |
706 | ||
707 | usbotg2: usb@02184200 { | |
708 | compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", | |
709 | "fsl,imx27-usb"; | |
710 | reg = <0x02184200 0x200>; | |
711 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
712 | clocks = <&clks IMX6SLL_CLK_USBOH3>; | |
713 | fsl,usbphy = <&usbphy2>; | |
714 | fsl,usbmisc = <&usbmisc 1>; | |
715 | ahb-burst-config = <0x0>; | |
716 | tx-burst-size-dword = <0x10>; | |
717 | rx-burst-size-dword = <0x10>; | |
718 | status = "disabled"; | |
719 | }; | |
720 | ||
721 | usbmisc: usbmisc@02184800 { | |
722 | #index-cells = <1>; | |
723 | compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", | |
724 | "fsl,imx6q-usbmisc"; | |
725 | reg = <0x02184800 0x200>; | |
726 | }; | |
727 | ||
728 | usdhc1: usdhc@02190000 { | |
729 | compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; | |
730 | reg = <0x02190000 0x4000>; | |
731 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
732 | clocks = <&clks IMX6SLL_CLK_USDHC1>, | |
733 | <&clks IMX6SLL_CLK_USDHC1>, | |
734 | <&clks IMX6SLL_CLK_USDHC1>; | |
735 | clock-names = "ipg", "ahb", "per"; | |
736 | bus-width = <4>; | |
737 | fsl,tuning-step = <2>; | |
738 | fsl,tuning-start-tap = <20>; | |
739 | status = "disabled"; | |
740 | }; | |
741 | ||
742 | usdhc2: usdhc@02194000 { | |
743 | compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; | |
744 | reg = <0x02194000 0x4000>; | |
745 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
746 | clocks = <&clks IMX6SLL_CLK_USDHC2>, | |
747 | <&clks IMX6SLL_CLK_USDHC2>, | |
748 | <&clks IMX6SLL_CLK_USDHC2>; | |
749 | clock-names = "ipg", "ahb", "per"; | |
750 | bus-width = <4>; | |
751 | fsl,tuning-step = <2>; | |
752 | fsl,tuning-start-tap = <20>; | |
753 | status = "disabled"; | |
754 | }; | |
755 | ||
756 | usdhc3: usdhc@02198000 { | |
757 | compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; | |
758 | reg = <0x02198000 0x4000>; | |
759 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
760 | clocks = <&clks IMX6SLL_CLK_USDHC3>, | |
761 | <&clks IMX6SLL_CLK_USDHC3>, | |
762 | <&clks IMX6SLL_CLK_USDHC3>; | |
763 | clock-names = "ipg", "ahb", "per"; | |
764 | bus-width = <4>; | |
765 | fsl,tuning-step = <2>; | |
766 | fsl,tuning-start-tap = <20>; | |
767 | status = "disabled"; | |
768 | }; | |
769 | ||
770 | i2c1: i2c@021a0000 { | |
771 | #address-cells = <1>; | |
772 | #size-cells = <0>; | |
773 | compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c"; | |
774 | reg = <0x021a0000 0x4000>; | |
775 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
776 | clocks = <&clks IMX6SLL_CLK_I2C1>; | |
777 | status = "disabled"; | |
778 | }; | |
779 | ||
780 | i2c2: i2c@021a4000 { | |
781 | #address-cells = <1>; | |
782 | #size-cells = <0>; | |
783 | compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; | |
784 | reg = <0x021a4000 0x4000>; | |
785 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
786 | clocks = <&clks IMX6SLL_CLK_I2C2>; | |
787 | status = "disabled"; | |
788 | }; | |
789 | ||
790 | i2c3: i2c@021a8000 { | |
791 | #address-cells = <1>; | |
792 | #size-cells = <0>; | |
793 | compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; | |
794 | reg = <0x021a8000 0x4000>; | |
795 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
796 | clocks = <&clks IMX6SLL_CLK_I2C3>; | |
797 | status = "disabled"; | |
798 | }; | |
799 | ||
800 | romcp@021ac000 { | |
801 | compatible = "fsl,imx6sll-romcp", "syscon"; | |
802 | reg = <0x021ac000 0x4000>; | |
803 | }; | |
804 | ||
805 | mmdc: mmdc@021b0000 { | |
806 | compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; | |
807 | reg = <0x021b0000 0x4000>; | |
808 | }; | |
809 | ||
810 | rngb: rngb@021b4000 { | |
811 | compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng"; | |
812 | reg = <0x021b4000 0x4000>; | |
813 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
814 | clocks = <&clks IMX6SLL_CLK_DUMMY>; | |
815 | }; | |
816 | ||
817 | ocotp: ocotp-ctrl@021bc000 { | |
818 | compatible = "fsl,imx6sll-ocotp", "syscon"; | |
819 | reg = <0x021bc000 0x4000>; | |
820 | clocks = <&clks IMX6SLL_CLK_OCOTP>; | |
821 | }; | |
822 | ||
823 | csu: csu@021c0000 { | |
824 | compatible = "fsl,imx6sll-csu"; | |
825 | reg = <0x021c0000 0x4000>; | |
826 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
827 | status = "disabled"; | |
828 | }; | |
829 | ||
830 | snvs_gpr: snvs-gpr@0x021c4000 { | |
831 | compatible = "fsl, imx6sll-snvs-gpr"; | |
832 | reg = <0x021c4000 0x10000>; | |
833 | }; | |
834 | ||
835 | iomuxc_snvs: iomuxc-snvs@021c8000 { | |
836 | compatible = "fsl,imx6sll-iomuxc-snvs"; | |
837 | reg = <0x021c80000 0x10000>; | |
838 | }; | |
839 | ||
840 | audmux: audmux@021d8000 { | |
841 | compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; | |
842 | reg = <0x021d8000 0x4000>; | |
843 | status = "disabled"; | |
844 | }; | |
845 | ||
846 | uart5: serial@021f4000 { | |
847 | compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; | |
848 | reg = <0x021f4000 0x4000>; | |
849 | interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
850 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; | |
851 | dma-names = "rx", "tx"; | |
852 | clocks = <&clks IMX6SLL_CLK_UART5_IPG>, | |
853 | <&clks IMX6SLL_CLK_UART5_SERIAL>; | |
854 | clock-names = "ipg", "per"; | |
855 | status = "disabled"; | |
856 | }; | |
857 | }; | |
858 | }; | |
859 | }; |