[thirdparty/u-boot.git] / arch / arm / dts / imx93-11x11-evk-u-boot.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2022 NXP
 */

/ {
	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&wdog3>;
		bootph-pre-ram;
	};

	aliases {
		usbgadget0 = &usbg1;
		usbgadget1 = &usbg2;
	};

	usbg1: usbg1 {
		compatible = "fsl,imx27-usb-gadget";
		dr_mode = "peripheral";
		chipidea,usb = <&usbotg1>;
		status = "okay";
	};

	usbg2: usbg2 {
		compatible = "fsl,imx27-usb-gadget";
		dr_mode = "peripheral";
		chipidea,usb = <&usbotg2>;
		status = "okay";
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

&{/soc@0} {
	bootph-all;
	bootph-pre-ram;
};

&aips1 {
	bootph-pre-ram;
	bootph-all;
};

&aips2 {
	bootph-pre-ram;
};

&aips3 {
	bootph-pre-ram;
};

&iomuxc {
	bootph-pre-ram;
};

&reg_usdhc2_vmmc {
	u-boot,off-on-delay-us = <20000>;
	bootph-pre-ram;
};

&pinctrl_reg_usdhc2_vmmc {
	bootph-pre-ram;
};

&pinctrl_uart1 {
	bootph-pre-ram;
};

&pinctrl_usdhc2_gpio {
	bootph-pre-ram;
};

&pinctrl_usdhc2 {
	bootph-pre-ram;
};

&gpio1 {
	bootph-pre-ram;
};

&gpio2 {
	bootph-pre-ram;
};

&gpio3 {
	bootph-pre-ram;
};

&gpio4 {
	bootph-pre-ram;
};

&lpuart1 {
	bootph-pre-ram;
};

&usdhc1 {
	bootph-pre-ram;
};

&usdhc2 {
	bootph-pre-ram;
	fsl,signal-voltage-switch-extra-delay-ms = <8>;
};

&lpi2c2 {
	bootph-pre-ram;
};

&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
	bootph-pre-ram;
};

&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
	bootph-pre-ram;
};

&pinctrl_lpi2c2 {
	bootph-pre-ram;
};

&fec {
	phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <15>;
	phy-reset-post-delay = <100>;
};

&eqos {
	compatible = "fsl,imx-eqos";
};

&ethphy1 {
	reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
	reset-assert-us = <15000>;
	reset-deassert-us = <100000>;
};

&usbotg1 {
	status = "okay";
	extcon = <&ptn5110>;
};

&usbotg2 {
	status = "okay";
	extcon = <&ptn5110_2>;
};

&s4muap {
	bootph-pre-ram;
	status = "okay";
};
Commit	Line	Data
86a17970 PF	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2022 NXP
	4	*/
	5
	6	/ {
	7	wdt-reboot {
	8	compatible = "wdt-reboot";
	9	wdt = <&wdog3>;
8c103c33	10	bootph-pre-ram;
86a17970 PF	11	};
	12
	13	aliases {
	14	usbgadget0 = &usbg1;
	15	usbgadget1 = &usbg2;
	16	};
	17
	18	usbg1: usbg1 {
	19	compatible = "fsl,imx27-usb-gadget";
	20	dr_mode = "peripheral";
	21	chipidea,usb = <&usbotg1>;
	22	status = "okay";
	23	};
	24
	25	usbg2: usbg2 {
	26	compatible = "fsl,imx27-usb-gadget";
	27	dr_mode = "peripheral";
	28	chipidea,usb = <&usbotg2>;
	29	status = "okay";
	30	};
	31
	32	firmware {
	33	optee {
	34	compatible = "linaro,optee-tz";
	35	method = "smc";
	36	};
	37	};
	38	};
	39
	40	&{/soc@0} {
8c103c33 SG	41	bootph-all;
8c103c33 SG	42	bootph-pre-ram;
86a17970 PF	43	};
	44
	45	&aips1 {
8c103c33 SG	46	bootph-pre-ram;
8c103c33 SG	47	bootph-all;
86a17970 PF	48	};
	49
	50	&aips2 {
8c103c33	51	bootph-pre-ram;
86a17970 PF	52	};
	53
	54	&aips3 {
8c103c33	55	bootph-pre-ram;
86a17970 PF	56	};
	57
	58	&iomuxc {
8c103c33	59	bootph-pre-ram;
86a17970 PF	60	};
	61
	62	&reg_usdhc2_vmmc {
	63	u-boot,off-on-delay-us = <20000>;
8c103c33	64	bootph-pre-ram;
86a17970 PF	65	};
	66
	67	&pinctrl_reg_usdhc2_vmmc {
8c103c33	68	bootph-pre-ram;
86a17970 PF	69	};
	70
	71	&pinctrl_uart1 {
8c103c33	72	bootph-pre-ram;
86a17970 PF	73	};
	74
	75	&pinctrl_usdhc2_gpio {
8c103c33	76	bootph-pre-ram;
86a17970 PF	77	};
	78
	79	&pinctrl_usdhc2 {
8c103c33	80	bootph-pre-ram;
86a17970 PF	81	};
	82
	83	&gpio1 {
8c103c33	84	bootph-pre-ram;
86a17970 PF	85	};
	86
	87	&gpio2 {
8c103c33	88	bootph-pre-ram;
86a17970 PF	89	};
	90
	91	&gpio3 {
8c103c33	92	bootph-pre-ram;
86a17970 PF	93	};
	94
	95	&gpio4 {
8c103c33	96	bootph-pre-ram;
86a17970 PF	97	};
	98
	99	&lpuart1 {
8c103c33	100	bootph-pre-ram;
86a17970 PF	101	};
	102
	103	&usdhc1 {
8c103c33	104	bootph-pre-ram;
86a17970 PF	105	};
	106
	107	&usdhc2 {
8c103c33	108	bootph-pre-ram;
86a17970 PF	109	fsl,signal-voltage-switch-extra-delay-ms = <8>;
	110	};
	111
	112	&lpi2c2 {
8c103c33	113	bootph-pre-ram;
86a17970 PF	114	};
	115
	116	&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
8c103c33	117	bootph-pre-ram;
86a17970 PF	118	};
	119
	120	&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
8c103c33	121	bootph-pre-ram;
86a17970 PF	122	};
	123
	124	&pinctrl_lpi2c2 {
8c103c33	125	bootph-pre-ram;
86a17970 PF	126	};
	127
	128	&fec {
	129	phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
	130	phy-reset-duration = <15>;
	131	phy-reset-post-delay = <100>;
	132	};
	133
	134	&eqos {
	135	compatible = "fsl,imx-eqos";
	136	};
	137
	138	&ethphy1 {
	139	reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
	140	reset-assert-us = <15000>;
	141	reset-deassert-us = <100000>;
	142	};
	143
	144	&usbotg1 {
	145	status = "okay";
	146	extcon = <&ptn5110>;
	147	};
	148
	149	&usbotg2 {
	150	status = "okay";
	151	extcon = <&ptn5110_2>;
	152	};
	153
	154	&s4muap {
8c103c33	155	bootph-pre-ram;
86a17970 PF	156	status = "okay";
86a17970 PF	157	};