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Commit | Line | Data |
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ddf79f36 | 1 | /* |
d83b47b7 | 2 | * Freescale ls1021a QDS board common device tree source |
ddf79f36 | 3 | * |
4 | * Copyright 2013-2015 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
ddf79f36 | 9 | #include "ls1021a.dtsi" |
10 | ||
11 | / { | |
12 | model = "LS1021A QDS Board"; | |
13 | ||
14 | aliases { | |
15 | enet0_rgmii_phy = &rgmii_phy1; | |
16 | enet1_rgmii_phy = &rgmii_phy2; | |
17 | enet2_rgmii_phy = &rgmii_phy3; | |
18 | enet0_sgmii_phy = &sgmii_phy1c; | |
19 | enet1_sgmii_phy = &sgmii_phy1d; | |
863b4e1b | 20 | spi0 = &qspi; |
6db79c44 | 21 | spi1 = &dspi0; |
ddf79f36 | 22 | }; |
23 | }; | |
24 | ||
25 | &dspi0 { | |
26 | bus-num = <0>; | |
27 | status = "okay"; | |
28 | ||
29 | dspiflash: at45db021d@0 { | |
30 | #address-cells = <1>; | |
31 | #size-cells = <1>; | |
69a27ea8 | 32 | compatible = "atmel,dataflash"; |
ddf79f36 | 33 | spi-max-frequency = <16000000>; |
34 | spi-cpol; | |
35 | spi-cpha; | |
36 | reg = <0>; | |
37 | }; | |
38 | }; | |
39 | ||
863b4e1b HW |
40 | &qspi { |
41 | bus-num = <0>; | |
42 | status = "okay"; | |
43 | ||
44 | qflash0: s25fl128s@0 { | |
45 | #address-cells = <1>; | |
46 | #size-cells = <1>; | |
47 | compatible = "spi-flash"; | |
48 | spi-max-frequency = <20000000>; | |
49 | reg = <0>; | |
50 | }; | |
51 | }; | |
52 | ||
ddf79f36 | 53 | &i2c0 { |
54 | status = "okay"; | |
55 | ||
56 | pca9547: mux@77 { | |
57 | reg = <0x77>; | |
58 | #address-cells = <1>; | |
59 | #size-cells = <0>; | |
60 | ||
61 | i2c@0 { | |
62 | #address-cells = <1>; | |
63 | #size-cells = <0>; | |
64 | reg = <0x0>; | |
65 | ||
66 | ds3232: rtc@68 { | |
67 | compatible = "dallas,ds3232"; | |
68 | reg = <0x68>; | |
69 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; | |
70 | }; | |
71 | }; | |
72 | ||
73 | i2c@2 { | |
74 | #address-cells = <1>; | |
75 | #size-cells = <0>; | |
76 | reg = <0x2>; | |
77 | ||
78 | ina220@40 { | |
79 | compatible = "ti,ina220"; | |
80 | reg = <0x40>; | |
81 | shunt-resistor = <1000>; | |
82 | }; | |
83 | ||
84 | ina220@41 { | |
85 | compatible = "ti,ina220"; | |
86 | reg = <0x41>; | |
87 | shunt-resistor = <1000>; | |
88 | }; | |
89 | }; | |
90 | ||
91 | i2c@3 { | |
92 | #address-cells = <1>; | |
93 | #size-cells = <0>; | |
94 | reg = <0x3>; | |
95 | ||
96 | eeprom@56 { | |
97 | compatible = "atmel,24c512"; | |
98 | reg = <0x56>; | |
99 | }; | |
100 | ||
101 | eeprom@57 { | |
102 | compatible = "atmel,24c512"; | |
103 | reg = <0x57>; | |
104 | }; | |
105 | ||
106 | adt7461a@4c { | |
107 | compatible = "adi,adt7461a"; | |
108 | reg = <0x4c>; | |
109 | }; | |
110 | }; | |
111 | }; | |
112 | }; | |
113 | ||
114 | &ifc { | |
115 | #address-cells = <2>; | |
116 | #size-cells = <1>; | |
117 | /* NOR, NAND Flashes and FPGA on board */ | |
ce35fc17 | 118 | ranges = <0x0 0x0 0x60000000 0x08000000 |
119 | 0x2 0x0 0x7e800000 0x00010000 | |
120 | 0x3 0x0 0x7fb00000 0x00000100>; | |
ddf79f36 | 121 | status = "okay"; |
122 | ||
123 | nor@0,0 { | |
124 | #address-cells = <1>; | |
125 | #size-cells = <1>; | |
126 | compatible = "cfi-flash"; | |
127 | reg = <0x0 0x0 0x8000000>; | |
128 | bank-width = <2>; | |
129 | device-width = <1>; | |
130 | }; | |
131 | ||
132 | fpga: board-control@3,0 { | |
133 | #address-cells = <1>; | |
134 | #size-cells = <1>; | |
135 | compatible = "simple-bus"; | |
136 | reg = <0x3 0x0 0x0000100>; | |
137 | bank-width = <1>; | |
138 | device-width = <1>; | |
139 | ranges = <0 3 0 0x100>; | |
140 | ||
141 | mdio-mux-emi1 { | |
142 | compatible = "mdio-mux-mmioreg"; | |
143 | mdio-parent-bus = <&mdio0>; | |
144 | #address-cells = <1>; | |
145 | #size-cells = <0>; | |
146 | reg = <0x54 1>; /* BRDCFG4 */ | |
147 | mux-mask = <0xe0>; /* EMI1[2:0] */ | |
148 | ||
149 | /* Onboard PHYs */ | |
150 | ls1021amdio0: mdio@0 { | |
151 | reg = <0>; | |
152 | #address-cells = <1>; | |
153 | #size-cells = <0>; | |
154 | rgmii_phy1: ethernet-phy@1 { | |
155 | reg = <0x1>; | |
156 | }; | |
157 | }; | |
158 | ||
159 | ls1021amdio1: mdio@20 { | |
160 | reg = <0x20>; | |
161 | #address-cells = <1>; | |
162 | #size-cells = <0>; | |
163 | rgmii_phy2: ethernet-phy@2 { | |
164 | reg = <0x2>; | |
165 | }; | |
166 | }; | |
167 | ||
168 | ls1021amdio2: mdio@40 { | |
169 | reg = <0x40>; | |
170 | #address-cells = <1>; | |
171 | #size-cells = <0>; | |
172 | rgmii_phy3: ethernet-phy@3 { | |
173 | reg = <0x3>; | |
174 | }; | |
175 | }; | |
176 | ||
177 | ls1021amdio3: mdio@60 { | |
178 | reg = <0x60>; | |
179 | #address-cells = <1>; | |
180 | #size-cells = <0>; | |
181 | sgmii_phy1c: ethernet-phy@1c { | |
182 | reg = <0x1c>; | |
183 | }; | |
184 | }; | |
185 | ||
186 | ls1021amdio4: mdio@80 { | |
187 | reg = <0x80>; | |
188 | #address-cells = <1>; | |
189 | #size-cells = <0>; | |
190 | sgmii_phy1d: ethernet-phy@1d { | |
191 | reg = <0x1d>; | |
192 | }; | |
193 | }; | |
194 | }; | |
195 | }; | |
196 | }; | |
197 | ||
198 | &lpuart0 { | |
199 | status = "okay"; | |
200 | }; | |
201 | ||
202 | &mdio0 { | |
203 | tbi0: tbi-phy@8 { | |
204 | reg = <0x8>; | |
205 | device_type = "tbi-phy"; | |
206 | }; | |
207 | }; | |
208 | ||
209 | &uart0 { | |
210 | status = "okay"; | |
211 | }; | |
212 | ||
213 | &uart1 { | |
214 | status = "okay"; | |
215 | }; |