projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 1a87cc78 AF |
1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* | |
| 3 | * Copyright (c) 2019 BayLibre, SAS | |
| 4 | * Author: Neil Armstrong <narmstrong@baylibre.com> | |
| 5 | * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> | |
| 6 | */ | |
| 7 | ||
| 1a87cc78 | 8 | / { |
| 3a7d6a9c NA |
9 | model = "Khadas VIM3"; |
| 10 | ||
| 1a87cc78 AF |
11 | vddcpu_a: regulator-vddcpu-a { |
| 12 | /* | |
| 13 | * MP8756GD Regulator. | |
| 14 | */ | |
| 15 | compatible = "pwm-regulator"; | |
| 16 | ||
| 17 | regulator-name = "VDDCPU_A"; | |
| 18 | regulator-min-microvolt = <690000>; | |
| 19 | regulator-max-microvolt = <1050000>; | |
| 20 | ||
| 21 | vin-supply = <&dc_in>; | |
| 22 | ||
| 23 | pwms = <&pwm_ab 0 1250 0>; | |
| 24 | pwm-dutycycle-range = <100 0>; | |
| 25 | ||
| 26 | regulator-boot-on; | |
| 27 | regulator-always-on; | |
| 28 | }; | |
| 29 | ||
| 30 | vddcpu_b: regulator-vddcpu-b { | |
| 31 | /* | |
| 32 | * Silergy SY8030DEC Regulator. | |
| 33 | */ | |
| 34 | compatible = "pwm-regulator"; | |
| 35 | ||
| 36 | regulator-name = "VDDCPU_B"; | |
| 37 | regulator-min-microvolt = <690000>; | |
| 38 | regulator-max-microvolt = <1050000>; | |
| 39 | ||
| 40 | vin-supply = <&vsys_3v3>; | |
| 41 | ||
| 42 | pwms = <&pwm_AO_cd 1 1250 0>; | |
| 43 | pwm-dutycycle-range = <100 0>; | |
| 44 | ||
| 45 | regulator-boot-on; | |
| 46 | regulator-always-on; | |
| 47 | }; | |
| 1a87cc78 AF |
48 | }; |
| 49 | ||
| 50 | &cpu0 { | |
| 51 | cpu-supply = <&vddcpu_b>; | |
| 52 | operating-points-v2 = <&cpu_opp_table_0>; | |
| 53 | clocks = <&clkc CLKID_CPU_CLK>; | |
| 54 | clock-latency = <50000>; | |
| 55 | }; | |
| 56 | ||
| 57 | &cpu1 { | |
| 58 | cpu-supply = <&vddcpu_b>; | |
| 59 | operating-points-v2 = <&cpu_opp_table_0>; | |
| 60 | clocks = <&clkc CLKID_CPU_CLK>; | |
| 61 | clock-latency = <50000>; | |
| 62 | }; | |
| 63 | ||
| 64 | &cpu100 { | |
| 65 | cpu-supply = <&vddcpu_a>; | |
| 66 | operating-points-v2 = <&cpub_opp_table_1>; | |
| 67 | clocks = <&clkc CLKID_CPUB_CLK>; | |
| 68 | clock-latency = <50000>; | |
| 69 | }; | |
| 70 | ||
| 71 | &cpu101 { | |
| 72 | cpu-supply = <&vddcpu_a>; | |
| 73 | operating-points-v2 = <&cpub_opp_table_1>; | |
| 74 | clocks = <&clkc CLKID_CPUB_CLK>; | |
| 75 | clock-latency = <50000>; | |
| 76 | }; | |
| 77 | ||
| 78 | &cpu102 { | |
| 79 | cpu-supply = <&vddcpu_a>; | |
| 80 | operating-points-v2 = <&cpub_opp_table_1>; | |
| 81 | clocks = <&clkc CLKID_CPUB_CLK>; | |
| 82 | clock-latency = <50000>; | |
| 83 | }; | |
| 84 | ||
| 85 | &cpu103 { | |
| 86 | cpu-supply = <&vddcpu_a>; | |
| 87 | operating-points-v2 = <&cpub_opp_table_1>; | |
| 88 | clocks = <&clkc CLKID_CPUB_CLK>; | |
| 89 | clock-latency = <50000>; | |
| 90 | }; | |
| 91 | ||
| 1a87cc78 AF |
92 | &pwm_ab { |
| 93 | pinctrl-0 = <&pwm_a_e_pins>; | |
| 94 | pinctrl-names = "default"; | |
| 95 | clocks = <&xtal>; | |
| 96 | clock-names = "clkin0"; | |
| 97 | status = "okay"; | |
| 98 | }; | |
| 99 | ||
| 100 | &pwm_AO_cd { | |
| 101 | pinctrl-0 = <&pwm_ao_d_e_pins>; | |
| 102 | pinctrl-names = "default"; | |
| 103 | clocks = <&xtal>; | |
| 104 | clock-names = "clkin1"; | |
| 105 | status = "okay"; | |
| 106 | }; | |
| 107 |