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cac4d6a6 AF |
1 | /* |
2 | * Device Tree Source for OMAP34XX/OMAP36XX clock data | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | &cm_clocks { | |
bf1ddfc0 AF |
11 | security_l4_ick2: security_l4_ick2 { |
12 | #clock-cells = <0>; | |
13 | compatible = "fixed-factor-clock"; | |
14 | clocks = <&l4_ick>; | |
15 | clock-mult = <1>; | |
16 | clock-div = <1>; | |
17 | }; | |
cac4d6a6 | 18 | |
bf1ddfc0 AF |
19 | aes1_ick: aes1_ick@a14 { |
20 | #clock-cells = <0>; | |
21 | compatible = "ti,omap3-interface-clock"; | |
22 | clocks = <&security_l4_ick2>; | |
23 | ti,bit-shift = <3>; | |
24 | reg = <0x0a14>; | |
25 | }; | |
cac4d6a6 | 26 | |
bf1ddfc0 AF |
27 | rng_ick: rng_ick@a14 { |
28 | #clock-cells = <0>; | |
29 | compatible = "ti,omap3-interface-clock"; | |
30 | clocks = <&security_l4_ick2>; | |
31 | reg = <0x0a14>; | |
32 | ti,bit-shift = <2>; | |
33 | }; | |
cac4d6a6 | 34 | |
bf1ddfc0 AF |
35 | sha11_ick: sha11_ick@a14 { |
36 | #clock-cells = <0>; | |
37 | compatible = "ti,omap3-interface-clock"; | |
38 | clocks = <&security_l4_ick2>; | |
39 | reg = <0x0a14>; | |
40 | ti,bit-shift = <1>; | |
41 | }; | |
cac4d6a6 | 42 | |
bf1ddfc0 AF |
43 | des1_ick: des1_ick@a14 { |
44 | #clock-cells = <0>; | |
45 | compatible = "ti,omap3-interface-clock"; | |
46 | clocks = <&security_l4_ick2>; | |
47 | reg = <0x0a14>; | |
48 | ti,bit-shift = <0>; | |
49 | }; | |
cac4d6a6 | 50 | |
bf1ddfc0 AF |
51 | cam_mclk: cam_mclk@f00 { |
52 | #clock-cells = <0>; | |
53 | compatible = "ti,gate-clock"; | |
54 | clocks = <&dpll4_m5x2_ck>; | |
55 | ti,bit-shift = <0>; | |
56 | reg = <0x0f00>; | |
57 | ti,set-rate-parent; | |
58 | }; | |
cac4d6a6 | 59 | |
bf1ddfc0 AF |
60 | cam_ick: cam_ick@f10 { |
61 | #clock-cells = <0>; | |
62 | compatible = "ti,omap3-no-wait-interface-clock"; | |
63 | clocks = <&l4_ick>; | |
64 | reg = <0x0f10>; | |
65 | ti,bit-shift = <0>; | |
66 | }; | |
cac4d6a6 | 67 | |
bf1ddfc0 AF |
68 | csi2_96m_fck: csi2_96m_fck@f00 { |
69 | #clock-cells = <0>; | |
70 | compatible = "ti,gate-clock"; | |
71 | clocks = <&core_96m_fck>; | |
72 | reg = <0x0f00>; | |
73 | ti,bit-shift = <1>; | |
74 | }; | |
cac4d6a6 | 75 | |
bf1ddfc0 AF |
76 | security_l3_ick: security_l3_ick { |
77 | #clock-cells = <0>; | |
78 | compatible = "fixed-factor-clock"; | |
79 | clocks = <&l3_ick>; | |
80 | clock-mult = <1>; | |
81 | clock-div = <1>; | |
82 | }; | |
cac4d6a6 | 83 | |
bf1ddfc0 AF |
84 | pka_ick: pka_ick@a14 { |
85 | #clock-cells = <0>; | |
86 | compatible = "ti,omap3-interface-clock"; | |
87 | clocks = <&security_l3_ick>; | |
88 | reg = <0x0a14>; | |
89 | ti,bit-shift = <4>; | |
90 | }; | |
cac4d6a6 | 91 | |
bf1ddfc0 AF |
92 | icr_ick: icr_ick@a10 { |
93 | #clock-cells = <0>; | |
94 | compatible = "ti,omap3-interface-clock"; | |
95 | clocks = <&core_l4_ick>; | |
96 | reg = <0x0a10>; | |
97 | ti,bit-shift = <29>; | |
98 | }; | |
cac4d6a6 | 99 | |
bf1ddfc0 AF |
100 | des2_ick: des2_ick@a10 { |
101 | #clock-cells = <0>; | |
102 | compatible = "ti,omap3-interface-clock"; | |
103 | clocks = <&core_l4_ick>; | |
104 | reg = <0x0a10>; | |
105 | ti,bit-shift = <26>; | |
106 | }; | |
cac4d6a6 | 107 | |
bf1ddfc0 AF |
108 | mspro_ick: mspro_ick@a10 { |
109 | #clock-cells = <0>; | |
110 | compatible = "ti,omap3-interface-clock"; | |
111 | clocks = <&core_l4_ick>; | |
112 | reg = <0x0a10>; | |
113 | ti,bit-shift = <23>; | |
114 | }; | |
cac4d6a6 | 115 | |
bf1ddfc0 AF |
116 | mailboxes_ick: mailboxes_ick@a10 { |
117 | #clock-cells = <0>; | |
118 | compatible = "ti,omap3-interface-clock"; | |
119 | clocks = <&core_l4_ick>; | |
120 | reg = <0x0a10>; | |
121 | ti,bit-shift = <7>; | |
122 | }; | |
cac4d6a6 | 123 | |
bf1ddfc0 AF |
124 | ssi_l4_ick: ssi_l4_ick { |
125 | #clock-cells = <0>; | |
126 | compatible = "fixed-factor-clock"; | |
127 | clocks = <&l4_ick>; | |
128 | clock-mult = <1>; | |
129 | clock-div = <1>; | |
130 | }; | |
cac4d6a6 | 131 | |
bf1ddfc0 AF |
132 | sr1_fck: sr1_fck@c00 { |
133 | #clock-cells = <0>; | |
134 | compatible = "ti,wait-gate-clock"; | |
135 | clocks = <&sys_ck>; | |
136 | reg = <0x0c00>; | |
137 | ti,bit-shift = <6>; | |
138 | }; | |
cac4d6a6 | 139 | |
bf1ddfc0 AF |
140 | sr2_fck: sr2_fck@c00 { |
141 | #clock-cells = <0>; | |
142 | compatible = "ti,wait-gate-clock"; | |
143 | clocks = <&sys_ck>; | |
144 | reg = <0x0c00>; | |
145 | ti,bit-shift = <7>; | |
146 | }; | |
cac4d6a6 | 147 | |
bf1ddfc0 AF |
148 | sr_l4_ick: sr_l4_ick { |
149 | #clock-cells = <0>; | |
150 | compatible = "fixed-factor-clock"; | |
151 | clocks = <&l4_ick>; | |
152 | clock-mult = <1>; | |
153 | clock-div = <1>; | |
154 | }; | |
cac4d6a6 | 155 | |
bf1ddfc0 AF |
156 | dpll2_fck: dpll2_fck@40 { |
157 | #clock-cells = <0>; | |
158 | compatible = "ti,divider-clock"; | |
159 | clocks = <&core_ck>; | |
160 | ti,bit-shift = <19>; | |
161 | ti,max-div = <7>; | |
162 | reg = <0x0040>; | |
163 | ti,index-starts-at-one; | |
164 | }; | |
cac4d6a6 | 165 | |
bf1ddfc0 AF |
166 | dpll2_ck: dpll2_ck@4 { |
167 | #clock-cells = <0>; | |
168 | compatible = "ti,omap3-dpll-clock"; | |
169 | clocks = <&sys_ck>, <&dpll2_fck>; | |
170 | reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>; | |
171 | ti,low-power-stop; | |
172 | ti,lock; | |
173 | ti,low-power-bypass; | |
174 | }; | |
cac4d6a6 | 175 | |
bf1ddfc0 AF |
176 | dpll2_m2_ck: dpll2_m2_ck@44 { |
177 | #clock-cells = <0>; | |
178 | compatible = "ti,divider-clock"; | |
179 | clocks = <&dpll2_ck>; | |
180 | ti,max-div = <31>; | |
181 | reg = <0x0044>; | |
182 | ti,index-starts-at-one; | |
183 | }; | |
cac4d6a6 | 184 | |
bf1ddfc0 AF |
185 | iva2_ck: iva2_ck@0 { |
186 | #clock-cells = <0>; | |
187 | compatible = "ti,wait-gate-clock"; | |
188 | clocks = <&dpll2_m2_ck>; | |
189 | reg = <0x0000>; | |
190 | ti,bit-shift = <0>; | |
191 | }; | |
cac4d6a6 | 192 | |
bf1ddfc0 AF |
193 | modem_fck: modem_fck@a00 { |
194 | #clock-cells = <0>; | |
195 | compatible = "ti,omap3-interface-clock"; | |
196 | clocks = <&sys_ck>; | |
197 | reg = <0x0a00>; | |
198 | ti,bit-shift = <31>; | |
199 | }; | |
cac4d6a6 | 200 | |
bf1ddfc0 AF |
201 | sad2d_ick: sad2d_ick@a10 { |
202 | #clock-cells = <0>; | |
203 | compatible = "ti,omap3-interface-clock"; | |
204 | clocks = <&l3_ick>; | |
205 | reg = <0x0a10>; | |
206 | ti,bit-shift = <3>; | |
207 | }; | |
cac4d6a6 | 208 | |
bf1ddfc0 AF |
209 | mad2d_ick: mad2d_ick@a18 { |
210 | #clock-cells = <0>; | |
211 | compatible = "ti,omap3-interface-clock"; | |
212 | clocks = <&l3_ick>; | |
213 | reg = <0x0a18>; | |
214 | ti,bit-shift = <3>; | |
215 | }; | |
cac4d6a6 | 216 | |
bf1ddfc0 AF |
217 | mspro_fck: mspro_fck@a00 { |
218 | #clock-cells = <0>; | |
219 | compatible = "ti,wait-gate-clock"; | |
220 | clocks = <&core_96m_fck>; | |
221 | reg = <0x0a00>; | |
222 | ti,bit-shift = <23>; | |
223 | }; | |
cac4d6a6 AF |
224 | }; |
225 | ||
226 | &cm_clockdomains { | |
bf1ddfc0 AF |
227 | cam_clkdm: cam_clkdm { |
228 | compatible = "ti,clockdomain"; | |
229 | clocks = <&cam_ick>, <&csi2_96m_fck>; | |
230 | }; | |
cac4d6a6 | 231 | |
bf1ddfc0 AF |
232 | iva2_clkdm: iva2_clkdm { |
233 | compatible = "ti,clockdomain"; | |
234 | clocks = <&iva2_ck>; | |
235 | }; | |
cac4d6a6 | 236 | |
bf1ddfc0 AF |
237 | dpll2_clkdm: dpll2_clkdm { |
238 | compatible = "ti,clockdomain"; | |
239 | clocks = <&dpll2_ck>; | |
240 | }; | |
cac4d6a6 | 241 | |
bf1ddfc0 AF |
242 | wkup_clkdm: wkup_clkdm { |
243 | compatible = "ti,clockdomain"; | |
244 | clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, | |
245 | <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, | |
246 | <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>; | |
247 | }; | |
cac4d6a6 | 248 | |
bf1ddfc0 AF |
249 | d2d_clkdm: d2d_clkdm { |
250 | compatible = "ti,clockdomain"; | |
251 | clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>; | |
252 | }; | |
cac4d6a6 | 253 | |
bf1ddfc0 AF |
254 | core_l4_clkdm: core_l4_clkdm { |
255 | compatible = "ti,clockdomain"; | |
256 | clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, | |
257 | <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, | |
258 | <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, | |
259 | <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, | |
260 | <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, | |
261 | <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, | |
262 | <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, | |
263 | <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, | |
264 | <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>, | |
265 | <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>, | |
266 | <&mspro_fck>; | |
267 | }; | |
cac4d6a6 | 268 | }; |