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3d5f7c5a LFT |
1 | /* |
2 | * Copyright (C) 2016-2017 Intel Corporation | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0 X11 | |
5 | * | |
6 | *<auto-generated> | |
7 | * This code was generated by a tool based on | |
8 | * handoffs from both Qsys and Quartus. | |
9 | * | |
10 | * Changes to this file may be lost if | |
11 | * the code is regenerated. | |
12 | *</auto-generated> | |
13 | */ | |
14 | ||
15 | #include "socfpga_arria10.dtsi" | |
16 | ||
17 | / { | |
18 | model = "Altera SOCFPGA Arria 10"; | |
19 | compatible = "altr,socfpga-arria10", "altr,socfpga"; | |
20 | ||
21 | chosen { | |
22 | /* Bootloader setting: uboot.rbf_filename */ | |
23 | cff-file = "ghrd_10as066n2.periph.rbf"; | |
24 | early-release-fpga-config; | |
25 | }; | |
26 | ||
27 | soc { | |
28 | u-boot,dm-pre-reloc; | |
29 | clkmgr@ffd04000 { | |
30 | u-boot,dm-pre-reloc; | |
31 | clocks { | |
32 | u-boot,dm-pre-reloc; | |
33 | osc1 { | |
34 | u-boot,dm-pre-reloc; | |
35 | clock-frequency = <25000000>; | |
36 | clock-output-names = "altera_arria10_hps_eosc1-clk"; | |
37 | }; | |
38 | ||
39 | cb_intosc_ls_clk { | |
40 | u-boot,dm-pre-reloc; | |
41 | clock-frequency = <60000000>; | |
42 | clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk"; | |
43 | }; | |
44 | ||
45 | f2s_free_clk { | |
46 | u-boot,dm-pre-reloc; | |
47 | clock-frequency = <200000000>; | |
48 | clock-output-names = "altera_arria10_hps_f2h_free-clk"; | |
49 | }; | |
50 | ||
51 | main_pll { | |
52 | u-boot,dm-pre-reloc; | |
53 | /* | |
54 | * Address Block: soc_clock_manager_OCP_SLV. | |
55 | * i_clk_mgr_mainpllgrp | |
56 | */ | |
57 | altr,of_reg_value = < | |
58 | 0 /* Field: vco0.psrc */ | |
59 | 1 /* Field: vco1.denom */ | |
60 | 191 /* Field: vco1.numer */ | |
61 | 0 /* Field: mpuclk */ | |
62 | 0 /* Field: mpuclk.cnt */ | |
63 | 0 /* Field: mpuclk.src */ | |
64 | 0 /* Field: nocclk */ | |
65 | 0 /* Field: nocclk.cnt */ | |
66 | 0 /* Field: nocclk.src */ | |
67 | 900 /* Field: cntr2clk.cnt */ | |
68 | 900 /* Field: cntr3clk.cnt */ | |
69 | 900 /* Field: cntr4clk.cnt */ | |
70 | 900 /* Field: cntr5clk.cnt */ | |
71 | 900 /* Field: cntr6clk.cnt */ | |
72 | 900 /* Field: cntr7clk.cnt */ | |
73 | 0 /* Field: cntr7clk.src */ | |
74 | 900 /* Field: cntr8clk.cnt */ | |
75 | 900 /* Field: cntr9clk.cnt */ | |
76 | 0 /* Field: cntr9clk.src */ | |
77 | 900 /* Field: cntr15clk.cnt */ | |
78 | 0 /* Field: nocdiv.l4mainclk */ | |
79 | 0 /* Field: nocdiv.l4mpclk */ | |
80 | 2 /* Field: nocdiv.l4spclk */ | |
81 | 0 /* Field: nocdiv.csatclk */ | |
82 | 1 /* Field: nocdiv.cstraceclk */ | |
83 | 1 /* Field: nocdiv.cspdbgclk */ | |
84 | >; | |
85 | }; | |
86 | ||
87 | periph_pll { | |
88 | u-boot,dm-pre-reloc; | |
89 | /* | |
90 | * Address Block: soc_clock_manager_OCP_SLV. | |
91 | * i_clk_mgr_perpllgrp | |
92 | */ | |
93 | altr,of_reg_value = < | |
94 | 0 /* Field: vco0.psrc */ | |
95 | 1 /* Field: vco1.denom */ | |
96 | 159 /* Field: vco1.numer */ | |
97 | 7 /* Field: cntr2clk.cnt */ | |
98 | 1 /* Field: cntr2clk.src */ | |
99 | 900 /* Field: cntr3clk.cnt */ | |
100 | 1 /* Field: cntr3clk.src */ | |
101 | 19 /* Field: cntr4clk.cnt */ | |
102 | 1 /* Field: cntr4clk.src */ | |
103 | 499 /* Field: cntr5clk.cnt */ | |
104 | 1 /* Field: cntr5clk.src */ | |
105 | 9 /* Field: cntr6clk.cnt */ | |
106 | 1 /* Field: cntr6clk.src */ | |
107 | 900 /* Field: cntr7clk.cnt */ | |
108 | 900 /* Field: cntr8clk.cnt */ | |
109 | 0 /* Field: cntr8clk.src */ | |
110 | 900 /* Field: cntr9clk.cnt */ | |
111 | 0 /* Field: emacctl.emac0sel */ | |
112 | 0 /* Field: emacctl.emac1sel */ | |
113 | 0 /* Field: emacctl.emac2sel */ | |
114 | 32000 /* Field: gpiodiv.gpiodbclk */ | |
115 | >; | |
116 | }; | |
117 | ||
118 | altera { | |
119 | u-boot,dm-pre-reloc; | |
120 | /* | |
121 | * Address Block: soc_clock_manager_OCP_SLV. | |
122 | * i_clk_mgr_alteragrp | |
123 | */ | |
124 | altr,of_reg_value = < | |
125 | 0x0384000b /* Register: nocclk */ | |
126 | 0x03840001 /* Register: mpuclk */ | |
127 | >; | |
128 | }; | |
129 | }; | |
130 | }; | |
131 | ||
132 | /* | |
133 | * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver | |
134 | * Binding: pinmux | |
135 | */ | |
136 | i_io48_pin_mux: pinmux@0xffd07000 { | |
137 | u-boot,dm-pre-reloc; | |
138 | #address-cells = <1>; | |
139 | #size-cells = <1>; | |
140 | compatible = "pinctrl-single"; | |
141 | reg = <0xffd07000 0x00000800>; | |
142 | reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; | |
143 | ||
144 | /* | |
145 | * Address Block: soc_3v_io48_pin_mux_OCP_SLV. | |
146 | * i_io48_pin_mux_shared_3v_io_grp | |
147 | */ | |
148 | shared { | |
149 | u-boot,dm-pre-reloc; | |
150 | reg = <0xffd07000 0x00000200>; | |
151 | pinctrl-single,register-width = <32>; | |
152 | pinctrl-single,function-mask = <0x0000000f>; | |
153 | pinctrl-single,pins = | |
154 | /* Reg: pinmux_shared_io_q1_1 */ | |
155 | <0x00000000 0x00000008>, | |
156 | /* Reg: pinmux_shared_io_q1_2 */ | |
157 | <0x00000004 0x00000008>, | |
158 | /* Reg: pinmux_shared_io_q1_3 */ | |
159 | <0x00000008 0x00000008>, | |
160 | /* Reg: pinmux_shared_io_q1_4 */ | |
161 | <0x0000000c 0x00000008>, | |
162 | /* Reg: pinmux_shared_io_q1_5 */ | |
163 | <0x00000010 0x00000008>, | |
164 | /* Reg: pinmux_shared_io_q1_6 */ | |
165 | <0x00000014 0x00000008>, | |
166 | /* Reg: pinmux_shared_io_q1_7 */ | |
167 | <0x00000018 0x00000008>, | |
168 | /* Reg: pinmux_shared_io_q1_8 */ | |
169 | <0x0000001c 0x00000008>, | |
170 | /* Reg: pinmux_shared_io_q1_9 */ | |
171 | <0x00000020 0x00000008>, | |
172 | /* Reg: pinmux_shared_io_q1_10 */ | |
173 | <0x00000024 0x00000008>, | |
174 | /* Reg: pinmux_shared_io_q1_11 */ | |
175 | <0x00000028 0x00000008>, | |
176 | /* Reg: pinmux_shared_io_q1_12 */ | |
177 | <0x0000002c 0x00000008>, | |
178 | /* Reg: pinmux_shared_io_q2_1 */ | |
179 | <0x00000030 0x00000004>, | |
180 | /* Reg: pinmux_shared_io_q2_2 */ | |
181 | <0x00000034 0x00000004>, | |
182 | /* Reg: pinmux_shared_io_q2_3 */ | |
183 | <0x00000038 0x00000004>, | |
184 | /* Reg: pinmux_shared_io_q2_4 */ | |
185 | <0x0000003c 0x00000004>, | |
186 | /* Reg: pinmux_shared_io_q2_5 */ | |
187 | <0x00000040 0x00000004>, | |
188 | /* Reg: pinmux_shared_io_q2_6 */ | |
189 | <0x00000044 0x00000004>, | |
190 | /* Reg: pinmux_shared_io_q2_7 */ | |
191 | <0x00000048 0x00000004>, | |
192 | /* Reg: pinmux_shared_io_q2_8 */ | |
193 | <0x0000004c 0x00000004>, | |
194 | /* Reg: pinmux_shared_io_q2_9 */ | |
195 | <0x00000050 0x00000004>, | |
196 | /* Reg: pinmux_shared_io_q2_10 */ | |
197 | <0x00000054 0x00000004>, | |
198 | /* Reg: pinmux_shared_io_q2_11 */ | |
199 | <0x00000058 0x00000004>, | |
200 | /* Reg: pinmux_shared_io_q2_12 */ | |
201 | <0x0000005c 0x00000004>, | |
202 | /* Reg: pinmux_shared_io_q3_1 */ | |
203 | <0x00000060 0x00000003>, | |
204 | /* Reg: pinmux_shared_io_q3_2 */ | |
205 | <0x00000064 0x00000003>, | |
206 | /* Reg: pinmux_shared_io_q3_3 */ | |
207 | <0x00000068 0x00000003>, | |
208 | /* Reg: pinmux_shared_io_q3_4 */ | |
209 | <0x0000006c 0x00000003>, | |
210 | /* Reg: pinmux_shared_io_q3_5 */ | |
211 | <0x00000070 0x00000003>, | |
212 | /* Reg: pinmux_shared_io_q3_6 */ | |
213 | <0x00000074 0x0000000f>, | |
214 | /* Reg: pinmux_shared_io_q3_7 */ | |
215 | <0x00000078 0x0000000a>, | |
216 | /* Reg: pinmux_shared_io_q3_8 */ | |
217 | <0x0000007c 0x0000000a>, | |
218 | /* Reg: pinmux_shared_io_q3_9 */ | |
219 | <0x00000080 0x0000000a>, | |
220 | /* Reg: pinmux_shared_io_q3_10 */ | |
221 | <0x00000084 0x0000000a>, | |
222 | /* Reg: pinmux_shared_io_q3_11 */ | |
223 | <0x00000088 0x00000001>, | |
224 | /* Reg: pinmux_shared_io_q3_12 */ | |
225 | <0x0000008c 0x00000001>, | |
226 | /* Reg: pinmux_shared_io_q4_1 */ | |
227 | <0x00000090 0x00000000>, | |
228 | /* Reg: pinmux_shared_io_q4_2 */ | |
229 | <0x00000094 0x00000000>, | |
230 | /* Reg: pinmux_shared_io_q4_3 */ | |
231 | <0x00000098 0x0000000f>, | |
232 | /* Reg: pinmux_shared_io_q4_4 */ | |
233 | <0x0000009c 0x0000000c>, | |
234 | /* Reg: pinmux_shared_io_q4_5 */ | |
235 | <0x000000a0 0x0000000f>, | |
236 | /* Reg: pinmux_shared_io_q4_6 */ | |
237 | <0x000000a4 0x0000000f>, | |
238 | /* Reg: pinmux_shared_io_q4_7 */ | |
239 | <0x000000a8 0x0000000a>, | |
240 | /* Reg: pinmux_shared_io_q4_8 */ | |
241 | <0x000000ac 0x0000000a>, | |
242 | /* Reg: pinmux_shared_io_q4_9 */ | |
243 | <0x000000b0 0x0000000c>, | |
244 | /* Reg: pinmux_shared_io_q4_10 */ | |
245 | <0x000000b4 0x0000000c>, | |
246 | /* Reg: pinmux_shared_io_q4_11 */ | |
247 | <0x000000b8 0x0000000c>, | |
248 | /* Reg: pinmux_shared_io_q4_12 */ | |
249 | <0x000000bc 0x0000000c>; | |
250 | }; | |
251 | ||
252 | /* | |
253 | * Address Block: soc_3v_io48_pin_mux_OCP_SLV. | |
254 | * i_io48_pin_mux_dedicated_io_grp | |
255 | */ | |
256 | dedicated { | |
257 | u-boot,dm-pre-reloc; | |
258 | reg = <0xffd07200 0x00000200>; | |
259 | pinctrl-single,register-width = <32>; | |
260 | pinctrl-single,function-mask = <0x0000000f>; | |
261 | pinctrl-single,pins = | |
262 | /* Reg: pinmux_dedicated_io_4 */ | |
263 | <0x0000000c 0x00000008>, | |
264 | /* Reg: pinmux_dedicated_io_5 */ | |
265 | <0x00000010 0x00000008>, | |
266 | /* Reg: pinmux_dedicated_io_6 */ | |
267 | <0x00000014 0x00000008>, | |
268 | /* Regi: pinmux_dedicated_io_7 */ | |
269 | <0x00000018 0x00000008>, | |
270 | /* Reg: pinmux_dedicated_io_8 */ | |
271 | <0x0000001c 0x00000008>, | |
272 | /* Reg: pinmux_dedicated_io_9 */ | |
273 | <0x00000020 0x00000008>, | |
274 | /* Reg: pinmux_dedicated_io_10 */ | |
275 | <0x00000024 0x0000000a>, | |
276 | /* Reg: pinmux_dedicated_io_11 */ | |
277 | <0x00000028 0x0000000a>, | |
278 | /* Reg: pinmux_dedicated_io_12 */ | |
279 | <0x0000002c 0x00000008>, | |
280 | /* Reg: pinmux_dedicated_io_13 */ | |
281 | <0x00000030 0x00000008>, | |
282 | /* Reg: pinmux_dedicated_io_14 */ | |
283 | <0x00000034 0x00000008>, | |
284 | /* Reg: pinmux_dedicated_io_15 */ | |
285 | <0x00000038 0x00000008>, | |
286 | /* Reg: pinmux_dedicated_io_16 */ | |
287 | <0x0000003c 0x0000000d>, | |
288 | /* Reg: pinmux_dedicated_io_17 */ | |
289 | <0x00000040 0x0000000d>; | |
290 | }; | |
291 | ||
292 | /* | |
293 | * Address Block: soc_3v_io48_pin_mux_OCP_SLV. | |
294 | * i_io48_pin_mux_dedicated_io_grp | |
295 | */ | |
296 | dedicated_cfg { | |
297 | u-boot,dm-pre-reloc; | |
298 | reg = <0xffd07200 0x00000200>; | |
299 | pinctrl-single,register-width = <32>; | |
300 | pinctrl-single,function-mask = <0x003f3f3f>; | |
301 | pinctrl-single,pins = | |
302 | /* Reg: cfg_dedicated_io_bank */ | |
303 | <0x00000100 0x00000101>, | |
304 | /* Reg: cfg_dedicated_io_1 */ | |
305 | <0x00000104 0x000b080a>, | |
306 | /* Reg: cfg_dedicated_io_2 */ | |
307 | <0x00000108 0x000b080a>, | |
308 | /* Reg: cfg_dedicated_io_3 */ | |
309 | <0x0000010c 0x000b080a>, | |
310 | /* Reg: cfg_dedicated_io_4 */ | |
311 | <0x00000110 0x000a282a>, | |
312 | /* Reg: cfg_dedicated_io_5 */ | |
313 | <0x00000114 0x000a282a>, | |
314 | /* Reg: cfg_dedicated_io_6 */ | |
315 | <0x00000118 0x0008282a>, | |
316 | /* Reg: cfg_dedicated_io_7 */ | |
317 | <0x0000011c 0x000a282a>, | |
318 | /* Reg: cfg_dedicated_io_8 */ | |
319 | <0x00000120 0x000a282a>, | |
320 | /* Reg: cfg_dedicated_io_9 */ | |
321 | <0x00000124 0x000a282a>, | |
322 | /* Reg: cfg_dedicated_io_10 */ | |
323 | <0x00000128 0x00090000>, | |
324 | /* Reg: cfg_dedicated_io_11 */ | |
325 | <0x0000012c 0x00090000>, | |
326 | /* Reg: cfg_dedicated_io_12 */ | |
327 | <0x00000130 0x000b282a>, | |
328 | /* Reg: cfg_dedicated_io_13 */ | |
329 | <0x00000134 0x000b282a>, | |
330 | /* Reg: cfg_dedicated_io_14 */ | |
331 | <0x00000138 0x000b282a>, | |
332 | /* Reg: cfg_dedicated_io_15 */ | |
333 | <0x0000013c 0x000b282a>, | |
334 | /* Reg: cfg_dedicated_io_16 */ | |
335 | <0x00000140 0x0008282a>, | |
336 | /* Reg: cfg_dedicated_io_17 */ | |
337 | <0x00000144 0x000a282a>; | |
338 | }; | |
339 | ||
340 | /* | |
341 | * Address Block: soc_3v_io48_pin_mux_OCP_SLV. | |
342 | * i_io48_pin_mux_fpga_interface_grp | |
343 | */ | |
344 | fpga { | |
345 | u-boot,dm-pre-reloc; | |
346 | reg = <0xffd07400 0x00000100>; | |
347 | pinctrl-single,register-width = <32>; | |
348 | pinctrl-single,function-mask = <0x00000001>; | |
349 | pinctrl-single,pins = | |
350 | /* Reg: pinmux_emac0_usefpga */ | |
351 | <0x00000000 0x00000000>, | |
352 | /* Reg: pinmux_emac1_usefpga */ | |
353 | <0x00000004 0x00000000>, | |
354 | /* Reg: pinmux_emac2_usefpga */ | |
355 | <0x00000008 0x00000000>, | |
356 | /* Reg: pinmux_i2c0_usefpga */ | |
357 | <0x0000000c 0x00000000>, | |
358 | /* Reg: pinmux_i2c1_usefpga */ | |
359 | <0x00000010 0x00000000>, | |
360 | /* Reg: pinmux_i2c_emac0_usefpga */ | |
361 | <0x00000014 0x00000000>, | |
362 | /* Reg: pinmux_i2c_emac1_usefpga */ | |
363 | <0x00000018 0x00000000>, | |
364 | /* Reg: pinmux_i2c_emac2_usefpga */ | |
365 | <0x0000001c 0x00000000>, | |
366 | /* Reg: pinmux_nand_usefpga */ | |
367 | <0x00000020 0x00000000>, | |
368 | /* Reg: pinmux_qspi_usefpga */ | |
369 | <0x00000024 0x00000000>, | |
370 | /* Reg: pinmux_sdmmc_usefpga */ | |
371 | <0x00000028 0x00000000>, | |
372 | /* Reg: pinmux_spim0_usefpga */ | |
373 | <0x0000002c 0x00000000>, | |
374 | /* Reg: pinmux_spim1_usefpga */ | |
375 | <0x00000030 0x00000000>, | |
376 | /* Reg: pinmux_spis0_usefpga */ | |
377 | <0x00000034 0x00000000>, | |
378 | /* Reg: pinmux_spis1_usefpga */ | |
379 | <0x00000038 0x00000000>, | |
380 | /* Reg: pinmux_uart0_usefpga */ | |
381 | <0x0000003c 0x00000000>, | |
382 | /* Reg: pinmux_uart1_usefpga */ | |
383 | <0x00000040 0x00000000>; | |
384 | }; | |
385 | }; | |
386 | ||
387 | i_noc: noc@0xffd10000 { | |
388 | u-boot,dm-pre-reloc; | |
389 | compatible = "altr,socfpga-a10-noc"; | |
390 | reg = <0xffd10000 0x00008000>; | |
391 | reg-names = "mpu_m0"; | |
392 | ||
393 | firewall { | |
394 | u-boot,dm-pre-reloc; | |
395 | /* | |
396 | * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. | |
397 | * I_NOC.mpu_m0. | |
398 | * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. | |
399 | * mpuregion0addr.base | |
400 | * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. | |
401 | * I_NOC.mpu_m0. | |
402 | * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. | |
403 | * mpuregion0addr.limit | |
404 | */ | |
405 | altr,mpu0 = <0x00000000 0x0000ffff>; | |
406 | /* | |
407 | * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. | |
408 | * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr. | |
409 | * hpsregion0addr.base | |
410 | * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. | |
411 | * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr. | |
412 | * hpsregion0addr.limit | |
413 | */ | |
414 | altr,l3-0 = <0x00000000 0x0000ffff>; | |
415 | /* | |
416 | * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. | |
417 | * I_NOC.mpu_m0. | |
418 | * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. | |
419 | * fpga2sdram0region0addr.base | |
420 | * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. | |
421 | * I_NOC.mpu_m0. | |
422 | * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. | |
423 | * fpga2sdram0region0addr.limit | |
424 | */ | |
425 | altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>; | |
426 | /* | |
427 | * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. | |
428 | * I_NOC.mpu_m0. | |
429 | * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. | |
430 | * fpga2sdram1region0addr.base | |
431 | * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. | |
432 | * I_NOC.mpu_m0. | |
433 | * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. | |
434 | * fpga2sdram1region0addr.limit | |
435 | */ | |
436 | altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>; | |
437 | /* | |
438 | * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. | |
439 | * I_NOC.mpu_m0. | |
440 | * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. | |
441 | * fpga2sdram2region0addr.base | |
442 | * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. | |
443 | * I_NOC.mpu_m0. | |
444 | * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. | |
445 | * fpga2sdram2region0addr.limit | |
446 | */ | |
447 | altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>; | |
448 | }; | |
449 | }; | |
450 | ||
451 | hps_fpgabridge0: fpgabridge@0 { | |
452 | compatible = "altr,socfpga-hps2fpga-bridge"; | |
453 | altr,init-val = <1>; | |
454 | }; | |
455 | ||
456 | hps_fpgabridge1: fpgabridge@1 { | |
457 | compatible = "altr,socfpga-lwhps2fpga-bridge"; | |
458 | altr,init-val = <1>; | |
459 | }; | |
460 | ||
461 | hps_fpgabridge2: fpgabridge@2 { | |
462 | compatible = "altr,socfpga-fpga2hps-bridge"; | |
463 | altr,init-val = <1>; | |
464 | }; | |
465 | ||
466 | hps_fpgabridge3: fpgabridge@3 { | |
467 | compatible = "altr,socfpga-fpga2sdram0-bridge"; | |
468 | altr,init-val = <1>; | |
469 | }; | |
470 | ||
471 | hps_fpgabridge4: fpgabridge@4 { | |
472 | compatible = "altr,socfpga-fpga2sdram1-bridge"; | |
473 | altr,init-val = <0>; | |
474 | }; | |
475 | ||
476 | hps_fpgabridge5: fpgabridge@5 { | |
477 | compatible = "altr,socfpga-fpga2sdram2-bridge"; | |
478 | altr,init-val = <1>; | |
479 | }; | |
480 | }; | |
481 | }; |