[people/ms/u-boot.git] / arch / arm / dts / socfpga_cyclone5.dtsi

/*
 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/dts-v1/;
/* First 4KB has trampoline code for secondary cores. */
/memreserve/ 0x00000000 0x0001000;
#include "socfpga.dtsi"

/ {
	soc {
		clkmgr@ffd04000 {
			clocks {
				osc1 {
					clock-frequency = <25000000>;
				};
			};
		};

		mmc0: dwmmc0@ff704000 {
			num-slots = <1>;
			broken-cd;
			bus-width = <4>;
			cap-mmc-highspeed;
			cap-sd-highspeed;
		};

		ethernet@ff702000 {
			phy-mode = "rgmii";
			phy-addr = <0xffffffff>; /* probe for phy addr */
			status = "okay";
		};

		sysmgr@ffd08000 {
			cpu1-start-addr = <0xffd080c4>;
		};
	};
};
Commit	Line	Data
51c580c6 SR	1	/*
	2	* Copyright (C) 2012 Altera Corporation <www.altera.com>
	3	*
5bf1f1ed	4	* SPDX-License-Identifier: GPL-2.0+
51c580c6 SR	5	*/
	6
	7	/dts-v1/;
	8	/* First 4KB has trampoline code for secondary cores. */
	9	/memreserve/ 0x00000000 0x0001000;
	10	#include "socfpga.dtsi"
	11
	12	/ {
	13	soc {
	14	clkmgr@ffd04000 {
	15	clocks {
	16	osc1 {
	17	clock-frequency = <25000000>;
	18	};
	19	};
	20	};
	21
	22	mmc0: dwmmc0@ff704000 {
	23	num-slots = <1>;
	24	broken-cd;
	25	bus-width = <4>;
	26	cap-mmc-highspeed;
	27	cap-sd-highspeed;
	28	};
	29
	30	ethernet@ff702000 {
	31	phy-mode = "rgmii";
	32	phy-addr = <0xffffffff>; /* probe for phy addr */
	33	status = "okay";
	34	};
	35
	36	sysmgr@ffd08000 {
	37	cpu1-start-addr = <0xffd080c4>;
	38	};
	39	};
	40	};