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da63df7c MV |
1 | /* |
2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include "socfpga_cyclone5.dtsi" | |
8 | ||
9 | / { | |
10 | model = "Altera SOCFPGA Cyclone V SoC Development Kit"; | |
11 | compatible = "altr,socfpga-cyclone5", "altr,socfpga"; | |
12 | ||
13 | chosen { | |
14 | bootargs = "console=ttyS0,115200"; | |
15 | }; | |
16 | ||
17 | memory { | |
18 | name = "memory"; | |
19 | device_type = "memory"; | |
20 | reg = <0x0 0x40000000>; /* 1GB */ | |
21 | }; | |
22 | ||
23 | aliases { | |
24 | /* this allow the ethaddr uboot environmnet variable contents | |
25 | * to be added to the gmac1 device tree blob. | |
26 | */ | |
27 | ethernet0 = &gmac1; | |
daa23f51 PM |
28 | |
29 | spi0 = "/spi@ff705000"; /* QSPI */ | |
30 | spi1 = "/spi@fff00000"; | |
31 | spi2 = "/spi@fff01000"; | |
da63df7c MV |
32 | }; |
33 | ||
34 | regulator_3_3v: 3-3-v-regulator { | |
35 | compatible = "regulator-fixed"; | |
36 | regulator-name = "3.3V"; | |
37 | regulator-min-microvolt = <3300000>; | |
38 | regulator-max-microvolt = <3300000>; | |
39 | }; | |
40 | }; | |
41 | ||
42 | &gmac1 { | |
43 | status = "okay"; | |
44 | phy-mode = "rgmii"; | |
45 | ||
46 | rxd0-skew-ps = <0>; | |
47 | rxd1-skew-ps = <0>; | |
48 | rxd2-skew-ps = <0>; | |
49 | rxd3-skew-ps = <0>; | |
50 | txen-skew-ps = <0>; | |
51 | txc-skew-ps = <2600>; | |
52 | rxdv-skew-ps = <0>; | |
53 | rxc-skew-ps = <2000>; | |
54 | }; | |
55 | ||
56 | &gpio1 { | |
57 | status = "okay"; | |
58 | }; | |
59 | ||
60 | &i2c0 { | |
61 | status = "okay"; | |
62 | ||
63 | eeprom@51 { | |
64 | compatible = "atmel,24c32"; | |
65 | reg = <0x51>; | |
66 | pagesize = <32>; | |
67 | }; | |
68 | ||
69 | rtc@68 { | |
70 | compatible = "dallas,ds1339"; | |
71 | reg = <0x68>; | |
72 | }; | |
73 | }; | |
74 | ||
75 | &mmc0 { | |
76 | cd-gpios = <&portb 18 0>; | |
77 | vmmc-supply = <®ulator_3_3v>; | |
78 | vqmmc-supply = <®ulator_3_3v>; | |
79 | }; | |
80 | ||
81 | &usb1 { | |
82 | status = "okay"; | |
83 | }; | |
daa23f51 PM |
84 | |
85 | &qspi { | |
86 | status = "okay"; | |
87 | ||
88 | flash0: n25q00@0 { | |
89 | #address-cells = <1>; | |
90 | #size-cells = <1>; | |
91 | compatible = "n25q00"; | |
92 | reg = <0>; /* chip select */ | |
93 | spi-max-frequency = <50000000>; | |
94 | m25p,fast-read; | |
95 | page-size = <256>; | |
96 | block-size = <16>; /* 2^16, 64KB */ | |
97 | read-delay = <4>; /* delay value in read data capture register */ | |
98 | tshsl-ns = <50>; | |
99 | tsd2d-ns = <50>; | |
100 | tchsh-ns = <4>; | |
101 | tslch-ns = <4>; | |
102 | }; | |
103 | }; |