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ARM: zynq: rename CONFIG_ZYNQ to CONFIG_ARCH_ZYNQ
[people/ms/u-boot.git] / arch / arm / dts / socfpga_cyclone5_socrates.dts
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1/*
2 * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
3 *
5bf1f1ed 4 * SPDX-License-Identifier: GPL-2.0+
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5 */
6
7#include "socfpga_cyclone5.dtsi"
8
9/ {
10 model = "EBV SOCrates";
11 compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
12
13 chosen {
14 bootargs = "console=ttyS0,115200";
15 };
16
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17 aliases {
18 spi0 = "/spi@ff705000"; /* QSPI */
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19 spi1 = "/spi@fff00000";
20 spi2 = "/spi@fff01000";
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21 };
22
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23 memory {
24 name = "memory";
25 device_type = "memory";
26 reg = <0x0 0x40000000>; /* 1GB */
27 };
28};
29
30&gmac1 {
31 status = "okay";
32};
33
34&i2c0 {
35 status = "okay";
36
37 rtc: rtc@68 {
38 compatible = "stm,m41t82";
39 reg = <0x68>;
40 };
41};
42
43&mmc {
44 status = "okay";
45};
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46
47&qspi {
48 status = "okay";
49
50 flash0: n25q00@0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "n25q00";
54 reg = <0>; /* chip select */
55 spi-max-frequency = <50000000>;
56 m25p,fast-read;
57 page-size = <256>;
58 block-size = <16>; /* 2^16, 64KB */
59 read-delay = <4>; /* delay value in read data capture register */
60 tshsl-ns = <50>;
61 tsd2d-ns = <50>;
62 tchsh-ns = <4>;
63 tslch-ns = <4>;
64 };
65};