projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 2d58dddf PC |
1 | /* |
| 2 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved | |
| 3 | * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. | |
| 4 | * | |
| 5 | * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | */ | |
| 7 | ||
| 8 | #include <dt-bindings/memory/stm32-sdram.h> | |
| 9 | /{ | |
| 10 | clocks { | |
| 11 | u-boot,dm-pre-reloc; | |
| 12 | }; | |
| 13 | ||
| 14 | aliases { | |
| 15 | /* Aliases for gpios so as to use sequence */ | |
| 16 | gpio0 = &gpioa; | |
| 17 | gpio1 = &gpiob; | |
| 18 | gpio2 = &gpioc; | |
| 19 | gpio3 = &gpiod; | |
| 20 | gpio4 = &gpioe; | |
| 21 | gpio5 = &gpiof; | |
| 22 | gpio6 = &gpiog; | |
| 23 | gpio7 = &gpioh; | |
| 24 | gpio8 = &gpioi; | |
| 25 | gpio9 = &gpioj; | |
| 26 | gpio10 = &gpiok; | |
| 27 | }; | |
| 28 | ||
| 29 | soc { | |
| 30 | u-boot,dm-pre-reloc; | |
| 31 | pin-controller { | |
| 32 | u-boot,dm-pre-reloc; | |
| 33 | }; | |
| 34 | ||
| 35 | fmc: fmc@A0000000 { | |
| 36 | compatible = "st,stm32-fmc"; | |
| 37 | reg = <0xA0000000 0x1000>; | |
| 38 | clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; | |
| 39 | st,syscfg = <&syscfg>; | |
| 40 | pinctrl-0 = <&fmc_pins_d32>; | |
| 41 | pinctrl-names = "default"; | |
| 42 | st,mem_remap = <4>; | |
| 43 | u-boot,dm-pre-reloc; | |
| 44 | ||
| 45 | /* | |
| 46 | * Memory configuration from sdram | |
| 47 | * MICRON MT48LC4M32B2B5-7 | |
| 48 | */ | |
| 49 | bank0: bank@0 { | |
| 50 | st,sdram-control = /bits/ 8 <NO_COL_9 | |
| 51 | NO_ROW_12 | |
| 52 | MWIDTH_32 | |
| 53 | BANKS_4 | |
| 54 | CAS_3 | |
| 55 | SDCLK_2 | |
| 56 | RD_BURST_EN | |
| 57 | RD_PIPE_DL_0>; | |
| 58 | st,sdram-timing = /bits/ 8 <TMRD_2 | |
| 59 | TXSR_6 | |
| 60 | TRAS_4 | |
| 61 | TRC_6 | |
| 62 | TWR_2 | |
| 63 | TRP_2 | |
| 64 | TRCD_2>; | |
| 65 | st,sdram-refcount = < 2812 >; | |
| 66 | }; | |
| 67 | }; | |
| 68 | }; | |
| 69 | }; | |
| 70 | ||
| 71 | &clk_hse { | |
| 72 | u-boot,dm-pre-reloc; | |
| 73 | }; | |
| 74 | ||
| 75 | &clk_lse { | |
| 76 | u-boot,dm-pre-reloc; | |
| 77 | }; | |
| 78 | ||
| 79 | &clk_i2s_ckin { | |
| 80 | u-boot,dm-pre-reloc; | |
| 81 | }; | |
| 82 | ||
| 83 | &pwrcfg { | |
| 84 | u-boot,dm-pre-reloc; | |
| 85 | }; | |
| 86 | ||
| 87 | &syscfg { | |
| 88 | u-boot,dm-pre-reloc; | |
| 89 | }; | |
| 90 | ||
| 91 | &rcc { | |
| 92 | u-boot,dm-pre-reloc; | |
| 93 | }; | |
| 94 | ||
| 95 | &gpioa { | |
| 96 | compatible = "st,stm32-gpio"; | |
| 97 | u-boot,dm-pre-reloc; | |
| 98 | }; | |
| 99 | ||
| 100 | &gpiob { | |
| 101 | compatible = "st,stm32-gpio"; | |
| 102 | u-boot,dm-pre-reloc; | |
| 103 | }; | |
| 104 | ||
| 105 | &gpioc { | |
| 106 | compatible = "st,stm32-gpio"; | |
| 107 | u-boot,dm-pre-reloc; | |
| 108 | }; | |
| 109 | ||
| 110 | &gpiod { | |
| 111 | compatible = "st,stm32-gpio"; | |
| 112 | u-boot,dm-pre-reloc; | |
| 113 | }; | |
| 114 | ||
| 115 | &gpioe { | |
| 116 | compatible = "st,stm32-gpio"; | |
| 117 | u-boot,dm-pre-reloc; | |
| 118 | }; | |
| 119 | ||
| 120 | &gpiof { | |
| 121 | compatible = "st,stm32-gpio"; | |
| 122 | u-boot,dm-pre-reloc; | |
| 123 | }; | |
| 124 | ||
| 125 | &gpiog { | |
| 126 | compatible = "st,stm32-gpio"; | |
| 127 | u-boot,dm-pre-reloc; | |
| 128 | }; | |
| 129 | ||
| 130 | &gpioh { | |
| 131 | compatible = "st,stm32-gpio"; | |
| 132 | u-boot,dm-pre-reloc; | |
| 133 | }; | |
| 134 | ||
| 135 | &gpioi { | |
| 136 | compatible = "st,stm32-gpio"; | |
| 137 | u-boot,dm-pre-reloc; | |
| 138 | }; | |
| 139 | ||
| 140 | &gpioj { | |
| 141 | compatible = "st,stm32-gpio"; | |
| 142 | u-boot,dm-pre-reloc; | |
| 143 | }; | |
| 144 | ||
| 145 | &gpiok { | |
| 146 | compatible = "st,stm32-gpio"; | |
| 147 | u-boot,dm-pre-reloc; | |
| 148 | }; | |
| 149 | ||
| 150 | &pinctrl { | |
| 151 | usart1_pins_a: usart1@0 { | |
| 152 | u-boot,dm-pre-reloc; | |
| 153 | pins1 { | |
| 154 | u-boot,dm-pre-reloc; | |
| 155 | }; | |
| 156 | pins2 { | |
| 157 | u-boot,dm-pre-reloc; | |
| 158 | }; | |
| 159 | }; | |
| 160 | ||
| 161 | fmc_pins_d32: fmc_d32@0 { | |
| 162 | u-boot,dm-pre-reloc; | |
| 163 | pins | |
| 164 | { | |
| 165 | pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */ | |
| 166 | <STM32_PINMUX('I', 9, AF12)>, /* D30 */ | |
| 167 | <STM32_PINMUX('I', 7, AF12)>, /* D29 */ | |
| 168 | <STM32_PINMUX('I', 6, AF12)>, /* D28 */ | |
| 169 | <STM32_PINMUX('I', 3, AF12)>, /* D27 */ | |
| 170 | <STM32_PINMUX('I', 2, AF12)>, /* D26 */ | |
| 171 | <STM32_PINMUX('I', 1, AF12)>, /* D25 */ | |
| 172 | <STM32_PINMUX('I', 0, AF12)>, /* D24 */ | |
| 173 | <STM32_PINMUX('H',15, AF12)>, /* D23 */ | |
| 174 | <STM32_PINMUX('H',14, AF12)>, /* D22 */ | |
| 175 | <STM32_PINMUX('H',13, AF12)>, /* D21 */ | |
| 176 | <STM32_PINMUX('H',12, AF12)>, /* D20 */ | |
| 177 | <STM32_PINMUX('H',11, AF12)>, /* D19 */ | |
| 178 | <STM32_PINMUX('H',10, AF12)>, /* D18 */ | |
| 179 | <STM32_PINMUX('H', 9, AF12)>, /* D17 */ | |
| 180 | <STM32_PINMUX('H', 8, AF12)>, /* D16 */ | |
| 181 | ||
| 182 | <STM32_PINMUX('D',10, AF12)>, /* D15 */ | |
| 183 | <STM32_PINMUX('D', 9, AF12)>, /* D14 */ | |
| 184 | <STM32_PINMUX('D', 8, AF12)>, /* D13 */ | |
| 185 | <STM32_PINMUX('E',15, AF12)>, /* D12 */ | |
| 186 | <STM32_PINMUX('E',14, AF12)>, /* D11 */ | |
| 187 | <STM32_PINMUX('E',13, AF12)>, /* D10 */ | |
| 188 | <STM32_PINMUX('E',12, AF12)>, /* D09 */ | |
| 189 | <STM32_PINMUX('E',11, AF12)>, /* D08 */ | |
| 190 | <STM32_PINMUX('E',10, AF12)>, /* D07 */ | |
| 191 | <STM32_PINMUX('E', 9, AF12)>, /* D06 */ | |
| 192 | <STM32_PINMUX('E', 8, AF12)>, /* D05 */ | |
| 193 | <STM32_PINMUX('E', 7, AF12)>, /* D04 */ | |
| 194 | <STM32_PINMUX('D', 1, AF12)>, /* D03 */ | |
| 195 | <STM32_PINMUX('D', 0, AF12)>, /* D02 */ | |
| 196 | <STM32_PINMUX('D',15, AF12)>, /* D01 */ | |
| 197 | <STM32_PINMUX('D',14, AF12)>, /* D00 */ | |
| 198 | ||
| 199 | <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */ | |
| 200 | <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */ | |
| 201 | <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */ | |
| 202 | <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */ | |
| 203 | ||
| 204 | <STM32_PINMUX('G', 5, AF12)>, /* A15-BA1 */ | |
| 205 | <STM32_PINMUX('G', 4, AF12)>, /* A14-BA0 */ | |
| 206 | <STM32_PINMUX('G', 3, AF12)>, /* A13 */ | |
| 207 | <STM32_PINMUX('G', 2, AF12)>, /* A12 */ | |
| 208 | <STM32_PINMUX('G', 1, AF12)>, /* A11 */ | |
| 209 | <STM32_PINMUX('G', 0, AF12)>, /* A10 */ | |
| 210 | <STM32_PINMUX('F',15, AF12)>, /* A09 */ | |
| 211 | <STM32_PINMUX('F',14, AF12)>, /* A08 */ | |
| 212 | <STM32_PINMUX('F',13, AF12)>, /* A07 */ | |
| 213 | <STM32_PINMUX('F',12, AF12)>, /* A06 */ | |
| 214 | <STM32_PINMUX('F', 5, AF12)>, /* A05 */ | |
| 215 | <STM32_PINMUX('F', 4, AF12)>, /* A04 */ | |
| 216 | <STM32_PINMUX('F', 3, AF12)>, /* A03 */ | |
| 217 | <STM32_PINMUX('F', 2, AF12)>, /* A02 */ | |
| 218 | <STM32_PINMUX('F', 1, AF12)>, /* A01 */ | |
| 219 | <STM32_PINMUX('F', 0, AF12)>, /* A00 */ | |
| 220 | ||
| 221 | <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */ | |
| 222 | <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */ | |
| 223 | <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */ | |
| 224 | <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */ | |
| 225 | <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */ | |
| 226 | <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */ | |
| 227 | slew-rate = <2>; | |
| 228 | u-boot,dm-pre-reloc; | |
| 229 | }; | |
| 230 | }; | |
| 231 | }; |