projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 791651e3 PC |
1 | /* |
| 2 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved | |
| 3 | * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. | |
| 4 | * | |
| 5 | * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | */ | |
| 7 | ||
| 8 | #include <dt-bindings/memory/stm32-sdram.h> | |
| 9 | /{ | |
| 10 | clocks { | |
| 11 | u-boot,dm-pre-reloc; | |
| 12 | }; | |
| 13 | ||
| 14 | aliases { | |
| 15 | /* Aliases for gpios so as to use sequence */ | |
| 16 | gpio0 = &gpioa; | |
| 17 | gpio1 = &gpiob; | |
| 18 | gpio2 = &gpioc; | |
| 19 | gpio3 = &gpiod; | |
| 20 | gpio4 = &gpioe; | |
| 21 | gpio5 = &gpiof; | |
| 22 | gpio6 = &gpiog; | |
| 23 | gpio7 = &gpioh; | |
| 24 | gpio8 = &gpioi; | |
| 25 | gpio9 = &gpioj; | |
| 26 | gpio10 = &gpiok; | |
| 27 | }; | |
| 28 | ||
| 29 | soc { | |
| 30 | u-boot,dm-pre-reloc; | |
| 31 | pin-controller { | |
| 32 | u-boot,dm-pre-reloc; | |
| 33 | }; | |
| 34 | ||
| 35 | fmc: fmc@A0000000 { | |
| 36 | compatible = "st,stm32-fmc"; | |
| 37 | reg = <0xA0000000 0x1000>; | |
| 38 | clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; | |
| 39 | pinctrl-0 = <&fmc_pins>; | |
| 40 | pinctrl-names = "default"; | |
| 41 | u-boot,dm-pre-reloc; | |
| 42 | ||
| 43 | /* | |
| 44 | * Memory configuration from sdram datasheet | |
| 45 | * IS42S16400J | |
| 46 | */ | |
| 47 | bank1: bank@1 { | |
| 48 | st,sdram-control = /bits/ 8 <NO_COL_8 | |
| 49 | NO_ROW_12 | |
| 50 | MWIDTH_16 | |
| 51 | BANKS_4 | |
| 52 | CAS_3 | |
| 53 | SDCLK_2 | |
| 54 | RD_BURST_EN | |
| 55 | RD_PIPE_DL_0>; | |
| 56 | st,sdram-timing = /bits/ 8 <TMRD_3 | |
| 57 | TXSR_7 | |
| 58 | TRAS_4 | |
| 59 | TRC_6 | |
| 60 | TWR_2 | |
| 61 | TRP_2 TRCD_2>; | |
| 62 | st,sdram-refcount = < 1386 >; | |
| 63 | }; | |
| 64 | }; | |
| 65 | }; | |
| 66 | }; | |
| 67 | ||
| 68 | &clk_hse { | |
| 69 | u-boot,dm-pre-reloc; | |
| 70 | }; | |
| 71 | ||
| 72 | &clk_lse { | |
| 73 | u-boot,dm-pre-reloc; | |
| 74 | }; | |
| 75 | ||
| 76 | &clk_i2s_ckin { | |
| 77 | u-boot,dm-pre-reloc; | |
| 78 | }; | |
| 79 | ||
| 80 | &pwrcfg { | |
| 81 | u-boot,dm-pre-reloc; | |
| 82 | }; | |
| 83 | ||
| 84 | &rcc { | |
| 85 | u-boot,dm-pre-reloc; | |
| 86 | }; | |
| 87 | ||
| 88 | &gpioa { | |
| 89 | compatible = "st,stm32-gpio"; | |
| 90 | u-boot,dm-pre-reloc; | |
| 91 | }; | |
| 92 | ||
| 93 | &gpiob { | |
| 94 | compatible = "st,stm32-gpio"; | |
| 95 | u-boot,dm-pre-reloc; | |
| 96 | }; | |
| 97 | ||
| 98 | &gpioc { | |
| 99 | compatible = "st,stm32-gpio"; | |
| 100 | u-boot,dm-pre-reloc; | |
| 101 | }; | |
| 102 | ||
| 103 | &gpiod { | |
| 104 | compatible = "st,stm32-gpio"; | |
| 105 | u-boot,dm-pre-reloc; | |
| 106 | }; | |
| 107 | ||
| 108 | &gpioe { | |
| 109 | compatible = "st,stm32-gpio"; | |
| 110 | u-boot,dm-pre-reloc; | |
| 111 | }; | |
| 112 | ||
| 113 | &gpiof { | |
| 114 | compatible = "st,stm32-gpio"; | |
| 115 | u-boot,dm-pre-reloc; | |
| 116 | }; | |
| 117 | ||
| 118 | &gpiog { | |
| 119 | compatible = "st,stm32-gpio"; | |
| 120 | u-boot,dm-pre-reloc; | |
| 121 | }; | |
| 122 | ||
| 123 | &gpioh { | |
| 124 | compatible = "st,stm32-gpio"; | |
| 125 | u-boot,dm-pre-reloc; | |
| 126 | }; | |
| 127 | ||
| 128 | &gpioi { | |
| 129 | compatible = "st,stm32-gpio"; | |
| 130 | u-boot,dm-pre-reloc; | |
| 131 | }; | |
| 132 | ||
| 133 | &gpioj { | |
| 134 | compatible = "st,stm32-gpio"; | |
| 135 | u-boot,dm-pre-reloc; | |
| 136 | }; | |
| 137 | ||
| 138 | &gpiok { | |
| 139 | compatible = "st,stm32-gpio"; | |
| 140 | u-boot,dm-pre-reloc; | |
| 141 | }; | |
| 142 | ||
| 143 | &pinctrl { | |
| 144 | usart1_pins_a: usart1@0 { | |
| 145 | u-boot,dm-pre-reloc; | |
| 146 | pins1 { | |
| 147 | u-boot,dm-pre-reloc; | |
| 148 | }; | |
| 149 | pins2 { | |
| 150 | u-boot,dm-pre-reloc; | |
| 151 | }; | |
| 152 | }; | |
| 153 | ||
| 154 | fmc_pins: fmc@0 { | |
| 155 | u-boot,dm-pre-reloc; | |
| 156 | pins | |
| 157 | { | |
| 158 | pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */ | |
| 159 | <STM32_PINMUX('D', 9, AF12)>, /* D14 */ | |
| 160 | <STM32_PINMUX('D', 8, AF12)>, /* D13 */ | |
| 161 | <STM32_PINMUX('E',15, AF12)>, /* D12 */ | |
| 162 | <STM32_PINMUX('E',14, AF12)>, /* D11 */ | |
| 163 | <STM32_PINMUX('E',13, AF12)>, /* D10 */ | |
| 164 | <STM32_PINMUX('E',12, AF12)>, /* D09 */ | |
| 165 | <STM32_PINMUX('E',11, AF12)>, /* D08 */ | |
| 166 | <STM32_PINMUX('E',10, AF12)>, /* D07 */ | |
| 167 | <STM32_PINMUX('E', 9, AF12)>, /* D06 */ | |
| 168 | <STM32_PINMUX('E', 8, AF12)>, /* D05 */ | |
| 169 | <STM32_PINMUX('E', 7, AF12)>, /* D04 */ | |
| 170 | <STM32_PINMUX('D', 1, AF12)>, /* D03 */ | |
| 171 | <STM32_PINMUX('D', 0, AF12)>, /* D02 */ | |
| 172 | <STM32_PINMUX('D',15, AF12)>, /* D01 */ | |
| 173 | <STM32_PINMUX('D',14, AF12)>, /* D00 */ | |
| 174 | ||
| 175 | <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */ | |
| 176 | <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */ | |
| 177 | ||
| 178 | <STM32_PINMUX('G', 5, AF12)>, /* BA1 */ | |
| 179 | <STM32_PINMUX('G', 4, AF12)>, /* BA0 */ | |
| 180 | ||
| 181 | <STM32_PINMUX('G', 1, AF12)>, /* A11 */ | |
| 182 | <STM32_PINMUX('G', 0, AF12)>, /* A10 */ | |
| 183 | <STM32_PINMUX('F',15, AF12)>, /* A09 */ | |
| 184 | <STM32_PINMUX('F',14, AF12)>, /* A08 */ | |
| 185 | <STM32_PINMUX('F',13, AF12)>, /* A07 */ | |
| 186 | <STM32_PINMUX('F',12, AF12)>, /* A06 */ | |
| 187 | <STM32_PINMUX('F', 5, AF12)>, /* A05 */ | |
| 188 | <STM32_PINMUX('F', 4, AF12)>, /* A04 */ | |
| 189 | <STM32_PINMUX('F', 3, AF12)>, /* A03 */ | |
| 190 | <STM32_PINMUX('F', 2, AF12)>, /* A02 */ | |
| 191 | <STM32_PINMUX('F', 1, AF12)>, /* A01 */ | |
| 192 | <STM32_PINMUX('F', 0, AF12)>, /* A00 */ | |
| 193 | ||
| 194 | <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */ | |
| 195 | <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */ | |
| 196 | <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */ | |
| 197 | <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */ | |
| 198 | <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */ | |
| 199 | <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */ | |
| 200 | slew-rate = <2>; | |
| 201 | u-boot,dm-pre-reloc; | |
| 202 | }; | |
| 203 | }; | |
| 204 | }; |