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Commit | Line | Data |
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b1a8de7e MK |
1 | /* |
2 | * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com> | |
fd198ee1 | 3 | * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com> |
b1a8de7e MK |
4 | * |
5 | * Based on: | |
6 | * stm32f429.dtsi from Linux | |
7 | * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> | |
8 | * | |
9 | * This file is dual-licensed: you can use it either under the terms | |
10 | * of the GPL or the X11 license, at your option. Note that this dual | |
11 | * licensing only applies to this file, and not this project as a | |
12 | * whole. | |
13 | * | |
14 | * a) This file is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of the | |
17 | * License, or (at your option) any later version. | |
18 | * | |
19 | * This file is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * Or, alternatively, | |
25 | * | |
26 | * b) Permission is hereby granted, free of charge, to any person | |
27 | * obtaining a copy of this software and associated documentation | |
28 | * files (the "Software"), to deal in the Software without | |
29 | * restriction, including without limitation the rights to use, | |
30 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
31 | * sell copies of the Software, and to permit persons to whom the | |
32 | * Software is furnished to do so, subject to the following | |
33 | * conditions: | |
34 | * | |
35 | * The above copyright notice and this permission notice shall be | |
36 | * included in all copies or substantial portions of the Software. | |
37 | * | |
38 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
39 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
40 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
41 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
42 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
43 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
44 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
45 | * OTHER DEALINGS IN THE SOFTWARE. | |
46 | */ | |
47 | ||
48 | #include "armv7-m.dtsi" | |
49 | #include <dt-bindings/pinctrl/stm32f746-pinfunc.h> | |
fa87abb6 PC |
50 | #include <dt-bindings/clock/stm32fx-clock.h> |
51 | #include <dt-bindings/mfd/stm32f7-rcc.h> | |
b1a8de7e MK |
52 | |
53 | / { | |
84bfdc17 VM |
54 | clocks { |
55 | clk_hse: clk-hse { | |
56 | #clock-cells = <0>; | |
57 | compatible = "fixed-clock"; | |
58 | clock-frequency = <0>; | |
59 | }; | |
60 | }; | |
61 | ||
b1a8de7e | 62 | soc { |
84bfdc17 | 63 | u-boot,dm-pre-reloc; |
b1a8de7e MK |
64 | mac: ethernet@40028000 { |
65 | compatible = "st,stm32-dwmac"; | |
66 | reg = <0x40028000 0x8000>; | |
67 | reg-names = "stmmaceth"; | |
68 | interrupts = <61>, <62>; | |
69 | interrupt-names = "macirq", "eth_wake_irq"; | |
70 | snps,pbl = <8>; | |
71 | snps,mixed-burst; | |
72 | dma-ranges; | |
73 | status = "disabled"; | |
74 | }; | |
75 | ||
fd198ee1 VM |
76 | fmc: fmc@A0000000 { |
77 | compatible = "st,stm32-fmc"; | |
78 | reg = <0xA0000000 0x1000>; | |
fa87abb6 | 79 | clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; |
fd198ee1 VM |
80 | u-boot,dm-pre-reloc; |
81 | }; | |
82 | ||
b1a8de7e MK |
83 | qspi: quadspi@A0001000 { |
84 | compatible = "st,stm32-qspi"; | |
85 | #address-cells = <1>; | |
86 | #size-cells = <0>; | |
87 | reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; | |
88 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
89 | interrupts = <92>; | |
90 | spi-max-frequency = <108000000>; | |
fa87abb6 | 91 | clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>; |
b1a8de7e MK |
92 | status = "disabled"; |
93 | }; | |
84bfdc17 | 94 | usart1: serial@40011000 { |
1113ad49 | 95 | compatible = "st,stm32f7-usart", "st,stm32f7-uart"; |
84bfdc17 VM |
96 | reg = <0x40011000 0x400>; |
97 | interrupts = <37>; | |
fa87abb6 | 98 | clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>; |
84bfdc17 VM |
99 | status = "disabled"; |
100 | u-boot,dm-pre-reloc; | |
101 | }; | |
d3651aac PC |
102 | |
103 | pwrcfg: power-config@58024800 { | |
104 | compatible = "syscon"; | |
105 | reg = <0x40007000 0x400>; | |
106 | }; | |
107 | ||
84bfdc17 VM |
108 | rcc: rcc@40023810 { |
109 | #reset-cells = <1>; | |
110 | #clock-cells = <2>; | |
1555903c | 111 | compatible = "st,stm32f746-rcc", "st,stm32-rcc"; |
84bfdc17 VM |
112 | reg = <0x40023800 0x400>; |
113 | clocks = <&clk_hse>; | |
d3651aac | 114 | st,syscfg = <&pwrcfg>; |
84bfdc17 VM |
115 | u-boot,dm-pre-reloc; |
116 | }; | |
117 | ||
da4e17f2 VM |
118 | pinctrl: pin-controller { |
119 | #address-cells = <1>; | |
120 | #size-cells = <1>; | |
121 | compatible = "st,stm32f746-pinctrl"; | |
122 | ranges = <0 0x40020000 0x3000>; | |
123 | u-boot,dm-pre-reloc; | |
124 | pins-are-numbered; | |
e34e19fe | 125 | |
d33a6a2f VM |
126 | gpioa: gpio@40020000 { |
127 | gpio-controller; | |
128 | #gpio-cells = <2>; | |
129 | compatible = "st,stm32-gpio"; | |
130 | reg = <0x0 0x400>; | |
fa87abb6 | 131 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; |
d33a6a2f VM |
132 | st,bank-name = "GPIOA"; |
133 | u-boot,dm-pre-reloc; | |
134 | }; | |
135 | ||
136 | gpiob: gpio@40020400 { | |
137 | gpio-controller; | |
138 | #gpio-cells = <2>; | |
139 | compatible = "st,stm32-gpio"; | |
140 | reg = <0x400 0x400>; | |
fa87abb6 | 141 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; |
d33a6a2f VM |
142 | st,bank-name = "GPIOB"; |
143 | u-boot,dm-pre-reloc; | |
144 | }; | |
145 | ||
146 | ||
147 | gpioc: gpio@40020800 { | |
148 | gpio-controller; | |
149 | #gpio-cells = <2>; | |
150 | compatible = "st,stm32-gpio"; | |
151 | reg = <0x800 0x400>; | |
fa87abb6 | 152 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; |
d33a6a2f VM |
153 | st,bank-name = "GPIOC"; |
154 | u-boot,dm-pre-reloc; | |
155 | }; | |
156 | ||
157 | gpiod: gpio@40020c00 { | |
158 | gpio-controller; | |
159 | #gpio-cells = <2>; | |
160 | compatible = "st,stm32-gpio"; | |
161 | reg = <0xc00 0x400>; | |
fa87abb6 | 162 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; |
d33a6a2f VM |
163 | st,bank-name = "GPIOD"; |
164 | u-boot,dm-pre-reloc; | |
165 | }; | |
166 | ||
167 | gpioe: gpio@40021000 { | |
168 | gpio-controller; | |
169 | #gpio-cells = <2>; | |
170 | compatible = "st,stm32-gpio"; | |
171 | reg = <0x1000 0x400>; | |
fa87abb6 | 172 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; |
d33a6a2f VM |
173 | st,bank-name = "GPIOE"; |
174 | u-boot,dm-pre-reloc; | |
175 | }; | |
176 | ||
177 | gpiof: gpio@40021400 { | |
178 | gpio-controller; | |
179 | #gpio-cells = <2>; | |
180 | compatible = "st,stm32-gpio"; | |
181 | reg = <0x1400 0x400>; | |
fa87abb6 | 182 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; |
d33a6a2f VM |
183 | st,bank-name = "GPIOF"; |
184 | u-boot,dm-pre-reloc; | |
185 | }; | |
186 | ||
187 | gpiog: gpio@40021800 { | |
188 | gpio-controller; | |
189 | #gpio-cells = <2>; | |
190 | compatible = "st,stm32-gpio"; | |
191 | reg = <0x1800 0x400>; | |
fa87abb6 | 192 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; |
d33a6a2f VM |
193 | st,bank-name = "GPIOG"; |
194 | u-boot,dm-pre-reloc; | |
195 | }; | |
196 | ||
197 | gpioh: gpio@40021c00 { | |
198 | gpio-controller; | |
199 | #gpio-cells = <2>; | |
200 | compatible = "st,stm32-gpio"; | |
201 | reg = <0x1c00 0x400>; | |
fa87abb6 | 202 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; |
d33a6a2f VM |
203 | st,bank-name = "GPIOH"; |
204 | u-boot,dm-pre-reloc; | |
205 | }; | |
206 | ||
207 | gpioi: gpio@40022000 { | |
208 | gpio-controller; | |
209 | #gpio-cells = <2>; | |
210 | compatible = "st,stm32-gpio"; | |
211 | reg = <0x2000 0x400>; | |
fa87abb6 | 212 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; |
d33a6a2f VM |
213 | st,bank-name = "GPIOI"; |
214 | u-boot,dm-pre-reloc; | |
215 | }; | |
216 | ||
217 | gpioj: gpio@40022400 { | |
218 | gpio-controller; | |
219 | #gpio-cells = <2>; | |
220 | compatible = "st,stm32-gpio"; | |
221 | reg = <0x2400 0x400>; | |
fa87abb6 | 222 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; |
d33a6a2f VM |
223 | st,bank-name = "GPIOJ"; |
224 | u-boot,dm-pre-reloc; | |
225 | }; | |
226 | ||
227 | gpiok: gpio@40022800 { | |
228 | gpio-controller; | |
229 | #gpio-cells = <2>; | |
230 | compatible = "st,stm32-gpio"; | |
231 | reg = <0x2800 0x400>; | |
fa87abb6 | 232 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; |
d33a6a2f VM |
233 | st,bank-name = "GPIOK"; |
234 | u-boot,dm-pre-reloc; | |
235 | }; | |
236 | ||
77729bd7 PC |
237 | sdio_pins: sdio_pins@0 { |
238 | pins { | |
239 | pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>, | |
240 | <STM32F746_PC9_FUNC_SDMMC1_D1>, | |
241 | <STM32F746_PC10_FUNC_SDMMC1_D2>, | |
242 | <STM32F746_PC11_FUNC_SDMMC1_D3>, | |
243 | <STM32F746_PC12_FUNC_SDMMC1_CK>, | |
244 | <STM32F746_PD2_FUNC_SDMMC1_CMD>; | |
245 | drive-push-pull; | |
246 | slew-rate = <2>; | |
247 | }; | |
248 | }; | |
249 | ||
250 | sdio_pins_od: sdio_pins_od@0 { | |
251 | pins1 { | |
252 | pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>, | |
253 | <STM32F746_PC9_FUNC_SDMMC1_D1>, | |
254 | <STM32F746_PC10_FUNC_SDMMC1_D2>, | |
255 | <STM32F746_PC11_FUNC_SDMMC1_D3>, | |
256 | <STM32F746_PC12_FUNC_SDMMC1_CK>; | |
257 | drive-push-pull; | |
258 | slew-rate = <2>; | |
259 | }; | |
260 | ||
261 | pins2 { | |
262 | pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>; | |
263 | drive-open-drain; | |
264 | slew-rate = <2>; | |
265 | }; | |
266 | }; | |
267 | ||
268 | sdio_pins_b: sdio_pins_b@0 { | |
269 | pins { | |
270 | pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>, | |
271 | <STM32F769_PG10_FUNC_SDMMC2_D1>, | |
272 | <STM32F769_PB3_FUNC_SDMMC2_D2>, | |
273 | <STM32F769_PB4_FUNC_SDMMC2_D3>, | |
274 | <STM32F769_PD6_FUNC_SDMMC2_CLK>, | |
275 | <STM32F769_PD7_FUNC_SDMMC2_CMD>; | |
276 | drive-push-pull; | |
277 | slew-rate = <2>; | |
278 | }; | |
279 | }; | |
280 | ||
281 | sdio_pins_od_b: sdio_pins_od_b@0 { | |
282 | pins1 { | |
283 | pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>, | |
284 | <STM32F769_PG10_FUNC_SDMMC2_D1>, | |
285 | <STM32F769_PB3_FUNC_SDMMC2_D2>, | |
286 | <STM32F769_PB4_FUNC_SDMMC2_D3>, | |
287 | <STM32F769_PD6_FUNC_SDMMC2_CLK>; | |
288 | drive-push-pull; | |
289 | slew-rate = <2>; | |
290 | }; | |
291 | ||
292 | pins2 { | |
293 | pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>; | |
294 | drive-open-drain; | |
295 | slew-rate = <2>; | |
296 | }; | |
297 | }; | |
298 | ||
299 | }; | |
300 | sdio: sdio@40012c00 { | |
301 | compatible = "st,stm32f4xx-sdio"; | |
302 | reg = <0x40012c00 0x400>; | |
303 | clocks = <&rcc 0 171>; | |
304 | interrupts = <49>; | |
305 | status = "disabled"; | |
306 | pinctrl-0 = <&sdio_pins>; | |
307 | pinctrl-1 = <&sdio_pins_od>; | |
308 | pinctrl-names = "default", "opendrain"; | |
309 | max-frequency = <48000000>; | |
310 | }; | |
311 | ||
312 | sdio2: sdio2@40011c00 { | |
313 | compatible = "st,stm32f4xx-sdio"; | |
314 | reg = <0x40011c00 0x400>; | |
315 | clocks = <&rcc 0 167>; | |
316 | interrupts = <103>; | |
317 | status = "disabled"; | |
318 | pinctrl-0 = <&sdio_pins_b>; | |
319 | pinctrl-1 = <&sdio_pins_od_b>; | |
320 | pinctrl-names = "default", "opendrain"; | |
321 | max-frequency = <48000000>; | |
da4e17f2 | 322 | }; |
b1a8de7e MK |
323 | }; |
324 | }; | |
325 | ||
326 | &systick { | |
327 | status = "okay"; | |
328 | }; |