[thirdparty/u-boot.git] / arch / arm / dts / stm32mp15-scmi-u-boot.dtsi

// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
 */

/ {
	aliases {
		gpio0 = &gpioa;
		gpio1 = &gpiob;
		gpio2 = &gpioc;
		gpio3 = &gpiod;
		gpio4 = &gpioe;
		gpio5 = &gpiof;
		gpio6 = &gpiog;
		gpio7 = &gpioh;
		gpio8 = &gpioi;
		gpio9 = &gpioj;
		gpio10 = &gpiok;
		gpio25 = &gpioz;
		pinctrl0 = &pinctrl;
		pinctrl1 = &pinctrl_z;
	};

	binman: binman {
		multiple-images;
	};

	soc {
		bootph-all;

		ddr: ddr@5a003000 {
			bootph-all;

			compatible = "st,stm32mp1-ddr";

			reg = <0x5a003000 0x550
			       0x5a004000 0x234>;

			status = "okay";
		};
	};

	/* need PSCI for sysreset during board_f */
	psci {
		bootph-some-ram;
	};
};

&bsec {
	bootph-all;
};

&gpioa {
	bootph-all;
};

&gpiob {
	bootph-all;
};

&gpioc {
	bootph-all;
};

&gpiod {
	bootph-all;
};

&gpioe {
	bootph-all;
};

&gpiof {
	bootph-all;
};

&gpiog {
	bootph-all;
};

&gpioh {
	bootph-all;
};

&gpioi {
	bootph-all;
};

&gpioj {
	bootph-all;
};

&gpiok {
	bootph-all;
};

&gpioz {
	bootph-all;
};

&optee {
	bootph-some-ram;
};

&iwdg2 {
	bootph-all;
};

/* pre-reloc probe = reserve video frame buffer in video_reserve() */
&ltdc {
	bootph-some-ram;
};

/* temp = waiting kernel update */
&m4_rproc {
	resets = <&scmi_reset RST_SCMI_MCU>,
		 <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
	reset-names = "mcu_rst", "hold_boot";
};

&pinctrl {
	bootph-all;
};

&pinctrl_z {
	bootph-all;
};

&rcc {
	bootph-all;
};

&scmi {
	bootph-some-ram;
};

&usart1 {
	resets = <&rcc USART1_R>;
};

&usart2 {
	resets = <&rcc USART2_R>;
};

&usart3 {
	resets = <&rcc USART3_R>;
};

&uart4 {
	resets = <&rcc UART4_R>;
};

&uart5 {
	resets = <&rcc UART5_R>;
};

&usart6 {
	resets = <&rcc USART6_R>;
};

&uart7 {
	resets = <&rcc UART7_R>;
};

&uart8{
	resets = <&rcc UART8_R>;
};
Commit	Line	Data
6cccc8d3 PD	1	// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
	2	/*
	3	* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
	4	*/
	5
	6	/ {
	7	aliases {
	8	gpio0 = &gpioa;
	9	gpio1 = &gpiob;
	10	gpio2 = &gpioc;
	11	gpio3 = &gpiod;
	12	gpio4 = &gpioe;
	13	gpio5 = &gpiof;
	14	gpio6 = &gpiog;
	15	gpio7 = &gpioh;
	16	gpio8 = &gpioi;
	17	gpio9 = &gpioj;
	18	gpio10 = &gpiok;
	19	gpio25 = &gpioz;
	20	pinctrl0 = &pinctrl;
	21	pinctrl1 = &pinctrl_z;
	22	};
	23
	24	binman: binman {
	25	multiple-images;
	26	};
	27
	28	soc {
8c103c33	29	bootph-all;
6cccc8d3 PD	30
6cccc8d3 PD	31	ddr: ddr@5a003000 {
8c103c33	32	bootph-all;
6cccc8d3 PD	33
	34	compatible = "st,stm32mp1-ddr";
	35
	36	reg = <0x5a003000 0x550
	37	0x5a004000 0x234>;
	38
	39	status = "okay";
	40	};
	41	};
	42
	43	/* need PSCI for sysreset during board_f */
	44	psci {
8c103c33	45	bootph-some-ram;
6cccc8d3 PD	46	};
	47	};
	48
	49	&bsec {
8c103c33	50	bootph-all;
6cccc8d3 PD	51	};
	52
	53	&gpioa {
8c103c33	54	bootph-all;
6cccc8d3 PD	55	};
	56
	57	&gpiob {
8c103c33	58	bootph-all;
6cccc8d3 PD	59	};
	60
	61	&gpioc {
8c103c33	62	bootph-all;
6cccc8d3 PD	63	};
	64
	65	&gpiod {
8c103c33	66	bootph-all;
6cccc8d3 PD	67	};
	68
	69	&gpioe {
8c103c33	70	bootph-all;
6cccc8d3 PD	71	};
	72
	73	&gpiof {
8c103c33	74	bootph-all;
6cccc8d3 PD	75	};
	76
	77	&gpiog {
8c103c33	78	bootph-all;
6cccc8d3 PD	79	};
	80
	81	&gpioh {
8c103c33	82	bootph-all;
6cccc8d3 PD	83	};
	84
	85	&gpioi {
8c103c33	86	bootph-all;
6cccc8d3 PD	87	};
	88
	89	&gpioj {
8c103c33	90	bootph-all;
6cccc8d3 PD	91	};
	92
	93	&gpiok {
8c103c33	94	bootph-all;
6cccc8d3 PD	95	};
	96
	97	&gpioz {
8c103c33	98	bootph-all;
6cccc8d3 PD	99	};
	100
	101	&optee {
8c103c33	102	bootph-some-ram;
6cccc8d3 PD	103	};
	104
	105	&iwdg2 {
8c103c33	106	bootph-all;
6cccc8d3 PD	107	};
	108
	109	/* pre-reloc probe = reserve video frame buffer in video_reserve() */
	110	&ltdc {
8c103c33	111	bootph-some-ram;
6cccc8d3 PD	112	};
	113
	114	/* temp = waiting kernel update */
	115	&m4_rproc {
	116	resets = <&scmi_reset RST_SCMI_MCU>,
	117	<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
	118	reset-names = "mcu_rst", "hold_boot";
	119	};
	120
	121	&pinctrl {
8c103c33	122	bootph-all;
6cccc8d3 PD	123	};
	124
	125	&pinctrl_z {
8c103c33	126	bootph-all;
6cccc8d3 PD	127	};
	128
	129	&rcc {
8c103c33	130	bootph-all;
6cccc8d3 PD	131	};
	132
	133	&scmi {
8c103c33	134	bootph-some-ram;
6cccc8d3 PD	135	};
	136
	137	&usart1 {
	138	resets = <&rcc USART1_R>;
	139	};
	140
	141	&usart2 {
	142	resets = <&rcc USART2_R>;
	143	};
	144
	145	&usart3 {
	146	resets = <&rcc USART3_R>;
	147	};
	148
	149	&uart4 {
	150	resets = <&rcc UART4_R>;
	151	};
	152
	153	&uart5 {
	154	resets = <&rcc UART5_R>;
	155	};
	156
	157	&usart6 {
	158	resets = <&rcc USART6_R>;
	159	};
	160
	161	&uart7 {
	162	resets = <&rcc UART7_R>;
	163	};
	164
	165	&uart8{
	166	resets = <&rcc UART8_R>;
	167	};