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Merge git://git.denx.de/u-boot-sunxi
[people/ms/u-boot.git] / arch / arm / dts / tegra20.dtsi
CommitLineData
c3691392 1#include <dt-bindings/clock/tegra20-car.h>
8946034a 2#include <dt-bindings/gpio/tegra-gpio.h>
ee7d755a 3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
8946034a
SG		 4#include <dt-bindings/interrupt-controller/arm-gic.h>
5
6c5be646 6#include "skeleton.dtsi"
c3474ef3
SG		 7
8/ {
9 compatible = "nvidia,tegra20";
ee7d755a 10 interrupt-parent = <&lic>;
c3474ef3 11
ee7d755a 12 host1x@50000000 {
b7723f3f
AM		 13 compatible = "nvidia,tegra20-host1x", "simple-bus";
14 reg = <0x50000000 0x00024000>;
ee7d755a
SG		 15 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
16 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
17 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
18 resets = <&tegra_car 28>;
19 reset-names = "host1x";
b7723f3f
AM		 20
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 ranges = <0x54000000 0x54000000 0x04000000>;
25
ee7d755a
SG		 26 mpe@54040000 {
27 compatible = "nvidia,tegra20-mpe";
b7723f3f 28 reg = <0x54040000 0x00040000>;
ee7d755a
SG		 29 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
30 clocks = <&tegra_car TEGRA20_CLK_MPE>;
31 resets = <&tegra_car 60>;
32 reset-names = "mpe";
b7723f3f
AM		 33 };
34
ee7d755a
SG		 35 vi@54080000 {
36 compatible = "nvidia,tegra20-vi";
b7723f3f 37 reg = <0x54080000 0x00040000>;
ee7d755a
SG		 38 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
39 clocks = <&tegra_car TEGRA20_CLK_VI>;
40 resets = <&tegra_car 20>;
41 reset-names = "vi";
b7723f3f
AM		 42 };
43
ee7d755a
SG		 44 epp@540c0000 {
45 compatible = "nvidia,tegra20-epp";
b7723f3f 46 reg = <0x540c0000 0x00040000>;
ee7d755a
SG		 47 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&tegra_car TEGRA20_CLK_EPP>;
49 resets = <&tegra_car 19>;
50 reset-names = "epp";
b7723f3f
AM		 51 };
52
ee7d755a
SG		 53 isp@54100000 {
54 compatible = "nvidia,tegra20-isp";
b7723f3f 55 reg = <0x54100000 0x00040000>;
ee7d755a
SG		 56 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
57 clocks = <&tegra_car TEGRA20_CLK_ISP>;
58 resets = <&tegra_car 23>;
59 reset-names = "isp";
b7723f3f
AM		 60 };
61
ee7d755a
SG		 62 gr2d@54140000 {
63 compatible = "nvidia,tegra20-gr2d";
b7723f3f 64 reg = <0x54140000 0x00040000>;
ee7d755a
SG		 65 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
66 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
67 resets = <&tegra_car 21>;
68 reset-names = "2d";
b7723f3f
AM		 69 };
70
ee7d755a
SG		 71 gr3d@54180000 {
72 compatible = "nvidia,tegra20-gr3d";
b7723f3f 73 reg = <0x54180000 0x00040000>;
ee7d755a
SG		 74 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
75 resets = <&tegra_car 24>;
76 reset-names = "3d";
b7723f3f
AM		 77 };
78
b7723f3f
AM		 79 dc@54200000 {
80 compatible = "nvidia,tegra20-dc";
81 reg = <0x54200000 0x00040000>;
ee7d755a
SG		 82 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
84 <&tegra_car TEGRA20_CLK_PLL_P>;
85 clock-names = "dc", "parent";
86 resets = <&tegra_car 27>;
87 reset-names = "dc";
88
89 nvidia,head = <0>;
b7723f3f
AM		 90
91 rgb {
92 status = "disabled";
93 };
94 };
95
96 dc@54240000 {
97 compatible = "nvidia,tegra20-dc";
98 reg = <0x54240000 0x00040000>;
ee7d755a
SG		 99 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
101 <&tegra_car TEGRA20_CLK_PLL_P>;
102 clock-names = "dc", "parent";
103 resets = <&tegra_car 26>;
104 reset-names = "dc";
105
106 nvidia,head = <1>;
b7723f3f
AM		 107
108 rgb {
109 status = "disabled";
110 };
111 };
112
ee7d755a 113 hdmi@54280000 {
b7723f3f
AM		 114 compatible = "nvidia,tegra20-hdmi";
115 reg = <0x54280000 0x00040000>;
ee7d755a
SG		 116 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
118 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
119 clock-names = "hdmi", "parent";
120 resets = <&tegra_car 51>;
121 reset-names = "hdmi";
b7723f3f
AM		 122 status = "disabled";
123 };
124
ee7d755a 125 tvo@542c0000 {
b7723f3f
AM		 126 compatible = "nvidia,tegra20-tvo";
127 reg = <0x542c0000 0x00040000>;
ee7d755a
SG		 128 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&tegra_car TEGRA20_CLK_TVO>;
b7723f3f
AM		 130 status = "disabled";
131 };
132
ee7d755a 133 dsi@54300000 {
b7723f3f
AM		 134 compatible = "nvidia,tegra20-dsi";
135 reg = <0x54300000 0x00040000>;
ee7d755a
SG		 136 clocks = <&tegra_car TEGRA20_CLK_DSI>;
137 resets = <&tegra_car 48>;
138 reset-names = "dsi";
b7723f3f
AM		 139 status = "disabled";
140 };
1f1a0212
SG		 141 };
142
ee7d755a
SG		 143 timer@50040600 {
144 compatible = "arm,cortex-a9-twd-timer";
145 interrupt-parent = <&intc>;
146 reg = <0x50040600 0x20>;
147 interrupts = <GIC_PPI 13
50a303bd 148 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
ee7d755a
SG		 149 clocks = <&tegra_car TEGRA20_CLK_TWD>;
150 };
151
c3474ef3 152 intc: interrupt-controller@50041000 {
ee7d755a
SG		 153 compatible = "arm,cortex-a9-gic";
154 reg = <0x50041000 0x1000
155 0x50040100 0x0100>;
c3474ef3 156 interrupt-controller;
ee7d755a
SG		 157 #interrupt-cells = <3>;
158 interrupt-parent = <&intc>;
159 };
160
161 cache-controller@50043000 {
162 compatible = "arm,pl310-cache";
163 reg = <0x50043000 0x1000>;
164 arm,data-latency = <5 5 2>;
165 arm,tag-latency = <4 4 2>;
166 cache-unified;
167 cache-level = <2>;
168 };
169
170 lic: interrupt-controller@60004000 {
171 compatible = "nvidia,tegra20-ictlr";
172 reg = <0x60004000 0x100>,
173 <0x60004100 0x50>,
174 <0x60004200 0x50>,
175 <0x60004300 0x50>;
176 interrupt-controller;
177 #interrupt-cells = <3>;
178 interrupt-parent = <&intc>;
179 };
180
181 timer@60005000 {
182 compatible = "nvidia,tegra20-timer";
183 reg = <0x60005000 0x60>;
184 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
c3474ef3
SG		 189 };
190
b7723f3f
AM		 191 tegra_car: clock@60006000 {
192 compatible = "nvidia,tegra20-car";
193 reg = <0x60006000 0x1000>;
194 #clock-cells = <1>;
ee7d755a
SG		 195 #reset-cells = <1>;
196 };
197
198 flow-controller@60007000 {
199 compatible = "nvidia,tegra20-flowctrl";
200 reg = <0x60007000 0x1000>;
c3474ef3
SG		 201 };
202
ee7d755a 203 apbdma: dma@6000a000 {
64e6ec1d
AM		 204 compatible = "nvidia,tegra20-apbdma";
205 reg = <0x6000a000 0x1200>;
ee7d755a
SG		 206 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
223 resets = <&tegra_car 34>;
224 reset-names = "dma";
225 #dma-cells = <1>;
226 };
227
228 ahb@6000c000 {
229 compatible = "nvidia,tegra20-ahb";
230 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
64e6ec1d
AM		 231 };
232
b7723f3f
AM		 233 gpio: gpio@6000d000 {
234 compatible = "nvidia,tegra20-gpio";
8946034a
SG		 235 reg = <0x6000d000 0x1000>;
236 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
b7723f3f
AM		 243 #gpio-cells = <2>;
244 gpio-controller;
8946034a
SG		 245 #interrupt-cells = <2>;
246 interrupt-controller;
ee7d755a
SG		 247 /*
248 gpio-ranges = <&pinmux 0 0 224>;
249 */
250 };
251
252 apbmisc@70000800 {
253 compatible = "nvidia,tegra20-apbmisc";
254 reg = <0x70000800 0x64 /* Chip revision */
255 0x70000008 0x04>; /* Strapping options */
c3474ef3
SG		 256 };
257
ee7d755a 258 pinmux: pinmux@70000014 {
b7723f3f 259 compatible = "nvidia,tegra20-pinmux";
ee7d755a
SG		 260 reg = <0x70000014 0x10 /* Tri-state registers */
261 0x70000080 0x20 /* Mux registers */
262 0x700000a0 0x14 /* Pull-up/down registers */
263 0x70000868 0xa8>; /* Pad control registers */
c3474ef3
SG		 264 };
265
b7723f3f 266 das@70000c00 {
b7723f3f
AM		 267 compatible = "nvidia,tegra20-das";
268 reg = <0x70000c00 0x80>;
c3474ef3
SG		 269 };
270
ee7d755a
SG		 271 tegra_ac97: ac97@70002000 {
272 compatible = "nvidia,tegra20-ac97";
273 reg = <0x70002000 0x200>;
274 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&tegra_car TEGRA20_CLK_AC97>;
276 resets = <&tegra_car 3>;
277 reset-names = "ac97";
278 dmas = <&apbdma 12>, <&apbdma 12>;
279 dma-names = "rx", "tx";
280 status = "disabled";
281 };
282
283 tegra_i2s1: i2s@70002800 {
c3474ef3
SG		 284 compatible = "nvidia,tegra20-i2s";
285 reg = <0x70002800 0x200>;
ee7d755a
SG		 286 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
288 resets = <&tegra_car 11>;
289 reset-names = "i2s";
290 dmas = <&apbdma 2>, <&apbdma 2>;
291 dma-names = "rx", "tx";
292 status = "disabled";
c3474ef3
SG		 293 };
294
ee7d755a 295 tegra_i2s2: i2s@70002a00 {
c3474ef3
SG		 296 compatible = "nvidia,tegra20-i2s";
297 reg = <0x70002a00 0x200>;
ee7d755a
SG		 298 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
300 resets = <&tegra_car 18>;
301 reset-names = "i2s";
302 dmas = <&apbdma 1>, <&apbdma 1>;
303 dma-names = "rx", "tx";
304 status = "disabled";
c3474ef3
SG		 305 };
306
ee7d755a
SG		 307 /*
308 * There are two serial driver i.e. 8250 based simple serial
309 * driver and APB DMA based serial driver for higher baudrate
310 * and performace. To enable the 8250 based driver, the compatible
311 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
50a303bd 312 * driver, the compatible is "nvidia,tegra20-hsuart".
ee7d755a 313 */
c3691392 314 uarta: serial@70006000 {
c3474ef3
SG		 315 compatible = "nvidia,tegra20-uart";
316 reg = <0x70006000 0x40>;
317 reg-shift = <2>;
c3691392
SG		 318 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
320 resets = <&tegra_car 6>;
321 reset-names = "serial";
322 dmas = <&apbdma 8>, <&apbdma 8>;
323 dma-names = "rx", "tx";
324 status = "disabled";
c3474ef3
SG		 325 };
326
c3691392 327 uartb: serial@70006040 {
c3474ef3
SG		 328 compatible = "nvidia,tegra20-uart";
329 reg = <0x70006040 0x40>;
330 reg-shift = <2>;
c3691392
SG		 331 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
333 resets = <&tegra_car 7>;
334 reset-names = "serial";
335 dmas = <&apbdma 9>, <&apbdma 9>;
336 dma-names = "rx", "tx";
337 status = "disabled";
c3474ef3
SG		 338 };
339
c3691392 340 uartc: serial@70006200 {
c3474ef3
SG		 341 compatible = "nvidia,tegra20-uart";
342 reg = <0x70006200 0x100>;
343 reg-shift = <2>;
c3691392
SG		 344 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
346 resets = <&tegra_car 55>;
347 reset-names = "serial";
348 dmas = <&apbdma 10>, <&apbdma 10>;
349 dma-names = "rx", "tx";
350 status = "disabled";
c3474ef3
SG		 351 };
352
c3691392 353 uartd: serial@70006300 {
c3474ef3
SG		 354 compatible = "nvidia,tegra20-uart";
355 reg = <0x70006300 0x100>;
356 reg-shift = <2>;
c3691392
SG		 357 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
359 resets = <&tegra_car 65>;
360 reset-names = "serial";
361 dmas = <&apbdma 19>, <&apbdma 19>;
362 dma-names = "rx", "tx";
363 status = "disabled";
c3474ef3
SG		 364 };
365
c3691392 366 uarte: serial@70006400 {
c3474ef3
SG		 367 compatible = "nvidia,tegra20-uart";
368 reg = <0x70006400 0x100>;
369 reg-shift = <2>;
c3691392
SG		 370 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
372 resets = <&tegra_car 66>;
373 reset-names = "serial";
374 dmas = <&apbdma 20>, <&apbdma 20>;
375 dma-names = "rx", "tx";
376 status = "disabled";
c3474ef3
SG		 377 };
378
b7723f3f
AM		 379 nand: nand-controller@70008000 {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 compatible = "nvidia,tegra20-nand";
383 reg = <0x70008000 0x100>;
c3474ef3
SG		 384 };
385
b7723f3f
AM		 386 pwm: pwm@7000a000 {
387 compatible = "nvidia,tegra20-pwm";
388 reg = <0x7000a000 0x100>;
389 #pwm-cells = <2>;
ee7d755a
SG		 390 clocks = <&tegra_car TEGRA20_CLK_PWM>;
391 resets = <&tegra_car 17>;
392 reset-names = "pwm";
393 status = "disabled";
394 };
395
396 rtc@7000e000 {
397 compatible = "nvidia,tegra20-rtc";
398 reg = <0x7000e000 0x100>;
399 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&tegra_car TEGRA20_CLK_RTC>;
c3474ef3
SG		 401 };
402
b7723f3f 403 i2c@7000c000 {
ee7d755a
SG		 404 compatible = "nvidia,tegra20-i2c";
405 reg = <0x7000c000 0x100>;
406 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
b7723f3f
AM		 407 #address-cells = <1>;
408 #size-cells = <0>;
ee7d755a
SG		 409 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
410 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
411 clock-names = "div-clk", "fast-clk";
412 resets = <&tegra_car 12>;
413 reset-names = "i2c";
414 dmas = <&apbdma 21>, <&apbdma 21>;
415 dma-names = "rx", "tx";
416 status = "disabled";
c3474ef3
SG		 417 };
418
c98f03fa
AM		 419 spi@7000c380 {
420 compatible = "nvidia,tegra20-sflash";
421 reg = <0x7000c380 0x80>;
ee7d755a 422 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
c98f03fa
AM		 423 #address-cells = <1>;
424 #size-cells = <0>;
ee7d755a
SG		 425 clocks = <&tegra_car TEGRA20_CLK_SPI>;
426 resets = <&tegra_car 43>;
427 reset-names = "spi";
428 dmas = <&apbdma 11>, <&apbdma 11>;
429 dma-names = "rx", "tx";
c98f03fa 430 status = "disabled";
c98f03fa
AM		 431 };
432
b7723f3f 433 i2c@7000c400 {
ee7d755a
SG		 434 compatible = "nvidia,tegra20-i2c";
435 reg = <0x7000c400 0x100>;
436 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
b7723f3f
AM		 437 #address-cells = <1>;
438 #size-cells = <0>;
ee7d755a
SG		 439 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
440 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
441 clock-names = "div-clk", "fast-clk";
442 resets = <&tegra_car 54>;
443 reset-names = "i2c";
444 dmas = <&apbdma 22>, <&apbdma 22>;
445 dma-names = "rx", "tx";
446 status = "disabled";
b7723f3f
AM		 447 };
448
449 i2c@7000c500 {
ee7d755a
SG		 450 compatible = "nvidia,tegra20-i2c";
451 reg = <0x7000c500 0x100>;
452 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
b7723f3f
AM		 453 #address-cells = <1>;
454 #size-cells = <0>;
ee7d755a
SG		 455 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
456 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
457 clock-names = "div-clk", "fast-clk";
458 resets = <&tegra_car 67>;
459 reset-names = "i2c";
460 dmas = <&apbdma 23>, <&apbdma 23>;
461 dma-names = "rx", "tx";
462 status = "disabled";
b7723f3f
AM		 463 };
464
465 i2c@7000d000 {
ee7d755a
SG		 466 compatible = "nvidia,tegra20-i2c-dvc";
467 reg = <0x7000d000 0x200>;
468 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
b7723f3f
AM		 469 #address-cells = <1>;
470 #size-cells = <0>;
ee7d755a
SG		 471 clocks = <&tegra_car TEGRA20_CLK_DVC>,
472 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
473 clock-names = "div-clk", "fast-clk";
474 resets = <&tegra_car 47>;
475 reset-names = "i2c";
476 dmas = <&apbdma 24>, <&apbdma 24>;
477 dma-names = "rx", "tx";
478 status = "disabled";
b7723f3f
AM		 479 };
480
20613c92
MK		 481 spi@7000d400 {
482 compatible = "nvidia,tegra20-slink";
483 reg = <0x7000d400 0x200>;
484 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
485 #address-cells = <1>;
486 #size-cells = <0>;
487 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
488 resets = <&tegra_car 41>;
489 reset-names = "spi";
490 dmas = <&apbdma 15>, <&apbdma 15>;
491 dma-names = "rx", "tx";
492 status = "disabled";
493 };
494
495 spi@7000d600 {
496 compatible = "nvidia,tegra20-slink";
497 reg = <0x7000d600 0x200>;
498 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
499 #address-cells = <1>;
500 #size-cells = <0>;
501 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
502 resets = <&tegra_car 44>;
503 reset-names = "spi";
504 dmas = <&apbdma 16>, <&apbdma 16>;
505 dma-names = "rx", "tx";
506 status = "disabled";
507 };
508
509 spi@7000d800 {
510 compatible = "nvidia,tegra20-slink";
511 reg = <0x7000d800 0x200>;
512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
513 #address-cells = <1>;
514 #size-cells = <0>;
515 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
516 resets = <&tegra_car 46>;
517 reset-names = "spi";
518 dmas = <&apbdma 17>, <&apbdma 17>;
519 dma-names = "rx", "tx";
520 status = "disabled";
521 };
522
523 spi@7000da00 {
524 compatible = "nvidia,tegra20-slink";
525 reg = <0x7000da00 0x200>;
526 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
528 #size-cells = <0>;
529 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
530 resets = <&tegra_car 68>;
531 reset-names = "spi";
532 dmas = <&apbdma 18>, <&apbdma 18>;
533 dma-names = "rx", "tx";
534 status = "disabled";
535 };
536
b7723f3f
AM		 537 kbc@7000e200 {
538 compatible = "nvidia,tegra20-kbc";
ee7d755a
SG		 539 reg = <0x7000e200 0x100>;
540 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&tegra_car TEGRA20_CLK_KBC>;
542 resets = <&tegra_car 36>;
543 reset-names = "kbc";
544 status = "disabled";
b7723f3f
AM		 545 };
546
ee7d755a
SG		 547 pmc@7000e400 {
548 compatible = "nvidia,tegra20-pmc";
549 reg = <0x7000e400 0x400>;
550 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
551 clock-names = "pclk", "clk32k_in";
552 };
553
554 memory-controller@7000f000 {
555 compatible = "nvidia,tegra20-mc";
556 reg = <0x7000f000 0x024
557 0x7000f03c 0x3c4>;
558 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
559 };
560
561 iommu@7000f024 {
562 compatible = "nvidia,tegra20-gart";
563 reg = <0x7000f024 0x00000018 /* controller registers */
564 0x58000000 0x02000000>; /* GART aperture */
565 };
566
567 memory-controller@7000f400 {
b7723f3f
AM		 568 compatible = "nvidia,tegra20-emc";
569 reg = <0x7000f400 0x200>;
ee7d755a
SG		 570 #address-cells = <1>;
571 #size-cells = <0>;
572 };
573
574 fuse@7000f800 {
575 compatible = "nvidia,tegra20-efuse";
576 reg = <0x7000f800 0x400>;
577 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
578 clock-names = "fuse";
579 resets = <&tegra_car 39>;
580 reset-names = "fuse";
c3474ef3
SG		 581 };
582
65d2465d
TR		 583 pcie-controller@80003000 {
584 compatible = "nvidia,tegra20-pcie";
585 device_type = "pci";
586 reg = <0x80003000 0x00000800 /* PADS registers */
587 0x80003800 0x00000200 /* AFI registers */
588 0x90000000 0x10000000>; /* configuration space */
589 reg-names = "pads", "afi", "cs";
590 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
591 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
592 interrupt-names = "intr", "msi";
593
594 #interrupt-cells = <1>;
595 interrupt-map-mask = <0 0 0 0>;
596 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
597
598 bus-range = <0x00 0xff>;
599 #address-cells = <3>;
600 #size-cells = <2>;
601
602 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
603 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
604 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
605 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
606 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
607
608 clocks = <&tegra_car TEGRA20_CLK_PEX>,
609 <&tegra_car TEGRA20_CLK_AFI>,
65d2465d 610 <&tegra_car TEGRA20_CLK_PLL_E>;
ee7d755a
SG		 611 clock-names = "pex", "afi", "pll_e";
612 resets = <&tegra_car 70>,
613 <&tegra_car 72>,
614 <&tegra_car 74>;
615 reset-names = "pex", "afi", "pcie_x";
65d2465d
TR		 616 status = "disabled";
617
618 pci@1,0 {
619 device_type = "pci";
620 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
621 reg = <0x000800 0 0 0 0>;
622 status = "disabled";
623
624 #address-cells = <3>;
625 #size-cells = <2>;
626 ranges;
627
628 nvidia,num-lanes = <2>;
629 };
630
631 pci@2,0 {
632 device_type = "pci";
633 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
634 reg = <0x001000 0 0 0 0>;
635 status = "disabled";
636
637 #address-cells = <3>;
638 #size-cells = <2>;
639 ranges;
640
641 nvidia,num-lanes = <2>;
642 };
643 };
644
c3474ef3
SG		 645 usb@c5000000 {
646 compatible = "nvidia,tegra20-ehci", "usb-ehci";
647 reg = <0xc5000000 0x4000>;
ee7d755a 648 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
c3474ef3 649 phy_type = "utmi";
1c1cce99 650 nvidia,has-legacy-mode;
ee7d755a
SG		 651 clocks = <&tegra_car TEGRA20_CLK_USBD>;
652 resets = <&tegra_car 22>;
653 reset-names = "usb";
654 nvidia,needs-double-reset;
655 nvidia,phy = <&phy1>;
656 status = "disabled";
657 };
658
659 phy1: usb-phy@c5000000 {
660 compatible = "nvidia,tegra20-usb-phy";
661 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
662 phy_type = "utmi";
663 clocks = <&tegra_car TEGRA20_CLK_USBD>,
664 <&tegra_car TEGRA20_CLK_PLL_U>,
665 <&tegra_car TEGRA20_CLK_CLK_M>,
666 <&tegra_car TEGRA20_CLK_USBD>;
667 clock-names = "reg", "pll_u", "timer", "utmi-pads";
668 resets = <&tegra_car 22>, <&tegra_car 22>;
669 reset-names = "usb", "utmi-pads";
670 nvidia,has-legacy-mode;
671 nvidia,hssync-start-delay = <9>;
672 nvidia,idle-wait-delay = <17>;
673 nvidia,elastic-limit = <16>;
674 nvidia,term-range-adj = <6>;
675 nvidia,xcvr-setup = <9>;
676 nvidia,xcvr-lsfslew = <1>;
677 nvidia,xcvr-lsrslew = <1>;
678 nvidia,has-utmi-pad-registers;
679 status = "disabled";
c3474ef3
SG		 680 };
681
682 usb@c5004000 {
683 compatible = "nvidia,tegra20-ehci", "usb-ehci";
684 reg = <0xc5004000 0x4000>;
ee7d755a
SG		 685 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
686 phy_type = "ulpi";
687 clocks = <&tegra_car TEGRA20_CLK_USB2>;
688 resets = <&tegra_car 58>;
689 reset-names = "usb";
690 nvidia,phy = <&phy2>;
691 status = "disabled";
692 };
693
694 phy2: usb-phy@c5004000 {
695 compatible = "nvidia,tegra20-usb-phy";
696 reg = <0xc5004000 0x4000>;
c3474ef3 697 phy_type = "ulpi";
ee7d755a
SG		 698 clocks = <&tegra_car TEGRA20_CLK_USB2>,
699 <&tegra_car TEGRA20_CLK_PLL_U>,
700 <&tegra_car TEGRA20_CLK_CDEV2>;
701 clock-names = "reg", "pll_u", "ulpi-link";
702 resets = <&tegra_car 58>, <&tegra_car 22>;
703 reset-names = "usb", "utmi-pads";
704 status = "disabled";
c3474ef3
SG		 705 };
706
707 usb@c5008000 {
708 compatible = "nvidia,tegra20-ehci", "usb-ehci";
709 reg = <0xc5008000 0x4000>;
ee7d755a
SG		 710 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
711 phy_type = "utmi";
712 clocks = <&tegra_car TEGRA20_CLK_USB3>;
713 resets = <&tegra_car 59>;
714 reset-names = "usb";
715 nvidia,phy = <&phy3>;
716 status = "disabled";
717 };
718
719 phy3: usb-phy@c5008000 {
720 compatible = "nvidia,tegra20-usb-phy";
721 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
c3474ef3 722 phy_type = "utmi";
ee7d755a
SG		 723 clocks = <&tegra_car TEGRA20_CLK_USB3>,
724 <&tegra_car TEGRA20_CLK_PLL_U>,
725 <&tegra_car TEGRA20_CLK_CLK_M>,
726 <&tegra_car TEGRA20_CLK_USBD>;
727 clock-names = "reg", "pll_u", "timer", "utmi-pads";
728 resets = <&tegra_car 59>, <&tegra_car 22>;
729 reset-names = "usb", "utmi-pads";
730 nvidia,hssync-start-delay = <9>;
731 nvidia,idle-wait-delay = <17>;
732 nvidia,elastic-limit = <16>;
733 nvidia,term-range-adj = <6>;
734 nvidia,xcvr-setup = <9>;
735 nvidia,xcvr-lsfslew = <2>;
736 nvidia,xcvr-lsrslew = <2>;
737 status = "disabled";
c3474ef3
SG		 738 };
739
b7723f3f
AM		 740 sdhci@c8000000 {
741 compatible = "nvidia,tegra20-sdhci";
742 reg = <0xc8000000 0x200>;
ee7d755a
SG		 743 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
745 resets = <&tegra_car 14>;
746 reset-names = "sdhci";
126685ad 747 status = "disabled";
8436fbc3 748 };
c6af2e7d 749
b7723f3f
AM		 750 sdhci@c8000200 {
751 compatible = "nvidia,tegra20-sdhci";
752 reg = <0xc8000200 0x200>;
ee7d755a
SG		 753 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
755 resets = <&tegra_car 9>;
756 reset-names = "sdhci";
126685ad 757 status = "disabled";
c6af2e7d 758 };
beca1fde 759
b7723f3f
AM		 760 sdhci@c8000400 {
761 compatible = "nvidia,tegra20-sdhci";
762 reg = <0xc8000400 0x200>;
ee7d755a
SG		 763 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
765 resets = <&tegra_car 69>;
766 reset-names = "sdhci";
126685ad 767 status = "disabled";
beca1fde
SG		 768 };
769
b7723f3f
AM		 770 sdhci@c8000600 {
771 compatible = "nvidia,tegra20-sdhci";
772 reg = <0xc8000600 0x200>;
ee7d755a
SG		 773 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
775 resets = <&tegra_car 15>;
776 reset-names = "sdhci";
126685ad 777 status = "disabled";
eefe3e59 778 };
ee7d755a
SG		 779
780 cpus {
781 #address-cells = <1>;
782 #size-cells = <0>;
783
784 cpu@0 {
785 device_type = "cpu";
786 compatible = "arm,cortex-a9";
787 reg = <0>;
788 };
789
790 cpu@1 {
791 device_type = "cpu";
792 compatible = "arm,cortex-a9";
793 reg = <1>;
794 };
795 };
796
797 pmu {
798 compatible = "arm,cortex-a9-pmu";
799 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
800 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
801 };
c3474ef3 802};
"Das U-Boot" Source Tree