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1674bd1a ST |
1 | /* |
2 | * Cavium Thunder DTS file - Thunder SoC description | |
3 | * | |
4 | * Copyright (C) 2014, Cavium Inc. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ or X11 | |
7 | * | |
8 | */ | |
9 | ||
10 | / { | |
11 | compatible = "cavium,thunder-88xx"; | |
12 | interrupt-parent = <&gic0>; | |
13 | #address-cells = <2>; | |
14 | #size-cells = <2>; | |
15 | ||
16 | psci { | |
17 | compatible = "arm,psci-0.2"; | |
18 | method = "smc"; | |
19 | }; | |
20 | ||
21 | cpus { | |
22 | #address-cells = <2>; | |
23 | #size-cells = <0>; | |
24 | ||
25 | cpu@000 { | |
26 | device_type = "cpu"; | |
27 | compatible = "cavium,thunder", "arm,armv8"; | |
28 | reg = <0x0 0x000>; | |
29 | enable-method = "psci"; | |
30 | }; | |
31 | cpu@001 { | |
32 | device_type = "cpu"; | |
33 | compatible = "cavium,thunder", "arm,armv8"; | |
34 | reg = <0x0 0x001>; | |
35 | enable-method = "psci"; | |
36 | }; | |
37 | cpu@002 { | |
38 | device_type = "cpu"; | |
39 | compatible = "cavium,thunder", "arm,armv8"; | |
40 | reg = <0x0 0x002>; | |
41 | enable-method = "psci"; | |
42 | }; | |
43 | cpu@003 { | |
44 | device_type = "cpu"; | |
45 | compatible = "cavium,thunder", "arm,armv8"; | |
46 | reg = <0x0 0x003>; | |
47 | enable-method = "psci"; | |
48 | }; | |
49 | cpu@004 { | |
50 | device_type = "cpu"; | |
51 | compatible = "cavium,thunder", "arm,armv8"; | |
52 | reg = <0x0 0x004>; | |
53 | enable-method = "psci"; | |
54 | }; | |
55 | cpu@005 { | |
56 | device_type = "cpu"; | |
57 | compatible = "cavium,thunder", "arm,armv8"; | |
58 | reg = <0x0 0x005>; | |
59 | enable-method = "psci"; | |
60 | }; | |
61 | cpu@006 { | |
62 | device_type = "cpu"; | |
63 | compatible = "cavium,thunder", "arm,armv8"; | |
64 | reg = <0x0 0x006>; | |
65 | enable-method = "psci"; | |
66 | }; | |
67 | cpu@007 { | |
68 | device_type = "cpu"; | |
69 | compatible = "cavium,thunder", "arm,armv8"; | |
70 | reg = <0x0 0x007>; | |
71 | enable-method = "psci"; | |
72 | }; | |
73 | cpu@008 { | |
74 | device_type = "cpu"; | |
75 | compatible = "cavium,thunder", "arm,armv8"; | |
76 | reg = <0x0 0x008>; | |
77 | enable-method = "psci"; | |
78 | }; | |
79 | cpu@009 { | |
80 | device_type = "cpu"; | |
81 | compatible = "cavium,thunder", "arm,armv8"; | |
82 | reg = <0x0 0x009>; | |
83 | enable-method = "psci"; | |
84 | }; | |
85 | cpu@00a { | |
86 | device_type = "cpu"; | |
87 | compatible = "cavium,thunder", "arm,armv8"; | |
88 | reg = <0x0 0x00a>; | |
89 | enable-method = "psci"; | |
90 | }; | |
91 | cpu@00b { | |
92 | device_type = "cpu"; | |
93 | compatible = "cavium,thunder", "arm,armv8"; | |
94 | reg = <0x0 0x00b>; | |
95 | enable-method = "psci"; | |
96 | }; | |
97 | cpu@00c { | |
98 | device_type = "cpu"; | |
99 | compatible = "cavium,thunder", "arm,armv8"; | |
100 | reg = <0x0 0x00c>; | |
101 | enable-method = "psci"; | |
102 | }; | |
103 | cpu@00d { | |
104 | device_type = "cpu"; | |
105 | compatible = "cavium,thunder", "arm,armv8"; | |
106 | reg = <0x0 0x00d>; | |
107 | enable-method = "psci"; | |
108 | }; | |
109 | cpu@00e { | |
110 | device_type = "cpu"; | |
111 | compatible = "cavium,thunder", "arm,armv8"; | |
112 | reg = <0x0 0x00e>; | |
113 | enable-method = "psci"; | |
114 | }; | |
115 | cpu@00f { | |
116 | device_type = "cpu"; | |
117 | compatible = "cavium,thunder", "arm,armv8"; | |
118 | reg = <0x0 0x00f>; | |
119 | enable-method = "psci"; | |
120 | }; | |
121 | cpu@100 { | |
122 | device_type = "cpu"; | |
123 | compatible = "cavium,thunder", "arm,armv8"; | |
124 | reg = <0x0 0x100>; | |
125 | enable-method = "psci"; | |
126 | }; | |
127 | cpu@101 { | |
128 | device_type = "cpu"; | |
129 | compatible = "cavium,thunder", "arm,armv8"; | |
130 | reg = <0x0 0x101>; | |
131 | enable-method = "psci"; | |
132 | }; | |
133 | cpu@102 { | |
134 | device_type = "cpu"; | |
135 | compatible = "cavium,thunder", "arm,armv8"; | |
136 | reg = <0x0 0x102>; | |
137 | enable-method = "psci"; | |
138 | }; | |
139 | cpu@103 { | |
140 | device_type = "cpu"; | |
141 | compatible = "cavium,thunder", "arm,armv8"; | |
142 | reg = <0x0 0x103>; | |
143 | enable-method = "psci"; | |
144 | }; | |
145 | cpu@104 { | |
146 | device_type = "cpu"; | |
147 | compatible = "cavium,thunder", "arm,armv8"; | |
148 | reg = <0x0 0x104>; | |
149 | enable-method = "psci"; | |
150 | }; | |
151 | cpu@105 { | |
152 | device_type = "cpu"; | |
153 | compatible = "cavium,thunder", "arm,armv8"; | |
154 | reg = <0x0 0x105>; | |
155 | enable-method = "psci"; | |
156 | }; | |
157 | cpu@106 { | |
158 | device_type = "cpu"; | |
159 | compatible = "cavium,thunder", "arm,armv8"; | |
160 | reg = <0x0 0x106>; | |
161 | enable-method = "psci"; | |
162 | }; | |
163 | cpu@107 { | |
164 | device_type = "cpu"; | |
165 | compatible = "cavium,thunder", "arm,armv8"; | |
166 | reg = <0x0 0x107>; | |
167 | enable-method = "psci"; | |
168 | }; | |
169 | cpu@108 { | |
170 | device_type = "cpu"; | |
171 | compatible = "cavium,thunder", "arm,armv8"; | |
172 | reg = <0x0 0x108>; | |
173 | enable-method = "psci"; | |
174 | }; | |
175 | cpu@109 { | |
176 | device_type = "cpu"; | |
177 | compatible = "cavium,thunder", "arm,armv8"; | |
178 | reg = <0x0 0x109>; | |
179 | enable-method = "psci"; | |
180 | }; | |
181 | cpu@10a { | |
182 | device_type = "cpu"; | |
183 | compatible = "cavium,thunder", "arm,armv8"; | |
184 | reg = <0x0 0x10a>; | |
185 | enable-method = "psci"; | |
186 | }; | |
187 | cpu@10b { | |
188 | device_type = "cpu"; | |
189 | compatible = "cavium,thunder", "arm,armv8"; | |
190 | reg = <0x0 0x10b>; | |
191 | enable-method = "psci"; | |
192 | }; | |
193 | cpu@10c { | |
194 | device_type = "cpu"; | |
195 | compatible = "cavium,thunder", "arm,armv8"; | |
196 | reg = <0x0 0x10c>; | |
197 | enable-method = "psci"; | |
198 | }; | |
199 | cpu@10d { | |
200 | device_type = "cpu"; | |
201 | compatible = "cavium,thunder", "arm,armv8"; | |
202 | reg = <0x0 0x10d>; | |
203 | enable-method = "psci"; | |
204 | }; | |
205 | cpu@10e { | |
206 | device_type = "cpu"; | |
207 | compatible = "cavium,thunder", "arm,armv8"; | |
208 | reg = <0x0 0x10e>; | |
209 | enable-method = "psci"; | |
210 | }; | |
211 | cpu@10f { | |
212 | device_type = "cpu"; | |
213 | compatible = "cavium,thunder", "arm,armv8"; | |
214 | reg = <0x0 0x10f>; | |
215 | enable-method = "psci"; | |
216 | }; | |
217 | cpu@200 { | |
218 | device_type = "cpu"; | |
219 | compatible = "cavium,thunder", "arm,armv8"; | |
220 | reg = <0x0 0x200>; | |
221 | enable-method = "psci"; | |
222 | }; | |
223 | cpu@201 { | |
224 | device_type = "cpu"; | |
225 | compatible = "cavium,thunder", "arm,armv8"; | |
226 | reg = <0x0 0x201>; | |
227 | enable-method = "psci"; | |
228 | }; | |
229 | cpu@202 { | |
230 | device_type = "cpu"; | |
231 | compatible = "cavium,thunder", "arm,armv8"; | |
232 | reg = <0x0 0x202>; | |
233 | enable-method = "psci"; | |
234 | }; | |
235 | cpu@203 { | |
236 | device_type = "cpu"; | |
237 | compatible = "cavium,thunder", "arm,armv8"; | |
238 | reg = <0x0 0x203>; | |
239 | enable-method = "psci"; | |
240 | }; | |
241 | cpu@204 { | |
242 | device_type = "cpu"; | |
243 | compatible = "cavium,thunder", "arm,armv8"; | |
244 | reg = <0x0 0x204>; | |
245 | enable-method = "psci"; | |
246 | }; | |
247 | cpu@205 { | |
248 | device_type = "cpu"; | |
249 | compatible = "cavium,thunder", "arm,armv8"; | |
250 | reg = <0x0 0x205>; | |
251 | enable-method = "psci"; | |
252 | }; | |
253 | cpu@206 { | |
254 | device_type = "cpu"; | |
255 | compatible = "cavium,thunder", "arm,armv8"; | |
256 | reg = <0x0 0x206>; | |
257 | enable-method = "psci"; | |
258 | }; | |
259 | cpu@207 { | |
260 | device_type = "cpu"; | |
261 | compatible = "cavium,thunder", "arm,armv8"; | |
262 | reg = <0x0 0x207>; | |
263 | enable-method = "psci"; | |
264 | }; | |
265 | cpu@208 { | |
266 | device_type = "cpu"; | |
267 | compatible = "cavium,thunder", "arm,armv8"; | |
268 | reg = <0x0 0x208>; | |
269 | enable-method = "psci"; | |
270 | }; | |
271 | cpu@209 { | |
272 | device_type = "cpu"; | |
273 | compatible = "cavium,thunder", "arm,armv8"; | |
274 | reg = <0x0 0x209>; | |
275 | enable-method = "psci"; | |
276 | }; | |
277 | cpu@20a { | |
278 | device_type = "cpu"; | |
279 | compatible = "cavium,thunder", "arm,armv8"; | |
280 | reg = <0x0 0x20a>; | |
281 | enable-method = "psci"; | |
282 | }; | |
283 | cpu@20b { | |
284 | device_type = "cpu"; | |
285 | compatible = "cavium,thunder", "arm,armv8"; | |
286 | reg = <0x0 0x20b>; | |
287 | enable-method = "psci"; | |
288 | }; | |
289 | cpu@20c { | |
290 | device_type = "cpu"; | |
291 | compatible = "cavium,thunder", "arm,armv8"; | |
292 | reg = <0x0 0x20c>; | |
293 | enable-method = "psci"; | |
294 | }; | |
295 | cpu@20d { | |
296 | device_type = "cpu"; | |
297 | compatible = "cavium,thunder", "arm,armv8"; | |
298 | reg = <0x0 0x20d>; | |
299 | enable-method = "psci"; | |
300 | }; | |
301 | cpu@20e { | |
302 | device_type = "cpu"; | |
303 | compatible = "cavium,thunder", "arm,armv8"; | |
304 | reg = <0x0 0x20e>; | |
305 | enable-method = "psci"; | |
306 | }; | |
307 | cpu@20f { | |
308 | device_type = "cpu"; | |
309 | compatible = "cavium,thunder", "arm,armv8"; | |
310 | reg = <0x0 0x20f>; | |
311 | enable-method = "psci"; | |
312 | }; | |
313 | }; | |
314 | ||
315 | timer { | |
316 | compatible = "arm,armv8-timer"; | |
317 | interrupts = <1 13 0xff01>, | |
318 | <1 14 0xff01>, | |
319 | <1 11 0xff01>, | |
320 | <1 10 0xff01>; | |
321 | }; | |
322 | ||
323 | soc { | |
324 | compatible = "simple-bus"; | |
325 | #address-cells = <2>; | |
326 | #size-cells = <2>; | |
327 | ranges; | |
328 | ||
329 | refclk50mhz: refclk50mhz { | |
330 | compatible = "fixed-clock"; | |
331 | #clock-cells = <0>; | |
332 | clock-frequency = <50000000>; | |
333 | clock-output-names = "refclk50mhz"; | |
334 | }; | |
335 | ||
336 | gic0: interrupt-controller@8010,00000000 { | |
337 | compatible = "arm,gic-v3"; | |
338 | #interrupt-cells = <3>; | |
339 | interrupt-controller; | |
340 | reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */ | |
341 | <0x8010 0x80000000 0x0 0x600000>; /* GICR */ | |
342 | interrupts = <1 9 0xf04>; | |
343 | }; | |
344 | ||
345 | uaa0: serial@87e0,24000000 { | |
346 | compatible = "arm,pl011", "arm,primecell"; | |
347 | reg = <0x87e0 0x24000000 0x0 0x1000>; | |
348 | interrupts = <1 21 4>; | |
349 | clocks = <&refclk50mhz>; | |
350 | clock-names = "apb_pclk"; | |
746f985a | 351 | uboot,skip-init; |
1674bd1a ST |
352 | }; |
353 | ||
354 | uaa1: serial@87e0,25000000 { | |
355 | compatible = "arm,pl011", "arm,primecell"; | |
356 | reg = <0x87e0 0x25000000 0x0 0x1000>; | |
357 | interrupts = <1 22 4>; | |
358 | clocks = <&refclk50mhz>; | |
359 | clock-names = "apb_pclk"; | |
746f985a | 360 | uboot,skip-init; |
1674bd1a ST |
361 | }; |
362 | }; | |
363 | }; |